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Rev 1129 Rev 1179
Line 25... Line 25...
25
 *          Alex Deucher
25
 *          Alex Deucher
26
 *          Jerome Glisse
26
 *          Jerome Glisse
27
 */
27
 */
28
//#include 
28
//#include 
Line 29... Line 29...
29
 
29
 
30
#include 
30
#include 
31
#include 
31
#include 
32
#include "radeon_drm.h"
32
#include "radeon_drm.h"
33
#include "radeon_reg.h"
33
#include "radeon_reg.h"
34
#include "radeon.h"
34
#include "radeon.h"
35
#include "radeon_asic.h"
35
#include "radeon_asic.h"
Line 41... Line 41...
41
int radeon_r4xx_atom = 0;
41
int radeon_r4xx_atom = 0;
42
int radeon_agpmode   = -1;
42
int radeon_agpmode   = -1;
43
int radeon_gart_size = 512; /* default gart size */
43
int radeon_gart_size = 512; /* default gart size */
44
int radeon_benchmarking = 0;
44
int radeon_benchmarking = 0;
45
int radeon_connector_table = 0;
45
int radeon_connector_table = 0;
-
 
46
int radeon_tv = 1;
Line 46... Line 47...
46
 
47
 
47
 
48
 
48
/*
49
/*
49
 * Clear GPU surface registers.
50
 * Clear GPU surface registers.
50
 */
51
 */
51
static void radeon_surface_init(struct radeon_device *rdev)
52
void radeon_surface_init(struct radeon_device *rdev)
Line 52... Line 53...
52
{
53
{
53
    dbgprintf("%s\n",__FUNCTION__);
54
    ENTER();
54
 
55
 
Line 55... Line 56...
55
    /* FIXME: check this out */
56
    /* FIXME: check this out */
56
    if (rdev->family < CHIP_R600) {
57
    if (rdev->family < CHIP_R600) {
57
        int i;
58
        int i;
58
 
59
 
59
        for (i = 0; i < 8; i++) {
60
        for (i = 0; i < 8; i++) {
-
 
61
            WREG32(RADEON_SURFACE0_INFO +
-
 
62
                   i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
60
            WREG32(RADEON_SURFACE0_INFO +
63
                   0);
61
                   i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
64
        }
Line 62... Line 65...
62
                   0);
65
		/* enable surfaces */
63
        }
66
		WREG32(RADEON_SURFACE_CNTL, 0);
64
    }
67
    }
65
}
68
}
66
 
69
 
67
/*
70
/*
Line 68... Line 71...
68
 * GPU scratch registers helpers function.
71
 * GPU scratch registers helpers function.
69
 */
72
 */
Line 130... Line 133...
130
	 * address space).
133
	 * address space).
131
	 */
134
	 */
132
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
135
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
133
		/* vram location was already setup try to put gtt after
136
		/* vram location was already setup try to put gtt after
134
		 * if it fits */
137
		 * if it fits */
135
		tmp = rdev->mc.vram_location + rdev->mc.vram_size;
138
		tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
136
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
139
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
137
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
140
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
138
			rdev->mc.gtt_location = tmp;
141
			rdev->mc.gtt_location = tmp;
139
		} else {
142
		} else {
140
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
143
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
Line 145... Line 148...
145
			rdev->mc.gtt_location = 0;
148
			rdev->mc.gtt_location = 0;
146
		}
149
		}
147
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
150
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
148
		/* gtt location was already setup try to put vram before
151
		/* gtt location was already setup try to put vram before
149
		 * if it fits */
152
		 * if it fits */
150
		if (rdev->mc.vram_size < rdev->mc.gtt_location) {
153
		if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
151
			rdev->mc.vram_location = 0;
154
			rdev->mc.vram_location = 0;
152
		} else {
155
		} else {
153
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
156
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
154
			tmp += (rdev->mc.vram_size - 1);
157
			tmp += (rdev->mc.mc_vram_size - 1);
155
			tmp &= ~(rdev->mc.vram_size - 1);
158
			tmp &= ~(rdev->mc.mc_vram_size - 1);
156
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
159
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
157
				rdev->mc.vram_location = tmp;
160
				rdev->mc.vram_location = tmp;
158
			} else {
161
			} else {
159
				printk(KERN_ERR "[drm] vram too big to fit "
162
				printk(KERN_ERR "[drm] vram too big to fit "
160
				       "before or after GTT location.\n");
163
				       "before or after GTT location.\n");
161
				return -EINVAL;
164
				return -EINVAL;
162
			}
165
			}
163
		}
166
		}
164
	} else {
167
	} else {
165
		rdev->mc.vram_location = 0;
168
		rdev->mc.vram_location = 0;
-
 
169
		tmp = rdev->mc.mc_vram_size;
-
 
170
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
166
		rdev->mc.gtt_location = rdev->mc.vram_size;
171
		rdev->mc.gtt_location = tmp;
167
	}
172
	}
-
 
173
	rdev->mc.vram_start = rdev->mc.vram_location;
-
 
174
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-
 
175
	rdev->mc.gtt_start = rdev->mc.gtt_location;
-
 
176
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
168
	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
177
	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
169
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
178
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
170
		 rdev->mc.vram_location,
179
		 (unsigned)rdev->mc.vram_location,
171
		 rdev->mc.vram_location + rdev->mc.vram_size - 1);
180
		 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
172
	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
181
	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
173
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
182
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
174
		 rdev->mc.gtt_location,
183
		 (unsigned)rdev->mc.gtt_location,
175
		 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
184
		 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
176
	return 0;
185
	return 0;
177
}
186
}
Line 178... Line 187...
178
 
187
 
179
 
188
 
180
/*
189
/*
181
 * GPU helpers function.
190
 * GPU helpers function.
182
 */
191
 */
183
static bool radeon_card_posted(struct radeon_device *rdev)
192
bool radeon_card_posted(struct radeon_device *rdev)
Line 184... Line 193...
184
{
193
{
Line 185... Line 194...
185
	uint32_t reg;
194
	uint32_t reg;
186
 
195
 
187
    dbgprintf("%s\n",__FUNCTION__);
196
    ENTER();
188
 
197
 
Line 232... Line 241...
232
    BUG_ON(1);
241
    BUG_ON(1);
233
}
242
}
Line 234... Line 243...
234
 
243
 
235
void radeon_register_accessor_init(struct radeon_device *rdev)
244
void radeon_register_accessor_init(struct radeon_device *rdev)
236
{
-
 
237
 
-
 
238
    dbgprintf("%s\n",__FUNCTION__);
-
 
239
 
-
 
240
    rdev->mm_rreg = &r100_mm_rreg;
-
 
241
    rdev->mm_wreg = &r100_mm_wreg;
245
{
242
    rdev->mc_rreg = &radeon_invalid_rreg;
246
    rdev->mc_rreg = &radeon_invalid_rreg;
243
    rdev->mc_wreg = &radeon_invalid_wreg;
247
    rdev->mc_wreg = &radeon_invalid_wreg;
244
    rdev->pll_rreg = &radeon_invalid_rreg;
248
    rdev->pll_rreg = &radeon_invalid_rreg;
245
    rdev->pll_wreg = &radeon_invalid_wreg;
-
 
246
    rdev->pcie_rreg = &radeon_invalid_rreg;
-
 
247
    rdev->pcie_wreg = &radeon_invalid_wreg;
249
    rdev->pll_wreg = &radeon_invalid_wreg;
248
    rdev->pciep_rreg = &radeon_invalid_rreg;
250
    rdev->pciep_rreg = &radeon_invalid_rreg;
Line 249... Line 251...
249
    rdev->pciep_wreg = &radeon_invalid_wreg;
251
    rdev->pciep_wreg = &radeon_invalid_wreg;
250
 
252
 
251
    /* Don't change order as we are overridding accessor. */
-
 
252
    if (rdev->family < CHIP_RV515) {
253
    /* Don't change order as we are overridding accessor. */
253
        rdev->pcie_rreg = &rv370_pcie_rreg;
254
    if (rdev->family < CHIP_RV515) {
254
        rdev->pcie_wreg = &rv370_pcie_wreg;
-
 
255
    }
-
 
256
    if (rdev->family >= CHIP_RV515) {
255
		rdev->pcie_reg_mask = 0xff;
257
        rdev->pcie_rreg = &rv515_pcie_rreg;
256
	} else {
258
        rdev->pcie_wreg = &rv515_pcie_wreg;
257
		rdev->pcie_reg_mask = 0x7ff;
259
    }
258
    }
260
    /* FIXME: not sure here */
259
    /* FIXME: not sure here */
261
    if (rdev->family <= CHIP_R580) {
260
    if (rdev->family <= CHIP_R580) {
262
        rdev->pll_rreg = &r100_pll_rreg;
261
        rdev->pll_rreg = &r100_pll_rreg;
-
 
262
        rdev->pll_wreg = &r100_pll_wreg;
-
 
263
    }
-
 
264
	if (rdev->family >= CHIP_R420) {
-
 
265
		rdev->mc_rreg = &r420_mc_rreg;
263
        rdev->pll_wreg = &r100_pll_wreg;
266
		rdev->mc_wreg = &r420_mc_wreg;
264
    }
267
	}
265
    if (rdev->family >= CHIP_RV515) {
268
    if (rdev->family >= CHIP_RV515) {
266
        rdev->mc_rreg = &rv515_mc_rreg;
269
        rdev->mc_rreg = &rv515_mc_rreg;
267
        rdev->mc_wreg = &rv515_mc_wreg;
270
        rdev->mc_wreg = &rv515_mc_wreg;
268
    }
271
    }
269
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
272
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
270
        rdev->mc_rreg = &rs400_mc_rreg;
273
        rdev->mc_rreg = &rs400_mc_rreg;
271
        rdev->mc_wreg = &rs400_mc_wreg;
274
        rdev->mc_wreg = &rs400_mc_wreg;
272
    }
275
    }
273
    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
276
//    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
274
        rdev->mc_rreg = &rs690_mc_rreg;
277
//        rdev->mc_rreg = &rs690_mc_rreg;
275
        rdev->mc_wreg = &rs690_mc_wreg;
278
//        rdev->mc_wreg = &rs690_mc_wreg;
276
    }
279
//    }
277
    if (rdev->family == CHIP_RS600) {
280
//    if (rdev->family == CHIP_RS600) {
278
        rdev->mc_rreg = &rs600_mc_rreg;
281
//        rdev->mc_rreg = &rs600_mc_rreg;
279
        rdev->mc_wreg = &rs600_mc_wreg;
282
//        rdev->mc_wreg = &rs600_mc_wreg;
280
    }
283
//    }
281
    if (rdev->family >= CHIP_R600) {
284
//    if (rdev->family >= CHIP_R600) {
282
        rdev->pciep_rreg = &r600_pciep_rreg;
285
//        rdev->pciep_rreg = &r600_pciep_rreg;
283
        rdev->pciep_wreg = &r600_pciep_wreg;
286
//        rdev->pciep_wreg = &r600_pciep_wreg;
Line 284... Line 287...
284
    }
287
//    }
285
}
288
}
286
 
289
 
287
 
290
 
288
/*
291
/*
289
 * ASIC
-
 
290
 */
-
 
291
int radeon_asic_init(struct radeon_device *rdev)
-
 
292
{
292
 * ASIC
293
 
293
 */
294
    dbgprintf("%s\n",__FUNCTION__);
294
int radeon_asic_init(struct radeon_device *rdev)
295
 
295
{
296
    radeon_register_accessor_init(rdev);
296
    radeon_register_accessor_init(rdev);
Line 309... Line 309...
309
	case CHIP_R300:
309
	case CHIP_R300:
310
	case CHIP_R350:
310
	case CHIP_R350:
311
	case CHIP_RV350:
311
	case CHIP_RV350:
312
	case CHIP_RV380:
312
	case CHIP_RV380:
313
        rdev->asic = &r300_asic;
313
        rdev->asic = &r300_asic;
-
 
314
		if (rdev->flags & RADEON_IS_PCIE) {
-
 
315
			rdev->asic->gart_init = &rv370_pcie_gart_init;
-
 
316
			rdev->asic->gart_fini = &rv370_pcie_gart_fini;
-
 
317
			rdev->asic->gart_enable = &rv370_pcie_gart_enable;
-
 
318
			rdev->asic->gart_disable = &rv370_pcie_gart_disable;
-
 
319
			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-
 
320
			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
-
 
321
		}
314
		break;
322
		break;
315
	case CHIP_R420:
323
	case CHIP_R420:
316
	case CHIP_R423:
324
	case CHIP_R423:
317
	case CHIP_RV410:
325
	case CHIP_RV410:
318
        rdev->asic = &r420_asic;
326
        rdev->asic = &r420_asic;
Line 320... Line 328...
320
	case CHIP_RS400:
328
	case CHIP_RS400:
321
	case CHIP_RS480:
329
	case CHIP_RS480:
322
       rdev->asic = &rs400_asic;
330
       rdev->asic = &rs400_asic;
323
		break;
331
		break;
324
	case CHIP_RS600:
332
	case CHIP_RS600:
325
       rdev->asic = &rs600_asic;
333
//       rdev->asic = &rs600_asic;
326
		break;
334
		break;
327
	case CHIP_RS690:
335
	case CHIP_RS690:
328
	case CHIP_RS740:
336
	case CHIP_RS740:
329
        rdev->asic = &rs690_asic;
337
//        rdev->asic = &rs690_asic;
330
		break;
338
		break;
331
	case CHIP_RV515:
339
	case CHIP_RV515:
332
        rdev->asic = &rv515_asic;
340
        rdev->asic = &rv515_asic;
333
		break;
341
		break;
334
	case CHIP_R520:
342
	case CHIP_R520:
Line 361... Line 369...
361
 */
369
 */
362
int radeon_clocks_init(struct radeon_device *rdev)
370
int radeon_clocks_init(struct radeon_device *rdev)
363
{
371
{
364
	int r;
372
	int r;
Line 365... Line 373...
365
 
373
 
Line 366... Line -...
366
    dbgprintf("%s\n",__FUNCTION__);
-
 
367
 
374
    ENTER();
368
    radeon_get_clock_info(rdev->ddev);
375
 
369
    r = radeon_static_clocks_init(rdev->ddev);
376
    r = radeon_static_clocks_init(rdev->ddev);
370
	if (r) {
377
	if (r) {
371
		return r;
378
		return r;
Line 437... Line 444...
437
    .pll_write = cail_pll_write,
444
    .pll_write = cail_pll_write,
438
};
445
};
Line 439... Line 446...
439
 
446
 
440
int radeon_atombios_init(struct radeon_device *rdev)
447
int radeon_atombios_init(struct radeon_device *rdev)
441
{
448
{
Line 442... Line 449...
442
    dbgprintf("%s\n",__FUNCTION__);
449
    ENTER();
443
 
450
 
444
    atom_card_info.dev = rdev->ddev;
451
    atom_card_info.dev = rdev->ddev;
445
    rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
452
    rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
Line 463... Line 470...
463
}
470
}
Line 464... Line 471...
464
 
471
 
465
int radeon_modeset_init(struct radeon_device *rdev);
472
int radeon_modeset_init(struct radeon_device *rdev);
Line -... Line 473...
-
 
473
void radeon_modeset_fini(struct radeon_device *rdev);
466
void radeon_modeset_fini(struct radeon_device *rdev);
474
 
467
 
475
 
468
/*
476
/*
469
 * Radeon device.
477
 * Radeon device.
470
 */
478
 */
471
int radeon_device_init(struct radeon_device *rdev,
479
int radeon_device_init(struct radeon_device *rdev,
472
               struct drm_device *ddev,
480
               struct drm_device *ddev,
473
               struct pci_dev *pdev,
481
               struct pci_dev *pdev,
474
               uint32_t flags)
482
               uint32_t flags)
-
 
483
{
Line 475... Line 484...
475
{
484
	int r, ret;
Line 476... Line 485...
476
	int r, ret;
485
	int dma_bits;
477
 
486
 
478
    dbgprintf("%s\n",__FUNCTION__);
487
    ENTER();
479
 
488
 
Line 492... Line 501...
492
 //   mutex_init(&rdev->cs_mutex);
501
 //   mutex_init(&rdev->cs_mutex);
493
 //   mutex_init(&rdev->ib_pool.mutex);
502
 //   mutex_init(&rdev->ib_pool.mutex);
494
 //   mutex_init(&rdev->cp.mutex);
503
 //   mutex_init(&rdev->cp.mutex);
495
 //   rwlock_init(&rdev->fence_drv.lock);
504
 //   rwlock_init(&rdev->fence_drv.lock);
Line -... Line 505...
-
 
505
 
-
 
506
	/* Set asic functions */
-
 
507
	r = radeon_asic_init(rdev);
-
 
508
	if (r) {
-
 
509
		return r;
-
 
510
	}
496
 
511
 
497
    if (radeon_agpmode == -1) {
512
    if (radeon_agpmode == -1) {
498
        rdev->flags &= ~RADEON_IS_AGP;
513
        rdev->flags &= ~RADEON_IS_AGP;
499
        if (rdev->family > CHIP_RV515 ||
514
		if (rdev->family >= CHIP_RV515 ||
500
            rdev->family == CHIP_RV380 ||
515
            rdev->family == CHIP_RV380 ||
501
            rdev->family == CHIP_RV410 ||
516
            rdev->family == CHIP_RV410 ||
502
            rdev->family == CHIP_R423) {
517
            rdev->family == CHIP_R423) {
503
            DRM_INFO("Forcing AGP to PCIE mode\n");
518
            DRM_INFO("Forcing AGP to PCIE mode\n");
-
 
519
            rdev->flags |= RADEON_IS_PCIE;
-
 
520
			rdev->asic->gart_init = &rv370_pcie_gart_init;
-
 
521
			rdev->asic->gart_fini = &rv370_pcie_gart_fini;
-
 
522
			rdev->asic->gart_enable = &rv370_pcie_gart_enable;
-
 
523
			rdev->asic->gart_disable = &rv370_pcie_gart_disable;
-
 
524
			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
504
            rdev->flags |= RADEON_IS_PCIE;
525
			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
505
        } else {
526
        } else {
506
            DRM_INFO("Forcing AGP to PCI mode\n");
527
            DRM_INFO("Forcing AGP to PCI mode\n");
-
 
528
            rdev->flags |= RADEON_IS_PCI;
-
 
529
			rdev->asic->gart_init = &r100_pci_gart_init;
-
 
530
			rdev->asic->gart_fini = &r100_pci_gart_fini;
-
 
531
			rdev->asic->gart_enable = &r100_pci_gart_enable;
-
 
532
			rdev->asic->gart_disable = &r100_pci_gart_disable;
-
 
533
			rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
507
            rdev->flags |= RADEON_IS_PCI;
534
			rdev->asic->gart_set_page = &r100_pci_gart_set_page;
508
        }
535
        }
Line -... Line 536...
-
 
536
    }
509
    }
537
 
510
 
538
	/* set DMA mask + need_dma32 flags.
511
    /* Set asic functions */
539
	 * PCIE - can handle 40-bits.
512
    r = radeon_asic_init(rdev);
540
	 * IGP - can handle 40-bits (in theory)
513
    if (r) {
541
	 * AGP - generally dma32 is safest
514
        return r;
-
 
-
 
542
	 * PCI - only dma32
-
 
543
	 */
-
 
544
	rdev->need_dma32 = false;
515
    }
545
	if (rdev->flags & RADEON_IS_AGP)
-
 
546
		rdev->need_dma32 = true;
Line 516... Line -...
516
 
-
 
517
    r = rdev->asic->init(rdev);
-
 
518
 
-
 
519
    if (r) {
-
 
520
        return r;
547
	if (rdev->flags & RADEON_IS_PCI)
521
    }
548
		rdev->need_dma32 = true;
522
 
549
 
523
    /* Report DMA addressing limitation */
550
	dma_bits = rdev->need_dma32 ? 32 : 40;
524
    r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
551
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
Line 525... Line 552...
525
    if (r) {
552
    if (r) {
Line 539... Line 566...
539
        return -ENOMEM;
566
        return -ENOMEM;
540
    }
567
    }
541
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
568
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
542
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
569
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
Line -... Line 570...
-
 
570
 
-
 
571
	rdev->new_init_path = false;
-
 
572
	r = radeon_init(rdev);
-
 
573
	if (r) {
-
 
574
		return r;
-
 
575
	}
-
 
576
 
543
 
577
	if (!rdev->new_init_path) {
544
    /* Setup errata flags */
578
    /* Setup errata flags */
545
    radeon_errata(rdev);
579
    radeon_errata(rdev);
546
    /* Initialize scratch registers */
580
    /* Initialize scratch registers */
547
    radeon_scratch_init(rdev);
581
    radeon_scratch_init(rdev);
548
	/* Initialize surface registers */
582
	/* Initialize surface registers */
Line 549... Line -...
549
    radeon_surface_init(rdev);
-
 
550
 
583
    radeon_surface_init(rdev);
551
    /* TODO: disable VGA need to use VGA request */
584
 
552
    /* BIOS*/
585
    /* BIOS*/
553
    if (!radeon_get_bios(rdev)) {
586
    if (!radeon_get_bios(rdev)) {
554
        if (ASIC_IS_AVIVO(rdev))
587
        if (ASIC_IS_AVIVO(rdev))
Line 576... Line 609...
576
            atom_asic_init(rdev->mode_info.atom_context);
609
            atom_asic_init(rdev->mode_info.atom_context);
577
        } else {
610
        } else {
578
			radeon_combios_asic_init(rdev->ddev);
611
			radeon_combios_asic_init(rdev->ddev);
579
        }
612
        }
580
    }
613
    }
581
    /* Get vram informations */
614
		/* Get clock & vram information */
-
 
615
		radeon_get_clock_info(rdev->ddev);
582
    radeon_vram_info(rdev);
616
		radeon_vram_info(rdev);
583
    /* Device is severly broken if aper size > vram size.
-
 
584
     * for RN50/M6/M7 - Novell bug 204882 ?
-
 
585
     */
-
 
586
    if (rdev->mc.vram_size < rdev->mc.aper_size) {
-
 
587
        rdev->mc.aper_size = rdev->mc.vram_size;
-
 
588
    }
-
 
589
    /* Add an MTRR for the VRAM */
-
 
590
//    rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
-
 
591
//                      MTRR_TYPE_WRCOMB, 1);
-
 
592
    DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
-
 
593
         rdev->mc.vram_size >> 20,
-
 
594
         (unsigned)rdev->mc.aper_size >> 20);
-
 
595
    DRM_INFO("RAM width %dbits %cDR\n",
-
 
596
         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
-
 
597
 
-
 
598
    /* Initialize clocks */
617
	/* Initialize clocks */
599
    r = radeon_clocks_init(rdev);
618
	r = radeon_clocks_init(rdev);
600
    if (r) {
619
	if (r) {
601
        return r;
620
		return r;
602
    }
621
	}
Line 604... Line 623...
604
    /* Initialize memory controller (also test AGP) */
623
	/* Initialize memory controller (also test AGP) */
605
    r = radeon_mc_init(rdev);
624
	r = radeon_mc_init(rdev);
606
    if (r) {
625
	if (r) {
607
        return r;
626
		return r;
608
	}
627
	}
609
    /* Fence driver */
-
 
610
//    r = radeon_fence_driver_init(rdev);
-
 
611
//    if (r) {
-
 
612
//        return r;
-
 
613
//    }
-
 
614
//    r = radeon_irq_kms_init(rdev);
-
 
615
//    if (r) {
-
 
616
//        return r;
-
 
617
//    }
-
 
618
    /* Memory manager */
628
    /* Memory manager */
619
    r = radeon_object_init(rdev);
629
    r = radeon_object_init(rdev);
620
    if (r) {
630
    if (r) {
621
        return r;
631
        return r;
622
    }
632
    }
-
 
633
		r = radeon_gpu_gart_init(rdev);
-
 
634
		if (r)
-
 
635
			return r;
623
    /* Initialize GART (initialize after TTM so we can allocate
636
    /* Initialize GART (initialize after TTM so we can allocate
624
     * memory through TTM but finalize after TTM) */
637
     * memory through TTM but finalize after TTM) */
625
    r = radeon_gart_enable(rdev);
638
    r = radeon_gart_enable(rdev);
626
    if (!r) {
639
		if (r)
-
 
640
			return 0;
627
        r = radeon_gem_init(rdev);
641
        r = radeon_gem_init(rdev);
628
    }
642
		if (r)
-
 
643
			return 0;
Line 629... Line 644...
629
 
644
 
630
    /* 1M ring buffer */
-
 
631
    if (!r) {
645
    /* 1M ring buffer */
632
        r = radeon_cp_init(rdev, 1024 * 1024);
-
 
633
    }
-
 
634
//    if (!r) {
-
 
635
//        r = radeon_wb_init(rdev);
646
//        r = radeon_cp_init(rdev, 1024 * 1024);
636
//        if (r) {
-
 
637
//            DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
647
//       if (r)
638
//            return r;
-
 
639
//        }
-
 
640
//    }
-
 
641
 
648
//           return 0;
-
 
649
#if 0
642
#if 0
650
		r = radeon_wb_init(rdev);
-
 
651
		if (r)
643
    if (!r) {
652
			DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
644
        r = radeon_ib_pool_init(rdev);
653
        r = radeon_ib_pool_init(rdev);
645
        if (r) {
-
 
646
            DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
654
		if (r)
647
            return r;
-
 
648
        }
-
 
649
    }
-
 
650
    if (!r) {
655
			return 0;
651
        r = radeon_ib_test(rdev);
656
		r = radeon_ib_test(rdev);
652
        if (r) {
-
 
653
            DRM_ERROR("radeon: failled testing IB (%d).\n", r);
657
		if (r)
654
            return r;
-
 
655
        }
-
 
656
    }
658
			return 0;
657
#endif
-
 
658
 
659
#endif
659
    ret = r;
660
		rdev->accel_working = true;
660
    r = radeon_modeset_init(rdev);
-
 
661
    if (r) {
-
 
662
        return r;
661
    r = radeon_modeset_init(rdev);
663
    }
-
 
664
//    if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
-
 
665
//        rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
-
 
666
//    }
-
 
667
    if (!ret) {
662
	}
-
 
663
	DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
-
 
664
//	if (radeon_testing) {
668
        DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
665
//		radeon_test_moves(rdev);
669
    }
666
//    }
670
	if (radeon_benchmarking) {
667
//	if (radeon_benchmarking) {
-
 
668
//		radeon_benchmark(rdev);
-
 
669
//    }
671
//        radeon_benchmark(rdev);
670
	return 0;
672
	}
-
 
Line 673... Line -...
673
	return ret;
-
 
674
 
-
 
Line 675... Line 671...
675
//    return -1;
671
}
676
}
672
 
677
 
673
 
Line 678... Line 674...
678
static struct pci_device_id pciidlist[] = {
674
static struct pci_device_id pciidlist[] = {
679
    radeon_PCI_IDS
675
    radeon_PCI_IDS
680
};
676
};
Line 681... Line 677...
681
 
677
 
682
 
678
 
Line 695... Line 691...
695
    {
691
    {
696
        printf("Can't open /hd0/2/atikms.log\nExit\n");
692
        printf("Can't open /hd0/2/atikms.log\nExit\n");
697
        return 0;
693
        return 0;
698
    }
694
    }
Line -... Line 695...
-
 
695
 
-
 
696
    if(cmdline)
-
 
697
        dbgprintf("cmdline: %s\n", cmdline);
699
 
698
 
Line 700... Line 699...
700
    enum_pci_devices();
699
    enum_pci_devices();
Line 701... Line 700...
701
 
700
 
Line 930... Line 929...
930
        return rem;
929
        return rem;
931
}
930
}
Line -... Line 931...
-
 
931
-
 
932
-
 
933