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Rev 1117 | Rev 1119 | ||
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Line 226... | Line 226... | ||
226 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
226 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
227 | reg, v); |
227 | reg, v); |
228 | BUG_ON(1); |
228 | BUG_ON(1); |
229 | } |
229 | } |
Line 230... | Line -... | ||
230 | - | ||
231 | 230 | ||
232 | void radeon_register_accessor_init(struct radeon_device *rdev) |
231 | void radeon_register_accessor_init(struct radeon_device *rdev) |
Line 233... | Line 232... | ||
233 | { |
232 | { |
Line 249... | Line 248... | ||
249 | if (rdev->family < CHIP_RV515) { |
248 | if (rdev->family < CHIP_RV515) { |
250 | // rdev->pcie_rreg = &rv370_pcie_rreg; |
249 | // rdev->pcie_rreg = &rv370_pcie_rreg; |
251 | // rdev->pcie_wreg = &rv370_pcie_wreg; |
250 | // rdev->pcie_wreg = &rv370_pcie_wreg; |
252 | } |
251 | } |
253 | if (rdev->family >= CHIP_RV515) { |
252 | if (rdev->family >= CHIP_RV515) { |
254 | // rdev->pcie_rreg = &rv515_pcie_rreg; |
253 | rdev->pcie_rreg = &rv515_pcie_rreg; |
255 | // rdev->pcie_wreg = &rv515_pcie_wreg; |
254 | rdev->pcie_wreg = &rv515_pcie_wreg; |
256 | } |
255 | } |
257 | /* FIXME: not sure here */ |
256 | /* FIXME: not sure here */ |
258 | if (rdev->family <= CHIP_R580) { |
257 | if (rdev->family <= CHIP_R580) { |
259 | // rdev->pll_rreg = &r100_pll_rreg; |
258 | rdev->pll_rreg = &r100_pll_rreg; |
260 | // rdev->pll_wreg = &r100_pll_wreg; |
259 | rdev->pll_wreg = &r100_pll_wreg; |
261 | } |
260 | } |
262 | if (rdev->family >= CHIP_RV515) { |
261 | if (rdev->family >= CHIP_RV515) { |
263 | rdev->mc_rreg = &rv515_mc_rreg; |
262 | rdev->mc_rreg = &rv515_mc_rreg; |
264 | rdev->mc_wreg = &rv515_mc_wreg; |
263 | rdev->mc_wreg = &rv515_mc_wreg; |
265 | } |
264 | } |
Line 445... | Line 444... | ||
445 | return 0; |
444 | return 0; |
446 | } |
445 | } |
Line 447... | Line 446... | ||
447 | 446 | ||
448 | void radeon_atombios_fini(struct radeon_device *rdev) |
447 | void radeon_atombios_fini(struct radeon_device *rdev) |
449 | { |
448 | { |
450 | free(rdev->mode_info.atom_context); |
449 | kfree(rdev->mode_info.atom_context); |
Line 451... | Line 450... | ||
451 | } |
450 | } |
452 | 451 | ||
453 | int radeon_combios_init(struct radeon_device *rdev) |
452 | int radeon_combios_init(struct radeon_device *rdev) |
Line 461... | Line 460... | ||
461 | } |
460 | } |
Line 462... | Line 461... | ||
462 | 461 | ||
463 | int radeon_modeset_init(struct radeon_device *rdev); |
462 | int radeon_modeset_init(struct radeon_device *rdev); |
Line 464... | Line -... | ||
464 | void radeon_modeset_fini(struct radeon_device *rdev); |
- | |
- | 463 | void radeon_modeset_fini(struct radeon_device *rdev); |
|
465 | 464 | ||
466 | 465 | void *ring_buffer; |
|
467 | /* |
466 | /* |
468 | * Radeon device. |
467 | * Radeon device. |
469 | */ |
468 | */ |
Line 491... | Line 490... | ||
491 | // mutex_init(&rdev->cs_mutex); |
490 | // mutex_init(&rdev->cs_mutex); |
492 | // mutex_init(&rdev->ib_pool.mutex); |
491 | // mutex_init(&rdev->ib_pool.mutex); |
493 | // mutex_init(&rdev->cp.mutex); |
492 | // mutex_init(&rdev->cp.mutex); |
494 | // rwlock_init(&rdev->fence_drv.lock); |
493 | // rwlock_init(&rdev->fence_drv.lock); |
Line -... | Line 494... | ||
- | 494 | ||
- | 495 | ring_buffer = CreateRingBuffer( 1024*1024, PG_SW ); |
|
495 | 496 | ||
496 | if (radeon_agpmode == -1) { |
497 | if (radeon_agpmode == -1) { |
497 | rdev->flags &= ~RADEON_IS_AGP; |
498 | rdev->flags &= ~RADEON_IS_AGP; |
498 | if (rdev->family > CHIP_RV515 || |
499 | if (rdev->family > CHIP_RV515 || |
499 | rdev->family == CHIP_RV380 || |
500 | rdev->family == CHIP_RV380 || |
Line 519... | Line 520... | ||
519 | if (r) { |
520 | if (r) { |
520 | return r; |
521 | return r; |
521 | } |
522 | } |
Line 522... | Line 523... | ||
522 | 523 | ||
523 | /* Report DMA addressing limitation */ |
524 | /* Report DMA addressing limitation */ |
524 | // r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); |
525 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); |
525 | // if (r) { |
526 | if (r) { |
526 | // printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
527 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
Line 527... | Line 528... | ||
527 | // } |
528 | } |
528 | 529 | ||
529 | /* Registers mapping */ |
530 | /* Registers mapping */ |
Line 563... | Line 564... | ||
563 | r = radeon_combios_init(rdev); |
564 | r = radeon_combios_init(rdev); |
564 | if (r) { |
565 | if (r) { |
565 | return r; |
566 | return r; |
566 | } |
567 | } |
567 | } |
568 | } |
568 | - | ||
569 | - | ||
570 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
569 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
571 | if (radeon_gpu_reset(rdev)) { |
570 | if (radeon_gpu_reset(rdev)) { |
572 | /* FIXME: what do we want to do here ? */ |
571 | /* FIXME: what do we want to do here ? */ |
573 | } |
572 | } |
574 | - | ||
575 | /* check if cards are posted or not */ |
573 | /* check if cards are posted or not */ |
576 | if (!radeon_card_posted(rdev) && rdev->bios) { |
574 | if (!radeon_card_posted(rdev) && rdev->bios) { |
577 | DRM_INFO("GPU not posted. posting now...\n"); |
575 | DRM_INFO("GPU not posted. posting now...\n"); |
578 | if (rdev->is_atom_bios) { |
576 | if (rdev->is_atom_bios) { |
579 | atom_asic_init(rdev->mode_info.atom_context); |
577 | atom_asic_init(rdev->mode_info.atom_context); |
Line 603... | Line 601... | ||
603 | r = radeon_clocks_init(rdev); |
601 | r = radeon_clocks_init(rdev); |
604 | if (r) { |
602 | if (r) { |
605 | return r; |
603 | return r; |
606 | } |
604 | } |
Line 607... | Line -... | ||
607 | - | ||
608 | #if 0 |
- | |
609 | 605 | ||
610 | /* Initialize memory controller (also test AGP) */ |
606 | /* Initialize memory controller (also test AGP) */ |
611 | r = radeon_mc_init(rdev); |
607 | r = radeon_mc_init(rdev); |
612 | if (r) { |
608 | if (r) { |
613 | return r; |
609 | return r; |
- | 610 | }; |
|
- | 611 | ||
614 | } |
612 | |
615 | /* Fence driver */ |
613 | /* Fence driver */ |
616 | r = radeon_fence_driver_init(rdev); |
614 | // r = radeon_fence_driver_init(rdev); |
617 | if (r) { |
615 | // if (r) { |
618 | return r; |
616 | // return r; |
619 | } |
617 | // } |
620 | r = radeon_irq_kms_init(rdev); |
618 | // r = radeon_irq_kms_init(rdev); |
621 | if (r) { |
619 | // if (r) { |
622 | return r; |
620 | // return r; |
623 | } |
621 | // } |
624 | /* Memory manager */ |
622 | /* Memory manager */ |
625 | r = radeon_object_init(rdev); |
623 | // r = radeon_object_init(rdev); |
626 | if (r) { |
624 | // if (r) { |
627 | return r; |
625 | // return r; |
628 | } |
626 | // } |
629 | /* Initialize GART (initialize after TTM so we can allocate |
627 | /* Initialize GART (initialize after TTM so we can allocate |
630 | * memory through TTM but finalize after TTM) */ |
628 | * memory through TTM but finalize after TTM) */ |
631 | r = radeon_gart_enable(rdev); |
629 | r = radeon_gart_enable(rdev); |
632 | if (!r) { |
630 | // if (!r) { |
633 | r = radeon_gem_init(rdev); |
631 | // r = radeon_gem_init(rdev); |
Line 634... | Line 632... | ||
634 | } |
632 | // } |
635 | 633 | ||
636 | /* 1M ring buffer */ |
634 | /* 1M ring buffer */ |
637 | if (!r) { |
635 | if (!r) { |
638 | r = radeon_cp_init(rdev, 1024 * 1024); |
636 | r = radeon_cp_init(rdev, 1024 * 1024); |
639 | } |
637 | } |
640 | if (!r) { |
638 | // if (!r) { |
641 | r = radeon_wb_init(rdev); |
639 | // r = radeon_wb_init(rdev); |
642 | if (r) { |
640 | // if (r) { |
643 | DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
641 | // DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
644 | return r; |
642 | // return r; |
- | 643 | // } |
|
- | 644 | // } |
|
645 | } |
645 | |
646 | } |
646 | #if 0 |
647 | if (!r) { |
647 | if (!r) { |
648 | r = radeon_ib_pool_init(rdev); |
648 | r = radeon_ib_pool_init(rdev); |
649 | if (r) { |
649 | if (r) { |