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1 | /* |
1 | /* |
2 | * Copyright 2004 ATI Technologies Inc., Markham, Ontario |
2 | * Copyright 2004 ATI Technologies Inc., Markham, Ontario |
3 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
4 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | */ |
26 | */ |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | 31 | ||
32 | #ifdef CONFIG_PPC_PMAC |
32 | #ifdef CONFIG_PPC_PMAC |
33 | /* not sure which of these are needed */ |
33 | /* not sure which of these are needed */ |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include |
37 | #include |
- | |
38 | #endif /* CONFIG_PPC_PMAC */ |
37 | #endif /* CONFIG_PPC_PMAC */ |
39 | 38 | ||
40 | /* from radeon_legacy_encoder.c */ |
39 | /* from radeon_legacy_encoder.c */ |
41 | extern void |
40 | extern void |
42 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
41 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
43 | uint32_t supported_device); |
42 | uint32_t supported_device); |
44 | 43 | ||
45 | /* old legacy ATI BIOS routines */ |
44 | /* old legacy ATI BIOS routines */ |
46 | 45 | ||
47 | /* COMBIOS table offsets */ |
46 | /* COMBIOS table offsets */ |
48 | enum radeon_combios_table_offset { |
47 | enum radeon_combios_table_offset { |
49 | /* absolute offset tables */ |
48 | /* absolute offset tables */ |
50 | COMBIOS_ASIC_INIT_1_TABLE, |
49 | COMBIOS_ASIC_INIT_1_TABLE, |
51 | COMBIOS_BIOS_SUPPORT_TABLE, |
50 | COMBIOS_BIOS_SUPPORT_TABLE, |
52 | COMBIOS_DAC_PROGRAMMING_TABLE, |
51 | COMBIOS_DAC_PROGRAMMING_TABLE, |
53 | COMBIOS_MAX_COLOR_DEPTH_TABLE, |
52 | COMBIOS_MAX_COLOR_DEPTH_TABLE, |
54 | COMBIOS_CRTC_INFO_TABLE, |
53 | COMBIOS_CRTC_INFO_TABLE, |
55 | COMBIOS_PLL_INFO_TABLE, |
54 | COMBIOS_PLL_INFO_TABLE, |
56 | COMBIOS_TV_INFO_TABLE, |
55 | COMBIOS_TV_INFO_TABLE, |
57 | COMBIOS_DFP_INFO_TABLE, |
56 | COMBIOS_DFP_INFO_TABLE, |
58 | COMBIOS_HW_CONFIG_INFO_TABLE, |
57 | COMBIOS_HW_CONFIG_INFO_TABLE, |
59 | COMBIOS_MULTIMEDIA_INFO_TABLE, |
58 | COMBIOS_MULTIMEDIA_INFO_TABLE, |
60 | COMBIOS_TV_STD_PATCH_TABLE, |
59 | COMBIOS_TV_STD_PATCH_TABLE, |
61 | COMBIOS_LCD_INFO_TABLE, |
60 | COMBIOS_LCD_INFO_TABLE, |
62 | COMBIOS_MOBILE_INFO_TABLE, |
61 | COMBIOS_MOBILE_INFO_TABLE, |
63 | COMBIOS_PLL_INIT_TABLE, |
62 | COMBIOS_PLL_INIT_TABLE, |
64 | COMBIOS_MEM_CONFIG_TABLE, |
63 | COMBIOS_MEM_CONFIG_TABLE, |
65 | COMBIOS_SAVE_MASK_TABLE, |
64 | COMBIOS_SAVE_MASK_TABLE, |
66 | COMBIOS_HARDCODED_EDID_TABLE, |
65 | COMBIOS_HARDCODED_EDID_TABLE, |
67 | COMBIOS_ASIC_INIT_2_TABLE, |
66 | COMBIOS_ASIC_INIT_2_TABLE, |
68 | COMBIOS_CONNECTOR_INFO_TABLE, |
67 | COMBIOS_CONNECTOR_INFO_TABLE, |
69 | COMBIOS_DYN_CLK_1_TABLE, |
68 | COMBIOS_DYN_CLK_1_TABLE, |
70 | COMBIOS_RESERVED_MEM_TABLE, |
69 | COMBIOS_RESERVED_MEM_TABLE, |
71 | COMBIOS_EXT_TMDS_INFO_TABLE, |
70 | COMBIOS_EXT_TMDS_INFO_TABLE, |
72 | COMBIOS_MEM_CLK_INFO_TABLE, |
71 | COMBIOS_MEM_CLK_INFO_TABLE, |
73 | COMBIOS_EXT_DAC_INFO_TABLE, |
72 | COMBIOS_EXT_DAC_INFO_TABLE, |
74 | COMBIOS_MISC_INFO_TABLE, |
73 | COMBIOS_MISC_INFO_TABLE, |
75 | COMBIOS_CRT_INFO_TABLE, |
74 | COMBIOS_CRT_INFO_TABLE, |
76 | COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, |
75 | COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, |
77 | COMBIOS_COMPONENT_VIDEO_INFO_TABLE, |
76 | COMBIOS_COMPONENT_VIDEO_INFO_TABLE, |
78 | COMBIOS_FAN_SPEED_INFO_TABLE, |
77 | COMBIOS_FAN_SPEED_INFO_TABLE, |
79 | COMBIOS_OVERDRIVE_INFO_TABLE, |
78 | COMBIOS_OVERDRIVE_INFO_TABLE, |
80 | COMBIOS_OEM_INFO_TABLE, |
79 | COMBIOS_OEM_INFO_TABLE, |
81 | COMBIOS_DYN_CLK_2_TABLE, |
80 | COMBIOS_DYN_CLK_2_TABLE, |
82 | COMBIOS_POWER_CONNECTOR_INFO_TABLE, |
81 | COMBIOS_POWER_CONNECTOR_INFO_TABLE, |
83 | COMBIOS_I2C_INFO_TABLE, |
82 | COMBIOS_I2C_INFO_TABLE, |
84 | /* relative offset tables */ |
83 | /* relative offset tables */ |
85 | COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ |
84 | COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ |
86 | COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ |
85 | COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ |
87 | COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ |
86 | COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ |
88 | COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ |
87 | COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ |
89 | COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ |
88 | COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ |
90 | COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ |
89 | COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ |
91 | COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ |
90 | COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ |
92 | COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ |
91 | COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ |
93 | COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ |
92 | COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ |
94 | COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ |
93 | COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ |
95 | COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ |
94 | COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ |
96 | }; |
95 | }; |
97 | 96 | ||
98 | enum radeon_combios_ddc { |
97 | enum radeon_combios_ddc { |
99 | DDC_NONE_DETECTED, |
98 | DDC_NONE_DETECTED, |
100 | DDC_MONID, |
99 | DDC_MONID, |
101 | DDC_DVI, |
100 | DDC_DVI, |
102 | DDC_VGA, |
101 | DDC_VGA, |
103 | DDC_CRT2, |
102 | DDC_CRT2, |
104 | DDC_LCD, |
103 | DDC_LCD, |
105 | DDC_GPIO, |
104 | DDC_GPIO, |
106 | }; |
105 | }; |
107 | 106 | ||
108 | enum radeon_combios_connector { |
107 | enum radeon_combios_connector { |
109 | CONNECTOR_NONE_LEGACY, |
108 | CONNECTOR_NONE_LEGACY, |
110 | CONNECTOR_PROPRIETARY_LEGACY, |
109 | CONNECTOR_PROPRIETARY_LEGACY, |
111 | CONNECTOR_CRT_LEGACY, |
110 | CONNECTOR_CRT_LEGACY, |
112 | CONNECTOR_DVI_I_LEGACY, |
111 | CONNECTOR_DVI_I_LEGACY, |
113 | CONNECTOR_DVI_D_LEGACY, |
112 | CONNECTOR_DVI_D_LEGACY, |
114 | CONNECTOR_CTV_LEGACY, |
113 | CONNECTOR_CTV_LEGACY, |
115 | CONNECTOR_STV_LEGACY, |
114 | CONNECTOR_STV_LEGACY, |
116 | CONNECTOR_UNSUPPORTED_LEGACY |
115 | CONNECTOR_UNSUPPORTED_LEGACY |
117 | }; |
116 | }; |
118 | 117 | ||
119 | static const int legacy_connector_convert[] = { |
118 | static const int legacy_connector_convert[] = { |
120 | DRM_MODE_CONNECTOR_Unknown, |
119 | DRM_MODE_CONNECTOR_Unknown, |
121 | DRM_MODE_CONNECTOR_DVID, |
120 | DRM_MODE_CONNECTOR_DVID, |
122 | DRM_MODE_CONNECTOR_VGA, |
121 | DRM_MODE_CONNECTOR_VGA, |
123 | DRM_MODE_CONNECTOR_DVII, |
122 | DRM_MODE_CONNECTOR_DVII, |
124 | DRM_MODE_CONNECTOR_DVID, |
123 | DRM_MODE_CONNECTOR_DVID, |
125 | DRM_MODE_CONNECTOR_Composite, |
124 | DRM_MODE_CONNECTOR_Composite, |
126 | DRM_MODE_CONNECTOR_SVIDEO, |
125 | DRM_MODE_CONNECTOR_SVIDEO, |
127 | DRM_MODE_CONNECTOR_Unknown, |
126 | DRM_MODE_CONNECTOR_Unknown, |
128 | }; |
127 | }; |
129 | 128 | ||
130 | static uint16_t combios_get_table_offset(struct drm_device *dev, |
129 | static uint16_t combios_get_table_offset(struct drm_device *dev, |
131 | enum radeon_combios_table_offset table) |
130 | enum radeon_combios_table_offset table) |
132 | { |
131 | { |
133 | struct radeon_device *rdev = dev->dev_private; |
132 | struct radeon_device *rdev = dev->dev_private; |
134 | int rev, size; |
133 | int rev, size; |
135 | uint16_t offset = 0, check_offset; |
134 | uint16_t offset = 0, check_offset; |
136 | 135 | ||
137 | if (!rdev->bios) |
136 | if (!rdev->bios) |
138 | return 0; |
137 | return 0; |
139 | 138 | ||
140 | switch (table) { |
139 | switch (table) { |
141 | /* absolute offset tables */ |
140 | /* absolute offset tables */ |
142 | case COMBIOS_ASIC_INIT_1_TABLE: |
141 | case COMBIOS_ASIC_INIT_1_TABLE: |
143 | check_offset = 0xc; |
142 | check_offset = 0xc; |
144 | break; |
143 | break; |
145 | case COMBIOS_BIOS_SUPPORT_TABLE: |
144 | case COMBIOS_BIOS_SUPPORT_TABLE: |
146 | check_offset = 0x14; |
145 | check_offset = 0x14; |
147 | break; |
146 | break; |
148 | case COMBIOS_DAC_PROGRAMMING_TABLE: |
147 | case COMBIOS_DAC_PROGRAMMING_TABLE: |
149 | check_offset = 0x2a; |
148 | check_offset = 0x2a; |
150 | break; |
149 | break; |
151 | case COMBIOS_MAX_COLOR_DEPTH_TABLE: |
150 | case COMBIOS_MAX_COLOR_DEPTH_TABLE: |
152 | check_offset = 0x2c; |
151 | check_offset = 0x2c; |
153 | break; |
152 | break; |
154 | case COMBIOS_CRTC_INFO_TABLE: |
153 | case COMBIOS_CRTC_INFO_TABLE: |
155 | check_offset = 0x2e; |
154 | check_offset = 0x2e; |
156 | break; |
155 | break; |
157 | case COMBIOS_PLL_INFO_TABLE: |
156 | case COMBIOS_PLL_INFO_TABLE: |
158 | check_offset = 0x30; |
157 | check_offset = 0x30; |
159 | break; |
158 | break; |
160 | case COMBIOS_TV_INFO_TABLE: |
159 | case COMBIOS_TV_INFO_TABLE: |
161 | check_offset = 0x32; |
160 | check_offset = 0x32; |
162 | break; |
161 | break; |
163 | case COMBIOS_DFP_INFO_TABLE: |
162 | case COMBIOS_DFP_INFO_TABLE: |
164 | check_offset = 0x34; |
163 | check_offset = 0x34; |
165 | break; |
164 | break; |
166 | case COMBIOS_HW_CONFIG_INFO_TABLE: |
165 | case COMBIOS_HW_CONFIG_INFO_TABLE: |
167 | check_offset = 0x36; |
166 | check_offset = 0x36; |
168 | break; |
167 | break; |
169 | case COMBIOS_MULTIMEDIA_INFO_TABLE: |
168 | case COMBIOS_MULTIMEDIA_INFO_TABLE: |
170 | check_offset = 0x38; |
169 | check_offset = 0x38; |
171 | break; |
170 | break; |
172 | case COMBIOS_TV_STD_PATCH_TABLE: |
171 | case COMBIOS_TV_STD_PATCH_TABLE: |
173 | check_offset = 0x3e; |
172 | check_offset = 0x3e; |
174 | break; |
173 | break; |
175 | case COMBIOS_LCD_INFO_TABLE: |
174 | case COMBIOS_LCD_INFO_TABLE: |
176 | check_offset = 0x40; |
175 | check_offset = 0x40; |
177 | break; |
176 | break; |
178 | case COMBIOS_MOBILE_INFO_TABLE: |
177 | case COMBIOS_MOBILE_INFO_TABLE: |
179 | check_offset = 0x42; |
178 | check_offset = 0x42; |
180 | break; |
179 | break; |
181 | case COMBIOS_PLL_INIT_TABLE: |
180 | case COMBIOS_PLL_INIT_TABLE: |
182 | check_offset = 0x46; |
181 | check_offset = 0x46; |
183 | break; |
182 | break; |
184 | case COMBIOS_MEM_CONFIG_TABLE: |
183 | case COMBIOS_MEM_CONFIG_TABLE: |
185 | check_offset = 0x48; |
184 | check_offset = 0x48; |
186 | break; |
185 | break; |
187 | case COMBIOS_SAVE_MASK_TABLE: |
186 | case COMBIOS_SAVE_MASK_TABLE: |
188 | check_offset = 0x4a; |
187 | check_offset = 0x4a; |
189 | break; |
188 | break; |
190 | case COMBIOS_HARDCODED_EDID_TABLE: |
189 | case COMBIOS_HARDCODED_EDID_TABLE: |
191 | check_offset = 0x4c; |
190 | check_offset = 0x4c; |
192 | break; |
191 | break; |
193 | case COMBIOS_ASIC_INIT_2_TABLE: |
192 | case COMBIOS_ASIC_INIT_2_TABLE: |
194 | check_offset = 0x4e; |
193 | check_offset = 0x4e; |
195 | break; |
194 | break; |
196 | case COMBIOS_CONNECTOR_INFO_TABLE: |
195 | case COMBIOS_CONNECTOR_INFO_TABLE: |
197 | check_offset = 0x50; |
196 | check_offset = 0x50; |
198 | break; |
197 | break; |
199 | case COMBIOS_DYN_CLK_1_TABLE: |
198 | case COMBIOS_DYN_CLK_1_TABLE: |
200 | check_offset = 0x52; |
199 | check_offset = 0x52; |
201 | break; |
200 | break; |
202 | case COMBIOS_RESERVED_MEM_TABLE: |
201 | case COMBIOS_RESERVED_MEM_TABLE: |
203 | check_offset = 0x54; |
202 | check_offset = 0x54; |
204 | break; |
203 | break; |
205 | case COMBIOS_EXT_TMDS_INFO_TABLE: |
204 | case COMBIOS_EXT_TMDS_INFO_TABLE: |
206 | check_offset = 0x58; |
205 | check_offset = 0x58; |
207 | break; |
206 | break; |
208 | case COMBIOS_MEM_CLK_INFO_TABLE: |
207 | case COMBIOS_MEM_CLK_INFO_TABLE: |
209 | check_offset = 0x5a; |
208 | check_offset = 0x5a; |
210 | break; |
209 | break; |
211 | case COMBIOS_EXT_DAC_INFO_TABLE: |
210 | case COMBIOS_EXT_DAC_INFO_TABLE: |
212 | check_offset = 0x5c; |
211 | check_offset = 0x5c; |
213 | break; |
212 | break; |
214 | case COMBIOS_MISC_INFO_TABLE: |
213 | case COMBIOS_MISC_INFO_TABLE: |
215 | check_offset = 0x5e; |
214 | check_offset = 0x5e; |
216 | break; |
215 | break; |
217 | case COMBIOS_CRT_INFO_TABLE: |
216 | case COMBIOS_CRT_INFO_TABLE: |
218 | check_offset = 0x60; |
217 | check_offset = 0x60; |
219 | break; |
218 | break; |
220 | case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: |
219 | case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: |
221 | check_offset = 0x62; |
220 | check_offset = 0x62; |
222 | break; |
221 | break; |
223 | case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: |
222 | case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: |
224 | check_offset = 0x64; |
223 | check_offset = 0x64; |
225 | break; |
224 | break; |
226 | case COMBIOS_FAN_SPEED_INFO_TABLE: |
225 | case COMBIOS_FAN_SPEED_INFO_TABLE: |
227 | check_offset = 0x66; |
226 | check_offset = 0x66; |
228 | break; |
227 | break; |
229 | case COMBIOS_OVERDRIVE_INFO_TABLE: |
228 | case COMBIOS_OVERDRIVE_INFO_TABLE: |
230 | check_offset = 0x68; |
229 | check_offset = 0x68; |
231 | break; |
230 | break; |
232 | case COMBIOS_OEM_INFO_TABLE: |
231 | case COMBIOS_OEM_INFO_TABLE: |
233 | check_offset = 0x6a; |
232 | check_offset = 0x6a; |
234 | break; |
233 | break; |
235 | case COMBIOS_DYN_CLK_2_TABLE: |
234 | case COMBIOS_DYN_CLK_2_TABLE: |
236 | check_offset = 0x6c; |
235 | check_offset = 0x6c; |
237 | break; |
236 | break; |
238 | case COMBIOS_POWER_CONNECTOR_INFO_TABLE: |
237 | case COMBIOS_POWER_CONNECTOR_INFO_TABLE: |
239 | check_offset = 0x6e; |
238 | check_offset = 0x6e; |
240 | break; |
239 | break; |
241 | case COMBIOS_I2C_INFO_TABLE: |
240 | case COMBIOS_I2C_INFO_TABLE: |
242 | check_offset = 0x70; |
241 | check_offset = 0x70; |
243 | break; |
242 | break; |
244 | /* relative offset tables */ |
243 | /* relative offset tables */ |
245 | case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ |
244 | case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ |
246 | check_offset = |
245 | check_offset = |
247 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
246 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
248 | if (check_offset) { |
247 | if (check_offset) { |
249 | rev = RBIOS8(check_offset); |
248 | rev = RBIOS8(check_offset); |
250 | if (rev > 0) { |
249 | if (rev > 0) { |
251 | check_offset = RBIOS16(check_offset + 0x3); |
250 | check_offset = RBIOS16(check_offset + 0x3); |
252 | if (check_offset) |
251 | if (check_offset) |
253 | offset = check_offset; |
252 | offset = check_offset; |
254 | } |
253 | } |
255 | } |
254 | } |
256 | break; |
255 | break; |
257 | case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ |
256 | case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ |
258 | check_offset = |
257 | check_offset = |
259 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
258 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
260 | if (check_offset) { |
259 | if (check_offset) { |
261 | rev = RBIOS8(check_offset); |
260 | rev = RBIOS8(check_offset); |
262 | if (rev > 0) { |
261 | if (rev > 0) { |
263 | check_offset = RBIOS16(check_offset + 0x5); |
262 | check_offset = RBIOS16(check_offset + 0x5); |
264 | if (check_offset) |
263 | if (check_offset) |
265 | offset = check_offset; |
264 | offset = check_offset; |
266 | } |
265 | } |
267 | } |
266 | } |
268 | break; |
267 | break; |
269 | case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ |
268 | case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ |
270 | check_offset = |
269 | check_offset = |
271 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
270 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
272 | if (check_offset) { |
271 | if (check_offset) { |
273 | rev = RBIOS8(check_offset); |
272 | rev = RBIOS8(check_offset); |
274 | if (rev > 0) { |
273 | if (rev > 0) { |
275 | check_offset = RBIOS16(check_offset + 0x7); |
274 | check_offset = RBIOS16(check_offset + 0x7); |
276 | if (check_offset) |
275 | if (check_offset) |
277 | offset = check_offset; |
276 | offset = check_offset; |
278 | } |
277 | } |
279 | } |
278 | } |
280 | break; |
279 | break; |
281 | case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ |
280 | case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ |
282 | check_offset = |
281 | check_offset = |
283 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
282 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
284 | if (check_offset) { |
283 | if (check_offset) { |
285 | rev = RBIOS8(check_offset); |
284 | rev = RBIOS8(check_offset); |
286 | if (rev == 2) { |
285 | if (rev == 2) { |
287 | check_offset = RBIOS16(check_offset + 0x9); |
286 | check_offset = RBIOS16(check_offset + 0x9); |
288 | if (check_offset) |
287 | if (check_offset) |
289 | offset = check_offset; |
288 | offset = check_offset; |
290 | } |
289 | } |
291 | } |
290 | } |
292 | break; |
291 | break; |
293 | case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ |
292 | case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ |
294 | check_offset = |
293 | check_offset = |
295 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
294 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
296 | if (check_offset) { |
295 | if (check_offset) { |
297 | while (RBIOS8(check_offset++)); |
296 | while (RBIOS8(check_offset++)); |
298 | check_offset += 2; |
297 | check_offset += 2; |
299 | if (check_offset) |
298 | if (check_offset) |
300 | offset = check_offset; |
299 | offset = check_offset; |
301 | } |
300 | } |
302 | break; |
301 | break; |
303 | case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ |
302 | case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ |
304 | check_offset = |
303 | check_offset = |
305 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
304 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
306 | if (check_offset) { |
305 | if (check_offset) { |
307 | check_offset = RBIOS16(check_offset + 0x11); |
306 | check_offset = RBIOS16(check_offset + 0x11); |
308 | if (check_offset) |
307 | if (check_offset) |
309 | offset = check_offset; |
308 | offset = check_offset; |
310 | } |
309 | } |
311 | break; |
310 | break; |
312 | case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ |
311 | case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ |
313 | check_offset = |
312 | check_offset = |
314 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
313 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
315 | if (check_offset) { |
314 | if (check_offset) { |
316 | check_offset = RBIOS16(check_offset + 0x13); |
315 | check_offset = RBIOS16(check_offset + 0x13); |
317 | if (check_offset) |
316 | if (check_offset) |
318 | offset = check_offset; |
317 | offset = check_offset; |
319 | } |
318 | } |
320 | break; |
319 | break; |
321 | case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ |
320 | case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ |
322 | check_offset = |
321 | check_offset = |
323 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
322 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
324 | if (check_offset) { |
323 | if (check_offset) { |
325 | check_offset = RBIOS16(check_offset + 0x15); |
324 | check_offset = RBIOS16(check_offset + 0x15); |
326 | if (check_offset) |
325 | if (check_offset) |
327 | offset = check_offset; |
326 | offset = check_offset; |
328 | } |
327 | } |
329 | break; |
328 | break; |
330 | case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ |
329 | case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ |
331 | check_offset = |
330 | check_offset = |
332 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
331 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
333 | if (check_offset) { |
332 | if (check_offset) { |
334 | check_offset = RBIOS16(check_offset + 0x17); |
333 | check_offset = RBIOS16(check_offset + 0x17); |
335 | if (check_offset) |
334 | if (check_offset) |
336 | offset = check_offset; |
335 | offset = check_offset; |
337 | } |
336 | } |
338 | break; |
337 | break; |
339 | case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ |
338 | case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ |
340 | check_offset = |
339 | check_offset = |
341 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
340 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
342 | if (check_offset) { |
341 | if (check_offset) { |
343 | check_offset = RBIOS16(check_offset + 0x2); |
342 | check_offset = RBIOS16(check_offset + 0x2); |
344 | if (check_offset) |
343 | if (check_offset) |
345 | offset = check_offset; |
344 | offset = check_offset; |
346 | } |
345 | } |
347 | break; |
346 | break; |
348 | case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ |
347 | case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ |
349 | check_offset = |
348 | check_offset = |
350 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
349 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
351 | if (check_offset) { |
350 | if (check_offset) { |
352 | check_offset = RBIOS16(check_offset + 0x4); |
351 | check_offset = RBIOS16(check_offset + 0x4); |
353 | if (check_offset) |
352 | if (check_offset) |
354 | offset = check_offset; |
353 | offset = check_offset; |
355 | } |
354 | } |
356 | break; |
355 | break; |
357 | default: |
356 | default: |
358 | check_offset = 0; |
357 | check_offset = 0; |
359 | break; |
358 | break; |
360 | } |
359 | } |
361 | 360 | ||
362 | size = RBIOS8(rdev->bios_header_start + 0x6); |
361 | size = RBIOS8(rdev->bios_header_start + 0x6); |
363 | /* check absolute offset tables */ |
362 | /* check absolute offset tables */ |
364 | if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) |
363 | if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) |
365 | offset = RBIOS16(rdev->bios_header_start + check_offset); |
364 | offset = RBIOS16(rdev->bios_header_start + check_offset); |
366 | 365 | ||
367 | return offset; |
366 | return offset; |
368 | } |
367 | } |
369 | 368 | ||
370 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
369 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
371 | { |
370 | { |
372 | int edid_info, size; |
371 | int edid_info, size; |
373 | struct edid *edid; |
372 | struct edid *edid; |
374 | unsigned char *raw; |
373 | unsigned char *raw; |
375 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
374 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
376 | if (!edid_info) |
375 | if (!edid_info) |
377 | return false; |
376 | return false; |
378 | 377 | ||
379 | raw = rdev->bios + edid_info; |
378 | raw = rdev->bios + edid_info; |
380 | size = EDID_LENGTH * (raw[0x7e] + 1); |
379 | size = EDID_LENGTH * (raw[0x7e] + 1); |
381 | edid = kmalloc(size, GFP_KERNEL); |
380 | edid = kmalloc(size, GFP_KERNEL); |
382 | if (edid == NULL) |
381 | if (edid == NULL) |
383 | return false; |
382 | return false; |
384 | 383 | ||
385 | memcpy((unsigned char *)edid, raw, size); |
384 | memcpy((unsigned char *)edid, raw, size); |
386 | 385 | ||
387 | if (!drm_edid_is_valid(edid)) { |
386 | if (!drm_edid_is_valid(edid)) { |
388 | kfree(edid); |
387 | kfree(edid); |
389 | return false; |
388 | return false; |
390 | } |
389 | } |
391 | 390 | ||
392 | rdev->mode_info.bios_hardcoded_edid = edid; |
391 | rdev->mode_info.bios_hardcoded_edid = edid; |
393 | rdev->mode_info.bios_hardcoded_edid_size = size; |
392 | rdev->mode_info.bios_hardcoded_edid_size = size; |
394 | return true; |
393 | return true; |
395 | } |
394 | } |
396 | 395 | ||
397 | /* this is used for atom LCDs as well */ |
396 | /* this is used for atom LCDs as well */ |
398 | struct edid * |
397 | struct edid * |
399 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
398 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
400 | { |
399 | { |
401 | struct edid *edid; |
400 | struct edid *edid; |
402 | 401 | ||
403 | if (rdev->mode_info.bios_hardcoded_edid) { |
402 | if (rdev->mode_info.bios_hardcoded_edid) { |
404 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); |
403 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); |
405 | if (edid) { |
404 | if (edid) { |
406 | memcpy((unsigned char *)edid, |
405 | memcpy((unsigned char *)edid, |
407 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid, |
406 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid, |
408 | rdev->mode_info.bios_hardcoded_edid_size); |
407 | rdev->mode_info.bios_hardcoded_edid_size); |
409 | return edid; |
408 | return edid; |
410 | } |
409 | } |
411 | } |
410 | } |
412 | return NULL; |
411 | return NULL; |
413 | } |
412 | } |
414 | 413 | ||
415 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
414 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
416 | enum radeon_combios_ddc ddc, |
415 | enum radeon_combios_ddc ddc, |
417 | u32 clk_mask, |
416 | u32 clk_mask, |
418 | u32 data_mask) |
417 | u32 data_mask) |
419 | { |
418 | { |
420 | struct radeon_i2c_bus_rec i2c; |
419 | struct radeon_i2c_bus_rec i2c; |
421 | int ddc_line = 0; |
420 | int ddc_line = 0; |
422 | 421 | ||
423 | /* ddc id = mask reg |
422 | /* ddc id = mask reg |
424 | * DDC_NONE_DETECTED = none |
423 | * DDC_NONE_DETECTED = none |
425 | * DDC_DVI = RADEON_GPIO_DVI_DDC |
424 | * DDC_DVI = RADEON_GPIO_DVI_DDC |
426 | * DDC_VGA = RADEON_GPIO_VGA_DDC |
425 | * DDC_VGA = RADEON_GPIO_VGA_DDC |
427 | * DDC_LCD = RADEON_GPIOPAD_MASK |
426 | * DDC_LCD = RADEON_GPIOPAD_MASK |
428 | * DDC_GPIO = RADEON_MDGPIO_MASK |
427 | * DDC_GPIO = RADEON_MDGPIO_MASK |
429 | * r1xx |
428 | * r1xx |
430 | * DDC_MONID = RADEON_GPIO_MONID |
429 | * DDC_MONID = RADEON_GPIO_MONID |
431 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
430 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
432 | * r200 |
431 | * r200 |
433 | * DDC_MONID = RADEON_GPIO_MONID |
432 | * DDC_MONID = RADEON_GPIO_MONID |
434 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
433 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
435 | * r300/r350 |
434 | * r300/r350 |
436 | * DDC_MONID = RADEON_GPIO_DVI_DDC |
435 | * DDC_MONID = RADEON_GPIO_DVI_DDC |
437 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
436 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
438 | * rv2xx/rv3xx |
437 | * rv2xx/rv3xx |
439 | * DDC_MONID = RADEON_GPIO_MONID |
438 | * DDC_MONID = RADEON_GPIO_MONID |
440 | * DDC_CRT2 = RADEON_GPIO_MONID |
439 | * DDC_CRT2 = RADEON_GPIO_MONID |
441 | * rs3xx/rs4xx |
440 | * rs3xx/rs4xx |
442 | * DDC_MONID = RADEON_GPIOPAD_MASK |
441 | * DDC_MONID = RADEON_GPIOPAD_MASK |
443 | * DDC_CRT2 = RADEON_GPIO_MONID |
442 | * DDC_CRT2 = RADEON_GPIO_MONID |
444 | */ |
443 | */ |
445 | switch (ddc) { |
444 | switch (ddc) { |
446 | case DDC_NONE_DETECTED: |
445 | case DDC_NONE_DETECTED: |
447 | default: |
446 | default: |
448 | ddc_line = 0; |
447 | ddc_line = 0; |
449 | break; |
448 | break; |
450 | case DDC_DVI: |
449 | case DDC_DVI: |
451 | ddc_line = RADEON_GPIO_DVI_DDC; |
450 | ddc_line = RADEON_GPIO_DVI_DDC; |
452 | break; |
451 | break; |
453 | case DDC_VGA: |
452 | case DDC_VGA: |
454 | ddc_line = RADEON_GPIO_VGA_DDC; |
453 | ddc_line = RADEON_GPIO_VGA_DDC; |
455 | break; |
454 | break; |
456 | case DDC_LCD: |
455 | case DDC_LCD: |
457 | ddc_line = RADEON_GPIOPAD_MASK; |
456 | ddc_line = RADEON_GPIOPAD_MASK; |
458 | break; |
457 | break; |
459 | case DDC_GPIO: |
458 | case DDC_GPIO: |
460 | ddc_line = RADEON_MDGPIO_MASK; |
459 | ddc_line = RADEON_MDGPIO_MASK; |
461 | break; |
460 | break; |
462 | case DDC_MONID: |
461 | case DDC_MONID: |
463 | if (rdev->family == CHIP_RS300 || |
462 | if (rdev->family == CHIP_RS300 || |
464 | rdev->family == CHIP_RS400 || |
463 | rdev->family == CHIP_RS400 || |
465 | rdev->family == CHIP_RS480) |
464 | rdev->family == CHIP_RS480) |
466 | ddc_line = RADEON_GPIOPAD_MASK; |
465 | ddc_line = RADEON_GPIOPAD_MASK; |
467 | else if (rdev->family == CHIP_R300 || |
466 | else if (rdev->family == CHIP_R300 || |
468 | rdev->family == CHIP_R350) { |
467 | rdev->family == CHIP_R350) { |
469 | ddc_line = RADEON_GPIO_DVI_DDC; |
468 | ddc_line = RADEON_GPIO_DVI_DDC; |
470 | ddc = DDC_DVI; |
469 | ddc = DDC_DVI; |
471 | } else |
470 | } else |
472 | ddc_line = RADEON_GPIO_MONID; |
471 | ddc_line = RADEON_GPIO_MONID; |
473 | break; |
472 | break; |
474 | case DDC_CRT2: |
473 | case DDC_CRT2: |
475 | if (rdev->family == CHIP_R200 || |
474 | if (rdev->family == CHIP_R200 || |
476 | rdev->family == CHIP_R300 || |
475 | rdev->family == CHIP_R300 || |
477 | rdev->family == CHIP_R350) { |
476 | rdev->family == CHIP_R350) { |
478 | ddc_line = RADEON_GPIO_DVI_DDC; |
477 | ddc_line = RADEON_GPIO_DVI_DDC; |
479 | ddc = DDC_DVI; |
478 | ddc = DDC_DVI; |
480 | } else if (rdev->family == CHIP_RS300 || |
479 | } else if (rdev->family == CHIP_RS300 || |
481 | rdev->family == CHIP_RS400 || |
480 | rdev->family == CHIP_RS400 || |
482 | rdev->family == CHIP_RS480) |
481 | rdev->family == CHIP_RS480) |
483 | ddc_line = RADEON_GPIO_MONID; |
482 | ddc_line = RADEON_GPIO_MONID; |
484 | else if (rdev->family >= CHIP_RV350) { |
483 | else if (rdev->family >= CHIP_RV350) { |
485 | ddc_line = RADEON_GPIO_MONID; |
484 | ddc_line = RADEON_GPIO_MONID; |
486 | ddc = DDC_MONID; |
485 | ddc = DDC_MONID; |
487 | } else |
486 | } else |
488 | ddc_line = RADEON_GPIO_CRT2_DDC; |
487 | ddc_line = RADEON_GPIO_CRT2_DDC; |
489 | break; |
488 | break; |
490 | } |
489 | } |
491 | 490 | ||
492 | if (ddc_line == RADEON_GPIOPAD_MASK) { |
491 | if (ddc_line == RADEON_GPIOPAD_MASK) { |
493 | i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; |
492 | i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; |
494 | i2c.mask_data_reg = RADEON_GPIOPAD_MASK; |
493 | i2c.mask_data_reg = RADEON_GPIOPAD_MASK; |
495 | i2c.a_clk_reg = RADEON_GPIOPAD_A; |
494 | i2c.a_clk_reg = RADEON_GPIOPAD_A; |
496 | i2c.a_data_reg = RADEON_GPIOPAD_A; |
495 | i2c.a_data_reg = RADEON_GPIOPAD_A; |
497 | i2c.en_clk_reg = RADEON_GPIOPAD_EN; |
496 | i2c.en_clk_reg = RADEON_GPIOPAD_EN; |
498 | i2c.en_data_reg = RADEON_GPIOPAD_EN; |
497 | i2c.en_data_reg = RADEON_GPIOPAD_EN; |
499 | i2c.y_clk_reg = RADEON_GPIOPAD_Y; |
498 | i2c.y_clk_reg = RADEON_GPIOPAD_Y; |
500 | i2c.y_data_reg = RADEON_GPIOPAD_Y; |
499 | i2c.y_data_reg = RADEON_GPIOPAD_Y; |
501 | } else if (ddc_line == RADEON_MDGPIO_MASK) { |
500 | } else if (ddc_line == RADEON_MDGPIO_MASK) { |
502 | i2c.mask_clk_reg = RADEON_MDGPIO_MASK; |
501 | i2c.mask_clk_reg = RADEON_MDGPIO_MASK; |
503 | i2c.mask_data_reg = RADEON_MDGPIO_MASK; |
502 | i2c.mask_data_reg = RADEON_MDGPIO_MASK; |
504 | i2c.a_clk_reg = RADEON_MDGPIO_A; |
503 | i2c.a_clk_reg = RADEON_MDGPIO_A; |
505 | i2c.a_data_reg = RADEON_MDGPIO_A; |
504 | i2c.a_data_reg = RADEON_MDGPIO_A; |
506 | i2c.en_clk_reg = RADEON_MDGPIO_EN; |
505 | i2c.en_clk_reg = RADEON_MDGPIO_EN; |
507 | i2c.en_data_reg = RADEON_MDGPIO_EN; |
506 | i2c.en_data_reg = RADEON_MDGPIO_EN; |
508 | i2c.y_clk_reg = RADEON_MDGPIO_Y; |
507 | i2c.y_clk_reg = RADEON_MDGPIO_Y; |
509 | i2c.y_data_reg = RADEON_MDGPIO_Y; |
508 | i2c.y_data_reg = RADEON_MDGPIO_Y; |
510 | } else { |
509 | } else { |
511 | i2c.mask_clk_reg = ddc_line; |
510 | i2c.mask_clk_reg = ddc_line; |
512 | i2c.mask_data_reg = ddc_line; |
511 | i2c.mask_data_reg = ddc_line; |
513 | i2c.a_clk_reg = ddc_line; |
512 | i2c.a_clk_reg = ddc_line; |
514 | i2c.a_data_reg = ddc_line; |
513 | i2c.a_data_reg = ddc_line; |
515 | i2c.en_clk_reg = ddc_line; |
514 | i2c.en_clk_reg = ddc_line; |
516 | i2c.en_data_reg = ddc_line; |
515 | i2c.en_data_reg = ddc_line; |
517 | i2c.y_clk_reg = ddc_line; |
516 | i2c.y_clk_reg = ddc_line; |
518 | i2c.y_data_reg = ddc_line; |
517 | i2c.y_data_reg = ddc_line; |
519 | } |
518 | } |
520 | 519 | ||
521 | if (clk_mask && data_mask) { |
520 | if (clk_mask && data_mask) { |
522 | /* system specific masks */ |
521 | /* system specific masks */ |
523 | i2c.mask_clk_mask = clk_mask; |
522 | i2c.mask_clk_mask = clk_mask; |
524 | i2c.mask_data_mask = data_mask; |
523 | i2c.mask_data_mask = data_mask; |
525 | i2c.a_clk_mask = clk_mask; |
524 | i2c.a_clk_mask = clk_mask; |
526 | i2c.a_data_mask = data_mask; |
525 | i2c.a_data_mask = data_mask; |
527 | i2c.en_clk_mask = clk_mask; |
526 | i2c.en_clk_mask = clk_mask; |
528 | i2c.en_data_mask = data_mask; |
527 | i2c.en_data_mask = data_mask; |
529 | i2c.y_clk_mask = clk_mask; |
528 | i2c.y_clk_mask = clk_mask; |
530 | i2c.y_data_mask = data_mask; |
529 | i2c.y_data_mask = data_mask; |
531 | } else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
530 | } else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
532 | (ddc_line == RADEON_MDGPIO_MASK)) { |
531 | (ddc_line == RADEON_MDGPIO_MASK)) { |
533 | /* default gpiopad masks */ |
532 | /* default gpiopad masks */ |
534 | i2c.mask_clk_mask = (0x20 << 8); |
533 | i2c.mask_clk_mask = (0x20 << 8); |
535 | i2c.mask_data_mask = 0x80; |
534 | i2c.mask_data_mask = 0x80; |
536 | i2c.a_clk_mask = (0x20 << 8); |
535 | i2c.a_clk_mask = (0x20 << 8); |
537 | i2c.a_data_mask = 0x80; |
536 | i2c.a_data_mask = 0x80; |
538 | i2c.en_clk_mask = (0x20 << 8); |
537 | i2c.en_clk_mask = (0x20 << 8); |
539 | i2c.en_data_mask = 0x80; |
538 | i2c.en_data_mask = 0x80; |
540 | i2c.y_clk_mask = (0x20 << 8); |
539 | i2c.y_clk_mask = (0x20 << 8); |
541 | i2c.y_data_mask = 0x80; |
540 | i2c.y_data_mask = 0x80; |
542 | } else { |
541 | } else { |
543 | /* default masks for ddc pads */ |
542 | /* default masks for ddc pads */ |
544 | i2c.mask_clk_mask = RADEON_GPIO_MASK_1; |
543 | i2c.mask_clk_mask = RADEON_GPIO_MASK_1; |
545 | i2c.mask_data_mask = RADEON_GPIO_MASK_0; |
544 | i2c.mask_data_mask = RADEON_GPIO_MASK_0; |
546 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
545 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
547 | i2c.a_data_mask = RADEON_GPIO_A_0; |
546 | i2c.a_data_mask = RADEON_GPIO_A_0; |
548 | i2c.en_clk_mask = RADEON_GPIO_EN_1; |
547 | i2c.en_clk_mask = RADEON_GPIO_EN_1; |
549 | i2c.en_data_mask = RADEON_GPIO_EN_0; |
548 | i2c.en_data_mask = RADEON_GPIO_EN_0; |
550 | i2c.y_clk_mask = RADEON_GPIO_Y_1; |
549 | i2c.y_clk_mask = RADEON_GPIO_Y_1; |
551 | i2c.y_data_mask = RADEON_GPIO_Y_0; |
550 | i2c.y_data_mask = RADEON_GPIO_Y_0; |
552 | } |
551 | } |
553 | 552 | ||
554 | switch (rdev->family) { |
553 | switch (rdev->family) { |
555 | case CHIP_R100: |
554 | case CHIP_R100: |
556 | case CHIP_RV100: |
555 | case CHIP_RV100: |
557 | case CHIP_RS100: |
556 | case CHIP_RS100: |
558 | case CHIP_RV200: |
557 | case CHIP_RV200: |
559 | case CHIP_RS200: |
558 | case CHIP_RS200: |
560 | case CHIP_RS300: |
559 | case CHIP_RS300: |
561 | switch (ddc_line) { |
560 | switch (ddc_line) { |
562 | case RADEON_GPIO_DVI_DDC: |
561 | case RADEON_GPIO_DVI_DDC: |
563 | i2c.hw_capable = true; |
562 | i2c.hw_capable = true; |
564 | break; |
563 | break; |
565 | default: |
564 | default: |
566 | i2c.hw_capable = false; |
565 | i2c.hw_capable = false; |
567 | break; |
566 | break; |
568 | } |
567 | } |
569 | break; |
568 | break; |
570 | case CHIP_R200: |
569 | case CHIP_R200: |
571 | switch (ddc_line) { |
570 | switch (ddc_line) { |
572 | case RADEON_GPIO_DVI_DDC: |
571 | case RADEON_GPIO_DVI_DDC: |
573 | case RADEON_GPIO_MONID: |
572 | case RADEON_GPIO_MONID: |
574 | i2c.hw_capable = true; |
573 | i2c.hw_capable = true; |
575 | break; |
574 | break; |
576 | default: |
575 | default: |
577 | i2c.hw_capable = false; |
576 | i2c.hw_capable = false; |
578 | break; |
577 | break; |
579 | } |
578 | } |
580 | break; |
579 | break; |
581 | case CHIP_RV250: |
580 | case CHIP_RV250: |
582 | case CHIP_RV280: |
581 | case CHIP_RV280: |
583 | switch (ddc_line) { |
582 | switch (ddc_line) { |
584 | case RADEON_GPIO_VGA_DDC: |
583 | case RADEON_GPIO_VGA_DDC: |
585 | case RADEON_GPIO_DVI_DDC: |
584 | case RADEON_GPIO_DVI_DDC: |
586 | case RADEON_GPIO_CRT2_DDC: |
585 | case RADEON_GPIO_CRT2_DDC: |
587 | i2c.hw_capable = true; |
586 | i2c.hw_capable = true; |
588 | break; |
587 | break; |
589 | default: |
588 | default: |
590 | i2c.hw_capable = false; |
589 | i2c.hw_capable = false; |
591 | break; |
590 | break; |
592 | } |
591 | } |
593 | break; |
592 | break; |
594 | case CHIP_R300: |
593 | case CHIP_R300: |
595 | case CHIP_R350: |
594 | case CHIP_R350: |
596 | switch (ddc_line) { |
595 | switch (ddc_line) { |
597 | case RADEON_GPIO_VGA_DDC: |
596 | case RADEON_GPIO_VGA_DDC: |
598 | case RADEON_GPIO_DVI_DDC: |
597 | case RADEON_GPIO_DVI_DDC: |
599 | i2c.hw_capable = true; |
598 | i2c.hw_capable = true; |
600 | break; |
599 | break; |
601 | default: |
600 | default: |
602 | i2c.hw_capable = false; |
601 | i2c.hw_capable = false; |
603 | break; |
602 | break; |
604 | } |
603 | } |
605 | break; |
604 | break; |
606 | case CHIP_RV350: |
605 | case CHIP_RV350: |
607 | case CHIP_RV380: |
606 | case CHIP_RV380: |
608 | case CHIP_RS400: |
607 | case CHIP_RS400: |
609 | case CHIP_RS480: |
608 | case CHIP_RS480: |
610 | switch (ddc_line) { |
609 | switch (ddc_line) { |
611 | case RADEON_GPIO_VGA_DDC: |
610 | case RADEON_GPIO_VGA_DDC: |
612 | case RADEON_GPIO_DVI_DDC: |
611 | case RADEON_GPIO_DVI_DDC: |
613 | i2c.hw_capable = true; |
612 | i2c.hw_capable = true; |
614 | break; |
613 | break; |
615 | case RADEON_GPIO_MONID: |
614 | case RADEON_GPIO_MONID: |
616 | /* hw i2c on RADEON_GPIO_MONID doesn't seem to work |
615 | /* hw i2c on RADEON_GPIO_MONID doesn't seem to work |
617 | * reliably on some pre-r4xx hardware; not sure why. |
616 | * reliably on some pre-r4xx hardware; not sure why. |
618 | */ |
617 | */ |
619 | i2c.hw_capable = false; |
618 | i2c.hw_capable = false; |
620 | break; |
619 | break; |
621 | default: |
620 | default: |
622 | i2c.hw_capable = false; |
621 | i2c.hw_capable = false; |
623 | break; |
622 | break; |
624 | } |
623 | } |
625 | break; |
624 | break; |
626 | default: |
625 | default: |
627 | i2c.hw_capable = false; |
626 | i2c.hw_capable = false; |
628 | break; |
627 | break; |
629 | } |
628 | } |
630 | i2c.mm_i2c = false; |
629 | i2c.mm_i2c = false; |
631 | 630 | ||
632 | i2c.i2c_id = ddc; |
631 | i2c.i2c_id = ddc; |
633 | i2c.hpd = RADEON_HPD_NONE; |
632 | i2c.hpd = RADEON_HPD_NONE; |
634 | 633 | ||
635 | if (ddc_line) |
634 | if (ddc_line) |
636 | i2c.valid = true; |
635 | i2c.valid = true; |
637 | else |
636 | else |
638 | i2c.valid = false; |
637 | i2c.valid = false; |
639 | 638 | ||
640 | return i2c; |
639 | return i2c; |
641 | } |
640 | } |
642 | 641 | ||
643 | static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) |
642 | static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) |
644 | { |
643 | { |
645 | struct drm_device *dev = rdev->ddev; |
644 | struct drm_device *dev = rdev->ddev; |
646 | struct radeon_i2c_bus_rec i2c; |
645 | struct radeon_i2c_bus_rec i2c; |
647 | u16 offset; |
646 | u16 offset; |
648 | u8 id, blocks, clk, data; |
647 | u8 id, blocks, clk, data; |
649 | int i; |
648 | int i; |
650 | 649 | ||
651 | i2c.valid = false; |
650 | i2c.valid = false; |
652 | 651 | ||
653 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
652 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
654 | if (offset) { |
653 | if (offset) { |
655 | blocks = RBIOS8(offset + 2); |
654 | blocks = RBIOS8(offset + 2); |
656 | for (i = 0; i < blocks; i++) { |
655 | for (i = 0; i < blocks; i++) { |
657 | id = RBIOS8(offset + 3 + (i * 5) + 0); |
656 | id = RBIOS8(offset + 3 + (i * 5) + 0); |
658 | if (id == 136) { |
657 | if (id == 136) { |
659 | clk = RBIOS8(offset + 3 + (i * 5) + 3); |
658 | clk = RBIOS8(offset + 3 + (i * 5) + 3); |
660 | data = RBIOS8(offset + 3 + (i * 5) + 4); |
659 | data = RBIOS8(offset + 3 + (i * 5) + 4); |
661 | /* gpiopad */ |
660 | /* gpiopad */ |
662 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
661 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
663 | (1 << clk), (1 << data)); |
662 | (1 << clk), (1 << data)); |
664 | break; |
663 | break; |
665 | } |
664 | } |
666 | } |
665 | } |
667 | } |
666 | } |
668 | return i2c; |
667 | return i2c; |
669 | } |
668 | } |
670 | 669 | ||
671 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
670 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
672 | { |
671 | { |
673 | struct drm_device *dev = rdev->ddev; |
672 | struct drm_device *dev = rdev->ddev; |
674 | struct radeon_i2c_bus_rec i2c; |
673 | struct radeon_i2c_bus_rec i2c; |
675 | 674 | ||
676 | /* actual hw pads |
675 | /* actual hw pads |
677 | * r1xx/rs2xx/rs3xx |
676 | * r1xx/rs2xx/rs3xx |
678 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
677 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
679 | * r200 |
678 | * r200 |
680 | * 0x60, 0x64, 0x68, mm |
679 | * 0x60, 0x64, 0x68, mm |
681 | * r300/r350 |
680 | * r300/r350 |
682 | * 0x60, 0x64, mm |
681 | * 0x60, 0x64, mm |
683 | * rv2xx/rv3xx/rs4xx |
682 | * rv2xx/rv3xx/rs4xx |
684 | * 0x60, 0x64, 0x68, gpiopads, mm |
683 | * 0x60, 0x64, 0x68, gpiopads, mm |
685 | */ |
684 | */ |
686 | 685 | ||
687 | /* 0x60 */ |
686 | /* 0x60 */ |
688 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
687 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
689 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
688 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
690 | /* 0x64 */ |
689 | /* 0x64 */ |
691 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
690 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
692 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
691 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
693 | 692 | ||
694 | /* mm i2c */ |
693 | /* mm i2c */ |
695 | i2c.valid = true; |
694 | i2c.valid = true; |
696 | i2c.hw_capable = true; |
695 | i2c.hw_capable = true; |
697 | i2c.mm_i2c = true; |
696 | i2c.mm_i2c = true; |
698 | i2c.i2c_id = 0xa0; |
697 | i2c.i2c_id = 0xa0; |
699 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
698 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
700 | 699 | ||
701 | if (rdev->family == CHIP_R300 || |
700 | if (rdev->family == CHIP_R300 || |
702 | rdev->family == CHIP_R350) { |
701 | rdev->family == CHIP_R350) { |
703 | /* only 2 sw i2c pads */ |
702 | /* only 2 sw i2c pads */ |
704 | } else if (rdev->family == CHIP_RS300 || |
703 | } else if (rdev->family == CHIP_RS300 || |
705 | rdev->family == CHIP_RS400 || |
704 | rdev->family == CHIP_RS400 || |
706 | rdev->family == CHIP_RS480) { |
705 | rdev->family == CHIP_RS480) { |
707 | /* 0x68 */ |
706 | /* 0x68 */ |
708 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
707 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
709 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
708 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
710 | 709 | ||
711 | /* gpiopad */ |
710 | /* gpiopad */ |
712 | i2c = radeon_combios_get_i2c_info_from_table(rdev); |
711 | i2c = radeon_combios_get_i2c_info_from_table(rdev); |
713 | if (i2c.valid) |
712 | if (i2c.valid) |
714 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
713 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
715 | } else if ((rdev->family == CHIP_R200) || |
714 | } else if ((rdev->family == CHIP_R200) || |
716 | (rdev->family >= CHIP_R300)) { |
715 | (rdev->family >= CHIP_R300)) { |
717 | /* 0x68 */ |
716 | /* 0x68 */ |
718 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
717 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
719 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
718 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
720 | } else { |
719 | } else { |
721 | /* 0x68 */ |
720 | /* 0x68 */ |
722 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
721 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
723 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
722 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
724 | /* 0x6c */ |
723 | /* 0x6c */ |
725 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
724 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
726 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
725 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
727 | } |
726 | } |
728 | } |
727 | } |
729 | 728 | ||
730 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
729 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
731 | { |
730 | { |
732 | struct radeon_device *rdev = dev->dev_private; |
731 | struct radeon_device *rdev = dev->dev_private; |
733 | uint16_t pll_info; |
732 | uint16_t pll_info; |
734 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
733 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
735 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
734 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
736 | struct radeon_pll *spll = &rdev->clock.spll; |
735 | struct radeon_pll *spll = &rdev->clock.spll; |
737 | struct radeon_pll *mpll = &rdev->clock.mpll; |
736 | struct radeon_pll *mpll = &rdev->clock.mpll; |
738 | int8_t rev; |
737 | int8_t rev; |
739 | uint16_t sclk, mclk; |
738 | uint16_t sclk, mclk; |
740 | 739 | ||
741 | pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); |
740 | pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); |
742 | if (pll_info) { |
741 | if (pll_info) { |
743 | rev = RBIOS8(pll_info); |
742 | rev = RBIOS8(pll_info); |
744 | 743 | ||
745 | /* pixel clocks */ |
744 | /* pixel clocks */ |
746 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); |
745 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); |
747 | p1pll->reference_div = RBIOS16(pll_info + 0x10); |
746 | p1pll->reference_div = RBIOS16(pll_info + 0x10); |
748 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
747 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
749 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
748 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
750 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
749 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
751 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
750 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
752 | 751 | ||
753 | if (rev > 9) { |
752 | if (rev > 9) { |
754 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
753 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
755 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); |
754 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); |
756 | } else { |
755 | } else { |
757 | p1pll->pll_in_min = 40; |
756 | p1pll->pll_in_min = 40; |
758 | p1pll->pll_in_max = 500; |
757 | p1pll->pll_in_max = 500; |
759 | } |
758 | } |
760 | *p2pll = *p1pll; |
759 | *p2pll = *p1pll; |
761 | 760 | ||
762 | /* system clock */ |
761 | /* system clock */ |
763 | spll->reference_freq = RBIOS16(pll_info + 0x1a); |
762 | spll->reference_freq = RBIOS16(pll_info + 0x1a); |
764 | spll->reference_div = RBIOS16(pll_info + 0x1c); |
763 | spll->reference_div = RBIOS16(pll_info + 0x1c); |
765 | spll->pll_out_min = RBIOS32(pll_info + 0x1e); |
764 | spll->pll_out_min = RBIOS32(pll_info + 0x1e); |
766 | spll->pll_out_max = RBIOS32(pll_info + 0x22); |
765 | spll->pll_out_max = RBIOS32(pll_info + 0x22); |
767 | 766 | ||
768 | if (rev > 10) { |
767 | if (rev > 10) { |
769 | spll->pll_in_min = RBIOS32(pll_info + 0x48); |
768 | spll->pll_in_min = RBIOS32(pll_info + 0x48); |
770 | spll->pll_in_max = RBIOS32(pll_info + 0x4c); |
769 | spll->pll_in_max = RBIOS32(pll_info + 0x4c); |
771 | } else { |
770 | } else { |
772 | /* ??? */ |
771 | /* ??? */ |
773 | spll->pll_in_min = 40; |
772 | spll->pll_in_min = 40; |
774 | spll->pll_in_max = 500; |
773 | spll->pll_in_max = 500; |
775 | } |
774 | } |
776 | 775 | ||
777 | /* memory clock */ |
776 | /* memory clock */ |
778 | mpll->reference_freq = RBIOS16(pll_info + 0x26); |
777 | mpll->reference_freq = RBIOS16(pll_info + 0x26); |
779 | mpll->reference_div = RBIOS16(pll_info + 0x28); |
778 | mpll->reference_div = RBIOS16(pll_info + 0x28); |
780 | mpll->pll_out_min = RBIOS32(pll_info + 0x2a); |
779 | mpll->pll_out_min = RBIOS32(pll_info + 0x2a); |
781 | mpll->pll_out_max = RBIOS32(pll_info + 0x2e); |
780 | mpll->pll_out_max = RBIOS32(pll_info + 0x2e); |
782 | 781 | ||
783 | if (rev > 10) { |
782 | if (rev > 10) { |
784 | mpll->pll_in_min = RBIOS32(pll_info + 0x5a); |
783 | mpll->pll_in_min = RBIOS32(pll_info + 0x5a); |
785 | mpll->pll_in_max = RBIOS32(pll_info + 0x5e); |
784 | mpll->pll_in_max = RBIOS32(pll_info + 0x5e); |
786 | } else { |
785 | } else { |
787 | /* ??? */ |
786 | /* ??? */ |
788 | mpll->pll_in_min = 40; |
787 | mpll->pll_in_min = 40; |
789 | mpll->pll_in_max = 500; |
788 | mpll->pll_in_max = 500; |
790 | } |
789 | } |
791 | 790 | ||
792 | /* default sclk/mclk */ |
791 | /* default sclk/mclk */ |
793 | sclk = RBIOS16(pll_info + 0xa); |
792 | sclk = RBIOS16(pll_info + 0xa); |
794 | mclk = RBIOS16(pll_info + 0x8); |
793 | mclk = RBIOS16(pll_info + 0x8); |
795 | if (sclk == 0) |
794 | if (sclk == 0) |
796 | sclk = 200 * 100; |
795 | sclk = 200 * 100; |
797 | if (mclk == 0) |
796 | if (mclk == 0) |
798 | mclk = 200 * 100; |
797 | mclk = 200 * 100; |
799 | 798 | ||
800 | rdev->clock.default_sclk = sclk; |
799 | rdev->clock.default_sclk = sclk; |
801 | rdev->clock.default_mclk = mclk; |
800 | rdev->clock.default_mclk = mclk; |
802 | 801 | ||
803 | if (RBIOS32(pll_info + 0x16)) |
802 | if (RBIOS32(pll_info + 0x16)) |
804 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); |
803 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); |
805 | else |
804 | else |
806 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
805 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
807 | 806 | ||
808 | return true; |
807 | return true; |
809 | } |
808 | } |
810 | return false; |
809 | return false; |
811 | } |
810 | } |
812 | 811 | ||
813 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
812 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
814 | { |
813 | { |
815 | struct drm_device *dev = rdev->ddev; |
814 | struct drm_device *dev = rdev->ddev; |
816 | u16 igp_info; |
815 | u16 igp_info; |
817 | 816 | ||
818 | /* sideport is AMD only */ |
817 | /* sideport is AMD only */ |
819 | if (rdev->family == CHIP_RS400) |
818 | if (rdev->family == CHIP_RS400) |
820 | return false; |
819 | return false; |
821 | 820 | ||
822 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
821 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
823 | 822 | ||
824 | if (igp_info) { |
823 | if (igp_info) { |
825 | if (RBIOS16(igp_info + 0x4)) |
824 | if (RBIOS16(igp_info + 0x4)) |
826 | return true; |
825 | return true; |
827 | } |
826 | } |
828 | return false; |
827 | return false; |
829 | } |
828 | } |
830 | 829 | ||
831 | static const uint32_t default_primarydac_adj[CHIP_LAST] = { |
830 | static const uint32_t default_primarydac_adj[CHIP_LAST] = { |
832 | 0x00000808, /* r100 */ |
831 | 0x00000808, /* r100 */ |
833 | 0x00000808, /* rv100 */ |
832 | 0x00000808, /* rv100 */ |
834 | 0x00000808, /* rs100 */ |
833 | 0x00000808, /* rs100 */ |
835 | 0x00000808, /* rv200 */ |
834 | 0x00000808, /* rv200 */ |
836 | 0x00000808, /* rs200 */ |
835 | 0x00000808, /* rs200 */ |
837 | 0x00000808, /* r200 */ |
836 | 0x00000808, /* r200 */ |
838 | 0x00000808, /* rv250 */ |
837 | 0x00000808, /* rv250 */ |
839 | 0x00000000, /* rs300 */ |
838 | 0x00000000, /* rs300 */ |
840 | 0x00000808, /* rv280 */ |
839 | 0x00000808, /* rv280 */ |
841 | 0x00000808, /* r300 */ |
840 | 0x00000808, /* r300 */ |
842 | 0x00000808, /* r350 */ |
841 | 0x00000808, /* r350 */ |
843 | 0x00000808, /* rv350 */ |
842 | 0x00000808, /* rv350 */ |
844 | 0x00000808, /* rv380 */ |
843 | 0x00000808, /* rv380 */ |
845 | 0x00000808, /* r420 */ |
844 | 0x00000808, /* r420 */ |
846 | 0x00000808, /* r423 */ |
845 | 0x00000808, /* r423 */ |
847 | 0x00000808, /* rv410 */ |
846 | 0x00000808, /* rv410 */ |
848 | 0x00000000, /* rs400 */ |
847 | 0x00000000, /* rs400 */ |
849 | 0x00000000, /* rs480 */ |
848 | 0x00000000, /* rs480 */ |
850 | }; |
849 | }; |
851 | 850 | ||
852 | static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, |
851 | static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, |
853 | struct radeon_encoder_primary_dac *p_dac) |
852 | struct radeon_encoder_primary_dac *p_dac) |
854 | { |
853 | { |
855 | p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; |
854 | p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; |
856 | return; |
855 | return; |
857 | } |
856 | } |
858 | 857 | ||
859 | struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct |
858 | struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct |
860 | radeon_encoder |
859 | radeon_encoder |
861 | *encoder) |
860 | *encoder) |
862 | { |
861 | { |
863 | struct drm_device *dev = encoder->base.dev; |
862 | struct drm_device *dev = encoder->base.dev; |
864 | struct radeon_device *rdev = dev->dev_private; |
863 | struct radeon_device *rdev = dev->dev_private; |
865 | uint16_t dac_info; |
864 | uint16_t dac_info; |
866 | uint8_t rev, bg, dac; |
865 | uint8_t rev, bg, dac; |
867 | struct radeon_encoder_primary_dac *p_dac = NULL; |
866 | struct radeon_encoder_primary_dac *p_dac = NULL; |
868 | int found = 0; |
867 | int found = 0; |
869 | 868 | ||
870 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), |
869 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), |
871 | GFP_KERNEL); |
870 | GFP_KERNEL); |
872 | 871 | ||
873 | if (!p_dac) |
872 | if (!p_dac) |
874 | return NULL; |
873 | return NULL; |
875 | 874 | ||
876 | /* check CRT table */ |
875 | /* check CRT table */ |
877 | dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
876 | dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
878 | if (dac_info) { |
877 | if (dac_info) { |
879 | rev = RBIOS8(dac_info) & 0x3; |
878 | rev = RBIOS8(dac_info) & 0x3; |
880 | if (rev < 2) { |
879 | if (rev < 2) { |
881 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
880 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
882 | dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; |
881 | dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; |
883 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
882 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
884 | } else { |
883 | } else { |
885 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
884 | bg = RBIOS8(dac_info + 0x2) & 0xf; |
886 | dac = RBIOS8(dac_info + 0x3) & 0xf; |
885 | dac = RBIOS8(dac_info + 0x3) & 0xf; |
887 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
886 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
888 | } |
887 | } |
889 | /* if the values are zeros, use the table */ |
888 | /* if the values are zeros, use the table */ |
890 | if ((dac == 0) || (bg == 0)) |
889 | if ((dac == 0) || (bg == 0)) |
891 | found = 0; |
890 | found = 0; |
892 | else |
891 | else |
893 | found = 1; |
892 | found = 1; |
894 | } |
893 | } |
895 | 894 | ||
896 | /* quirks */ |
895 | /* quirks */ |
897 | /* Radeon 7000 (RV100) */ |
896 | /* Radeon 7000 (RV100) */ |
898 | if (((dev->pdev->device == 0x5159) && |
897 | if (((dev->pdev->device == 0x5159) && |
899 | (dev->pdev->subsystem_vendor == 0x174B) && |
898 | (dev->pdev->subsystem_vendor == 0x174B) && |
900 | (dev->pdev->subsystem_device == 0x7c28)) || |
899 | (dev->pdev->subsystem_device == 0x7c28)) || |
901 | /* Radeon 9100 (R200) */ |
900 | /* Radeon 9100 (R200) */ |
902 | ((dev->pdev->device == 0x514D) && |
901 | ((dev->pdev->device == 0x514D) && |
903 | (dev->pdev->subsystem_vendor == 0x174B) && |
902 | (dev->pdev->subsystem_vendor == 0x174B) && |
904 | (dev->pdev->subsystem_device == 0x7149))) { |
903 | (dev->pdev->subsystem_device == 0x7149))) { |
905 | /* vbios value is bad, use the default */ |
904 | /* vbios value is bad, use the default */ |
906 | found = 0; |
905 | found = 0; |
907 | } |
906 | } |
908 | 907 | ||
909 | if (!found) /* fallback to defaults */ |
908 | if (!found) /* fallback to defaults */ |
910 | radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); |
909 | radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); |
911 | 910 | ||
912 | return p_dac; |
911 | return p_dac; |
913 | } |
912 | } |
914 | 913 | ||
915 | enum radeon_tv_std |
914 | enum radeon_tv_std |
916 | radeon_combios_get_tv_info(struct radeon_device *rdev) |
915 | radeon_combios_get_tv_info(struct radeon_device *rdev) |
917 | { |
916 | { |
918 | struct drm_device *dev = rdev->ddev; |
917 | struct drm_device *dev = rdev->ddev; |
919 | uint16_t tv_info; |
918 | uint16_t tv_info; |
920 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
919 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
921 | 920 | ||
922 | tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
921 | tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
923 | if (tv_info) { |
922 | if (tv_info) { |
924 | if (RBIOS8(tv_info + 6) == 'T') { |
923 | if (RBIOS8(tv_info + 6) == 'T') { |
925 | switch (RBIOS8(tv_info + 7) & 0xf) { |
924 | switch (RBIOS8(tv_info + 7) & 0xf) { |
926 | case 1: |
925 | case 1: |
927 | tv_std = TV_STD_NTSC; |
926 | tv_std = TV_STD_NTSC; |
928 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
927 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
929 | break; |
928 | break; |
930 | case 2: |
929 | case 2: |
931 | tv_std = TV_STD_PAL; |
930 | tv_std = TV_STD_PAL; |
932 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
931 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
933 | break; |
932 | break; |
934 | case 3: |
933 | case 3: |
935 | tv_std = TV_STD_PAL_M; |
934 | tv_std = TV_STD_PAL_M; |
936 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
935 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
937 | break; |
936 | break; |
938 | case 4: |
937 | case 4: |
939 | tv_std = TV_STD_PAL_60; |
938 | tv_std = TV_STD_PAL_60; |
940 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
939 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
941 | break; |
940 | break; |
942 | case 5: |
941 | case 5: |
943 | tv_std = TV_STD_NTSC_J; |
942 | tv_std = TV_STD_NTSC_J; |
944 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
943 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
945 | break; |
944 | break; |
946 | case 6: |
945 | case 6: |
947 | tv_std = TV_STD_SCART_PAL; |
946 | tv_std = TV_STD_SCART_PAL; |
948 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
947 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
949 | break; |
948 | break; |
950 | default: |
949 | default: |
951 | tv_std = TV_STD_NTSC; |
950 | tv_std = TV_STD_NTSC; |
952 | DRM_DEBUG_KMS |
951 | DRM_DEBUG_KMS |
953 | ("Unknown TV standard; defaulting to NTSC\n"); |
952 | ("Unknown TV standard; defaulting to NTSC\n"); |
954 | break; |
953 | break; |
955 | } |
954 | } |
956 | 955 | ||
957 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
956 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
958 | case 0: |
957 | case 0: |
959 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
958 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
960 | break; |
959 | break; |
961 | case 1: |
960 | case 1: |
962 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
961 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
963 | break; |
962 | break; |
964 | case 2: |
963 | case 2: |
965 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
964 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
966 | break; |
965 | break; |
967 | case 3: |
966 | case 3: |
968 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
967 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
969 | break; |
968 | break; |
970 | default: |
969 | default: |
971 | break; |
970 | break; |
972 | } |
971 | } |
973 | } |
972 | } |
974 | } |
973 | } |
975 | return tv_std; |
974 | return tv_std; |
976 | } |
975 | } |
977 | 976 | ||
978 | static const uint32_t default_tvdac_adj[CHIP_LAST] = { |
977 | static const uint32_t default_tvdac_adj[CHIP_LAST] = { |
979 | 0x00000000, /* r100 */ |
978 | 0x00000000, /* r100 */ |
980 | 0x00280000, /* rv100 */ |
979 | 0x00280000, /* rv100 */ |
981 | 0x00000000, /* rs100 */ |
980 | 0x00000000, /* rs100 */ |
982 | 0x00880000, /* rv200 */ |
981 | 0x00880000, /* rv200 */ |
983 | 0x00000000, /* rs200 */ |
982 | 0x00000000, /* rs200 */ |
984 | 0x00000000, /* r200 */ |
983 | 0x00000000, /* r200 */ |
985 | 0x00770000, /* rv250 */ |
984 | 0x00770000, /* rv250 */ |
986 | 0x00290000, /* rs300 */ |
985 | 0x00290000, /* rs300 */ |
987 | 0x00560000, /* rv280 */ |
986 | 0x00560000, /* rv280 */ |
988 | 0x00780000, /* r300 */ |
987 | 0x00780000, /* r300 */ |
989 | 0x00770000, /* r350 */ |
988 | 0x00770000, /* r350 */ |
990 | 0x00780000, /* rv350 */ |
989 | 0x00780000, /* rv350 */ |
991 | 0x00780000, /* rv380 */ |
990 | 0x00780000, /* rv380 */ |
992 | 0x01080000, /* r420 */ |
991 | 0x01080000, /* r420 */ |
993 | 0x01080000, /* r423 */ |
992 | 0x01080000, /* r423 */ |
994 | 0x01080000, /* rv410 */ |
993 | 0x01080000, /* rv410 */ |
995 | 0x00780000, /* rs400 */ |
994 | 0x00780000, /* rs400 */ |
996 | 0x00780000, /* rs480 */ |
995 | 0x00780000, /* rs480 */ |
997 | }; |
996 | }; |
998 | 997 | ||
999 | static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, |
998 | static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, |
1000 | struct radeon_encoder_tv_dac *tv_dac) |
999 | struct radeon_encoder_tv_dac *tv_dac) |
1001 | { |
1000 | { |
1002 | tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; |
1001 | tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; |
1003 | if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) |
1002 | if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) |
1004 | tv_dac->ps2_tvdac_adj = 0x00880000; |
1003 | tv_dac->ps2_tvdac_adj = 0x00880000; |
1005 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1004 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1006 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1005 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1007 | return; |
1006 | return; |
1008 | } |
1007 | } |
1009 | 1008 | ||
1010 | struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct |
1009 | struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct |
1011 | radeon_encoder |
1010 | radeon_encoder |
1012 | *encoder) |
1011 | *encoder) |
1013 | { |
1012 | { |
1014 | struct drm_device *dev = encoder->base.dev; |
1013 | struct drm_device *dev = encoder->base.dev; |
1015 | struct radeon_device *rdev = dev->dev_private; |
1014 | struct radeon_device *rdev = dev->dev_private; |
1016 | uint16_t dac_info; |
1015 | uint16_t dac_info; |
1017 | uint8_t rev, bg, dac; |
1016 | uint8_t rev, bg, dac; |
1018 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
1017 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
1019 | int found = 0; |
1018 | int found = 0; |
1020 | 1019 | ||
1021 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
1020 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
1022 | if (!tv_dac) |
1021 | if (!tv_dac) |
1023 | return NULL; |
1022 | return NULL; |
1024 | 1023 | ||
1025 | /* first check TV table */ |
1024 | /* first check TV table */ |
1026 | dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
1025 | dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
1027 | if (dac_info) { |
1026 | if (dac_info) { |
1028 | rev = RBIOS8(dac_info + 0x3); |
1027 | rev = RBIOS8(dac_info + 0x3); |
1029 | if (rev > 4) { |
1028 | if (rev > 4) { |
1030 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
1029 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
1031 | dac = RBIOS8(dac_info + 0xd) & 0xf; |
1030 | dac = RBIOS8(dac_info + 0xd) & 0xf; |
1032 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1031 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1033 | 1032 | ||
1034 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
1033 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
1035 | dac = RBIOS8(dac_info + 0xf) & 0xf; |
1034 | dac = RBIOS8(dac_info + 0xf) & 0xf; |
1036 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1035 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1037 | 1036 | ||
1038 | bg = RBIOS8(dac_info + 0x10) & 0xf; |
1037 | bg = RBIOS8(dac_info + 0x10) & 0xf; |
1039 | dac = RBIOS8(dac_info + 0x11) & 0xf; |
1038 | dac = RBIOS8(dac_info + 0x11) & 0xf; |
1040 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1039 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1041 | /* if the values are all zeros, use the table */ |
1040 | /* if the values are all zeros, use the table */ |
1042 | if (tv_dac->ps2_tvdac_adj) |
1041 | if (tv_dac->ps2_tvdac_adj) |
1043 | found = 1; |
1042 | found = 1; |
1044 | } else if (rev > 1) { |
1043 | } else if (rev > 1) { |
1045 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
1044 | bg = RBIOS8(dac_info + 0xc) & 0xf; |
1046 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; |
1045 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; |
1047 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1046 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1048 | 1047 | ||
1049 | bg = RBIOS8(dac_info + 0xd) & 0xf; |
1048 | bg = RBIOS8(dac_info + 0xd) & 0xf; |
1050 | dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; |
1049 | dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; |
1051 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1050 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1052 | 1051 | ||
1053 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
1052 | bg = RBIOS8(dac_info + 0xe) & 0xf; |
1054 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
1053 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
1055 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1054 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1056 | /* if the values are all zeros, use the table */ |
1055 | /* if the values are all zeros, use the table */ |
1057 | if (tv_dac->ps2_tvdac_adj) |
1056 | if (tv_dac->ps2_tvdac_adj) |
1058 | found = 1; |
1057 | found = 1; |
1059 | } |
1058 | } |
1060 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
1059 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
1061 | } |
1060 | } |
1062 | if (!found) { |
1061 | if (!found) { |
1063 | /* then check CRT table */ |
1062 | /* then check CRT table */ |
1064 | dac_info = |
1063 | dac_info = |
1065 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
1064 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
1066 | if (dac_info) { |
1065 | if (dac_info) { |
1067 | rev = RBIOS8(dac_info) & 0x3; |
1066 | rev = RBIOS8(dac_info) & 0x3; |
1068 | if (rev < 2) { |
1067 | if (rev < 2) { |
1069 | bg = RBIOS8(dac_info + 0x3) & 0xf; |
1068 | bg = RBIOS8(dac_info + 0x3) & 0xf; |
1070 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; |
1069 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; |
1071 | tv_dac->ps2_tvdac_adj = |
1070 | tv_dac->ps2_tvdac_adj = |
1072 | (bg << 16) | (dac << 20); |
1071 | (bg << 16) | (dac << 20); |
1073 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1072 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1074 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1073 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1075 | /* if the values are all zeros, use the table */ |
1074 | /* if the values are all zeros, use the table */ |
1076 | if (tv_dac->ps2_tvdac_adj) |
1075 | if (tv_dac->ps2_tvdac_adj) |
1077 | found = 1; |
1076 | found = 1; |
1078 | } else { |
1077 | } else { |
1079 | bg = RBIOS8(dac_info + 0x4) & 0xf; |
1078 | bg = RBIOS8(dac_info + 0x4) & 0xf; |
1080 | dac = RBIOS8(dac_info + 0x5) & 0xf; |
1079 | dac = RBIOS8(dac_info + 0x5) & 0xf; |
1081 | tv_dac->ps2_tvdac_adj = |
1080 | tv_dac->ps2_tvdac_adj = |
1082 | (bg << 16) | (dac << 20); |
1081 | (bg << 16) | (dac << 20); |
1083 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1082 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1084 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1083 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1085 | /* if the values are all zeros, use the table */ |
1084 | /* if the values are all zeros, use the table */ |
1086 | if (tv_dac->ps2_tvdac_adj) |
1085 | if (tv_dac->ps2_tvdac_adj) |
1087 | found = 1; |
1086 | found = 1; |
1088 | } |
1087 | } |
1089 | } else { |
1088 | } else { |
1090 | DRM_INFO("No TV DAC info found in BIOS\n"); |
1089 | DRM_INFO("No TV DAC info found in BIOS\n"); |
1091 | } |
1090 | } |
1092 | } |
1091 | } |
1093 | 1092 | ||
1094 | if (!found) /* fallback to defaults */ |
1093 | if (!found) /* fallback to defaults */ |
1095 | radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); |
1094 | radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); |
1096 | 1095 | ||
1097 | return tv_dac; |
1096 | return tv_dac; |
1098 | } |
1097 | } |
1099 | 1098 | ||
1100 | static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct |
1099 | static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct |
1101 | radeon_device |
1100 | radeon_device |
1102 | *rdev) |
1101 | *rdev) |
1103 | { |
1102 | { |
1104 | struct radeon_encoder_lvds *lvds = NULL; |
1103 | struct radeon_encoder_lvds *lvds = NULL; |
1105 | uint32_t fp_vert_stretch, fp_horz_stretch; |
1104 | uint32_t fp_vert_stretch, fp_horz_stretch; |
1106 | uint32_t ppll_div_sel, ppll_val; |
1105 | uint32_t ppll_div_sel, ppll_val; |
1107 | uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
1106 | uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
1108 | 1107 | ||
1109 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
1108 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
1110 | 1109 | ||
1111 | if (!lvds) |
1110 | if (!lvds) |
1112 | return NULL; |
1111 | return NULL; |
1113 | 1112 | ||
1114 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); |
1113 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); |
1115 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); |
1114 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); |
1116 | 1115 | ||
1117 | /* These should be fail-safe defaults, fingers crossed */ |
1116 | /* These should be fail-safe defaults, fingers crossed */ |
1118 | lvds->panel_pwr_delay = 200; |
1117 | lvds->panel_pwr_delay = 200; |
1119 | lvds->panel_vcc_delay = 2000; |
1118 | lvds->panel_vcc_delay = 2000; |
1120 | 1119 | ||
1121 | lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
1120 | lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
1122 | lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; |
1121 | lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; |
1123 | lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; |
1122 | lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; |
1124 | 1123 | ||
1125 | if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) |
1124 | if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) |
1126 | lvds->native_mode.vdisplay = |
1125 | lvds->native_mode.vdisplay = |
1127 | ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> |
1126 | ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> |
1128 | RADEON_VERT_PANEL_SHIFT) + 1; |
1127 | RADEON_VERT_PANEL_SHIFT) + 1; |
1129 | else |
1128 | else |
1130 | lvds->native_mode.vdisplay = |
1129 | lvds->native_mode.vdisplay = |
1131 | (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; |
1130 | (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; |
1132 | 1131 | ||
1133 | if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) |
1132 | if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) |
1134 | lvds->native_mode.hdisplay = |
1133 | lvds->native_mode.hdisplay = |
1135 | (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> |
1134 | (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> |
1136 | RADEON_HORZ_PANEL_SHIFT) + 1) * 8; |
1135 | RADEON_HORZ_PANEL_SHIFT) + 1) * 8; |
1137 | else |
1136 | else |
1138 | lvds->native_mode.hdisplay = |
1137 | lvds->native_mode.hdisplay = |
1139 | ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; |
1138 | ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; |
1140 | 1139 | ||
1141 | if ((lvds->native_mode.hdisplay < 640) || |
1140 | if ((lvds->native_mode.hdisplay < 640) || |
1142 | (lvds->native_mode.vdisplay < 480)) { |
1141 | (lvds->native_mode.vdisplay < 480)) { |
1143 | lvds->native_mode.hdisplay = 640; |
1142 | lvds->native_mode.hdisplay = 640; |
1144 | lvds->native_mode.vdisplay = 480; |
1143 | lvds->native_mode.vdisplay = 480; |
1145 | } |
1144 | } |
1146 | 1145 | ||
1147 | ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; |
1146 | ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; |
1148 | ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); |
1147 | ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); |
1149 | if ((ppll_val & 0x000707ff) == 0x1bb) |
1148 | if ((ppll_val & 0x000707ff) == 0x1bb) |
1150 | lvds->use_bios_dividers = false; |
1149 | lvds->use_bios_dividers = false; |
1151 | else { |
1150 | else { |
1152 | lvds->panel_ref_divider = |
1151 | lvds->panel_ref_divider = |
1153 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
1152 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
1154 | lvds->panel_post_divider = (ppll_val >> 16) & 0x7; |
1153 | lvds->panel_post_divider = (ppll_val >> 16) & 0x7; |
1155 | lvds->panel_fb_divider = ppll_val & 0x7ff; |
1154 | lvds->panel_fb_divider = ppll_val & 0x7ff; |
1156 | 1155 | ||
1157 | if ((lvds->panel_ref_divider != 0) && |
1156 | if ((lvds->panel_ref_divider != 0) && |
1158 | (lvds->panel_fb_divider > 3)) |
1157 | (lvds->panel_fb_divider > 3)) |
1159 | lvds->use_bios_dividers = true; |
1158 | lvds->use_bios_dividers = true; |
1160 | } |
1159 | } |
1161 | lvds->panel_vcc_delay = 200; |
1160 | lvds->panel_vcc_delay = 200; |
1162 | 1161 | ||
1163 | DRM_INFO("Panel info derived from registers\n"); |
1162 | DRM_INFO("Panel info derived from registers\n"); |
1164 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1163 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1165 | lvds->native_mode.vdisplay); |
1164 | lvds->native_mode.vdisplay); |
1166 | 1165 | ||
1167 | return lvds; |
1166 | return lvds; |
1168 | } |
1167 | } |
1169 | 1168 | ||
1170 | struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder |
1169 | struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder |
1171 | *encoder) |
1170 | *encoder) |
1172 | { |
1171 | { |
1173 | struct drm_device *dev = encoder->base.dev; |
1172 | struct drm_device *dev = encoder->base.dev; |
1174 | struct radeon_device *rdev = dev->dev_private; |
1173 | struct radeon_device *rdev = dev->dev_private; |
1175 | uint16_t lcd_info; |
1174 | uint16_t lcd_info; |
1176 | uint32_t panel_setup; |
1175 | uint32_t panel_setup; |
1177 | char stmp[30]; |
1176 | char stmp[30]; |
1178 | int tmp, i; |
1177 | int tmp, i; |
1179 | struct radeon_encoder_lvds *lvds = NULL; |
1178 | struct radeon_encoder_lvds *lvds = NULL; |
1180 | 1179 | ||
1181 | lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
1180 | lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
1182 | 1181 | ||
1183 | if (lcd_info) { |
1182 | if (lcd_info) { |
1184 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
1183 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); |
1185 | 1184 | ||
1186 | if (!lvds) |
1185 | if (!lvds) |
1187 | return NULL; |
1186 | return NULL; |
1188 | 1187 | ||
1189 | for (i = 0; i < 24; i++) |
1188 | for (i = 0; i < 24; i++) |
1190 | stmp[i] = RBIOS8(lcd_info + i + 1); |
1189 | stmp[i] = RBIOS8(lcd_info + i + 1); |
1191 | stmp[24] = 0; |
1190 | stmp[24] = 0; |
1192 | 1191 | ||
1193 | DRM_INFO("Panel ID String: %s\n", stmp); |
1192 | DRM_INFO("Panel ID String: %s\n", stmp); |
1194 | 1193 | ||
1195 | lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); |
1194 | lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); |
1196 | lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); |
1195 | lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); |
1197 | 1196 | ||
1198 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1197 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1199 | lvds->native_mode.vdisplay); |
1198 | lvds->native_mode.vdisplay); |
1200 | 1199 | ||
1201 | lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); |
1200 | lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); |
1202 | lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); |
1201 | lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); |
1203 | 1202 | ||
1204 | lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); |
1203 | lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); |
1205 | lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; |
1204 | lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; |
1206 | lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; |
1205 | lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; |
1207 | 1206 | ||
1208 | lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); |
1207 | lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); |
1209 | lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); |
1208 | lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); |
1210 | lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); |
1209 | lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); |
1211 | if ((lvds->panel_ref_divider != 0) && |
1210 | if ((lvds->panel_ref_divider != 0) && |
1212 | (lvds->panel_fb_divider > 3)) |
1211 | (lvds->panel_fb_divider > 3)) |
1213 | lvds->use_bios_dividers = true; |
1212 | lvds->use_bios_dividers = true; |
1214 | 1213 | ||
1215 | panel_setup = RBIOS32(lcd_info + 0x39); |
1214 | panel_setup = RBIOS32(lcd_info + 0x39); |
1216 | lvds->lvds_gen_cntl = 0xff00; |
1215 | lvds->lvds_gen_cntl = 0xff00; |
1217 | if (panel_setup & 0x1) |
1216 | if (panel_setup & 0x1) |
1218 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; |
1217 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; |
1219 | 1218 | ||
1220 | if ((panel_setup >> 4) & 0x1) |
1219 | if ((panel_setup >> 4) & 0x1) |
1221 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; |
1220 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; |
1222 | 1221 | ||
1223 | switch ((panel_setup >> 8) & 0x7) { |
1222 | switch ((panel_setup >> 8) & 0x7) { |
1224 | case 0: |
1223 | case 0: |
1225 | lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; |
1224 | lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; |
1226 | break; |
1225 | break; |
1227 | case 1: |
1226 | case 1: |
1228 | lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; |
1227 | lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; |
1229 | break; |
1228 | break; |
1230 | case 2: |
1229 | case 2: |
1231 | lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; |
1230 | lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; |
1232 | break; |
1231 | break; |
1233 | default: |
1232 | default: |
1234 | break; |
1233 | break; |
1235 | } |
1234 | } |
1236 | 1235 | ||
1237 | if ((panel_setup >> 16) & 0x1) |
1236 | if ((panel_setup >> 16) & 0x1) |
1238 | lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; |
1237 | lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; |
1239 | 1238 | ||
1240 | if ((panel_setup >> 17) & 0x1) |
1239 | if ((panel_setup >> 17) & 0x1) |
1241 | lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; |
1240 | lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; |
1242 | 1241 | ||
1243 | if ((panel_setup >> 18) & 0x1) |
1242 | if ((panel_setup >> 18) & 0x1) |
1244 | lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; |
1243 | lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; |
1245 | 1244 | ||
1246 | if ((panel_setup >> 23) & 0x1) |
1245 | if ((panel_setup >> 23) & 0x1) |
1247 | lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; |
1246 | lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; |
1248 | 1247 | ||
1249 | lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); |
1248 | lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); |
1250 | 1249 | ||
1251 | for (i = 0; i < 32; i++) { |
1250 | for (i = 0; i < 32; i++) { |
1252 | tmp = RBIOS16(lcd_info + 64 + i * 2); |
1251 | tmp = RBIOS16(lcd_info + 64 + i * 2); |
1253 | if (tmp == 0) |
1252 | if (tmp == 0) |
1254 | break; |
1253 | break; |
1255 | 1254 | ||
1256 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
1255 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
1257 | (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
1256 | (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
1258 | u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; |
1257 | u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; |
1259 | 1258 | ||
1260 | if (hss > lvds->native_mode.hdisplay) |
1259 | if (hss > lvds->native_mode.hdisplay) |
1261 | hss = (10 - 1) * 8; |
1260 | hss = (10 - 1) * 8; |
1262 | 1261 | ||
1263 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1262 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1264 | (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; |
1263 | (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; |
1265 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
1264 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
1266 | hss; |
1265 | hss; |
1267 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
1266 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
1268 | (RBIOS8(tmp + 23) * 8); |
1267 | (RBIOS8(tmp + 23) * 8); |
1269 | 1268 | ||
1270 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
1269 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
1271 | (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); |
1270 | (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); |
1272 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
1271 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
1273 | ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); |
1272 | ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); |
1274 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1273 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1275 | ((RBIOS16(tmp + 28) & 0xf800) >> 11); |
1274 | ((RBIOS16(tmp + 28) & 0xf800) >> 11); |
1276 | 1275 | ||
1277 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
1276 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
1278 | lvds->native_mode.flags = 0; |
1277 | lvds->native_mode.flags = 0; |
1279 | /* set crtc values */ |
1278 | /* set crtc values */ |
1280 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
1279 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
1281 | 1280 | ||
1282 | } |
1281 | } |
1283 | } |
1282 | } |
1284 | } else { |
1283 | } else { |
1285 | DRM_INFO("No panel info found in BIOS\n"); |
1284 | DRM_INFO("No panel info found in BIOS\n"); |
1286 | lvds = radeon_legacy_get_lvds_info_from_regs(rdev); |
1285 | lvds = radeon_legacy_get_lvds_info_from_regs(rdev); |
1287 | } |
1286 | } |
1288 | 1287 | ||
1289 | if (lvds) |
1288 | if (lvds) |
1290 | encoder->native_mode = lvds->native_mode; |
1289 | encoder->native_mode = lvds->native_mode; |
1291 | return lvds; |
1290 | return lvds; |
1292 | } |
1291 | } |
1293 | 1292 | ||
1294 | static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { |
1293 | static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { |
1295 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ |
1294 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ |
1296 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ |
1295 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ |
1297 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ |
1296 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ |
1298 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ |
1297 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ |
1299 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ |
1298 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ |
1300 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ |
1299 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ |
1301 | {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ |
1300 | {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ |
1302 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ |
1301 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ |
1303 | {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ |
1302 | {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ |
1304 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ |
1303 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ |
1305 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ |
1304 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ |
1306 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ |
1305 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ |
1307 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ |
1306 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ |
1308 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ |
1307 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ |
1309 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ |
1308 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ |
1310 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ |
1309 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ |
1311 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ |
1310 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ |
1312 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ |
1311 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ |
1313 | }; |
1312 | }; |
1314 | 1313 | ||
1315 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1314 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1316 | struct radeon_encoder_int_tmds *tmds) |
1315 | struct radeon_encoder_int_tmds *tmds) |
1317 | { |
1316 | { |
1318 | struct drm_device *dev = encoder->base.dev; |
1317 | struct drm_device *dev = encoder->base.dev; |
1319 | struct radeon_device *rdev = dev->dev_private; |
1318 | struct radeon_device *rdev = dev->dev_private; |
1320 | int i; |
1319 | int i; |
1321 | 1320 | ||
1322 | for (i = 0; i < 4; i++) { |
1321 | for (i = 0; i < 4; i++) { |
1323 | tmds->tmds_pll[i].value = |
1322 | tmds->tmds_pll[i].value = |
1324 | default_tmds_pll[rdev->family][i].value; |
1323 | default_tmds_pll[rdev->family][i].value; |
1325 | tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; |
1324 | tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; |
1326 | } |
1325 | } |
1327 | 1326 | ||
1328 | return true; |
1327 | return true; |
1329 | } |
1328 | } |
1330 | 1329 | ||
1331 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1330 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1332 | struct radeon_encoder_int_tmds *tmds) |
1331 | struct radeon_encoder_int_tmds *tmds) |
1333 | { |
1332 | { |
1334 | struct drm_device *dev = encoder->base.dev; |
1333 | struct drm_device *dev = encoder->base.dev; |
1335 | struct radeon_device *rdev = dev->dev_private; |
1334 | struct radeon_device *rdev = dev->dev_private; |
1336 | uint16_t tmds_info; |
1335 | uint16_t tmds_info; |
1337 | int i, n; |
1336 | int i, n; |
1338 | uint8_t ver; |
1337 | uint8_t ver; |
1339 | 1338 | ||
1340 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1339 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1341 | 1340 | ||
1342 | if (tmds_info) { |
1341 | if (tmds_info) { |
1343 | ver = RBIOS8(tmds_info); |
1342 | ver = RBIOS8(tmds_info); |
1344 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
1343 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
1345 | if (ver == 3) { |
1344 | if (ver == 3) { |
1346 | n = RBIOS8(tmds_info + 5) + 1; |
1345 | n = RBIOS8(tmds_info + 5) + 1; |
1347 | if (n > 4) |
1346 | if (n > 4) |
1348 | n = 4; |
1347 | n = 4; |
1349 | for (i = 0; i < n; i++) { |
1348 | for (i = 0; i < n; i++) { |
1350 | tmds->tmds_pll[i].value = |
1349 | tmds->tmds_pll[i].value = |
1351 | RBIOS32(tmds_info + i * 10 + 0x08); |
1350 | RBIOS32(tmds_info + i * 10 + 0x08); |
1352 | tmds->tmds_pll[i].freq = |
1351 | tmds->tmds_pll[i].freq = |
1353 | RBIOS16(tmds_info + i * 10 + 0x10); |
1352 | RBIOS16(tmds_info + i * 10 + 0x10); |
1354 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1353 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1355 | tmds->tmds_pll[i].freq, |
1354 | tmds->tmds_pll[i].freq, |
1356 | tmds->tmds_pll[i].value); |
1355 | tmds->tmds_pll[i].value); |
1357 | } |
1356 | } |
1358 | } else if (ver == 4) { |
1357 | } else if (ver == 4) { |
1359 | int stride = 0; |
1358 | int stride = 0; |
1360 | n = RBIOS8(tmds_info + 5) + 1; |
1359 | n = RBIOS8(tmds_info + 5) + 1; |
1361 | if (n > 4) |
1360 | if (n > 4) |
1362 | n = 4; |
1361 | n = 4; |
1363 | for (i = 0; i < n; i++) { |
1362 | for (i = 0; i < n; i++) { |
1364 | tmds->tmds_pll[i].value = |
1363 | tmds->tmds_pll[i].value = |
1365 | RBIOS32(tmds_info + stride + 0x08); |
1364 | RBIOS32(tmds_info + stride + 0x08); |
1366 | tmds->tmds_pll[i].freq = |
1365 | tmds->tmds_pll[i].freq = |
1367 | RBIOS16(tmds_info + stride + 0x10); |
1366 | RBIOS16(tmds_info + stride + 0x10); |
1368 | if (i == 0) |
1367 | if (i == 0) |
1369 | stride += 10; |
1368 | stride += 10; |
1370 | else |
1369 | else |
1371 | stride += 6; |
1370 | stride += 6; |
1372 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1371 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1373 | tmds->tmds_pll[i].freq, |
1372 | tmds->tmds_pll[i].freq, |
1374 | tmds->tmds_pll[i].value); |
1373 | tmds->tmds_pll[i].value); |
1375 | } |
1374 | } |
1376 | } |
1375 | } |
1377 | } else { |
1376 | } else { |
1378 | DRM_INFO("No TMDS info found in BIOS\n"); |
1377 | DRM_INFO("No TMDS info found in BIOS\n"); |
1379 | return false; |
1378 | return false; |
1380 | } |
1379 | } |
1381 | return true; |
1380 | return true; |
1382 | } |
1381 | } |
1383 | 1382 | ||
1384 | bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
1383 | bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
1385 | struct radeon_encoder_ext_tmds *tmds) |
1384 | struct radeon_encoder_ext_tmds *tmds) |
1386 | { |
1385 | { |
1387 | struct drm_device *dev = encoder->base.dev; |
1386 | struct drm_device *dev = encoder->base.dev; |
1388 | struct radeon_device *rdev = dev->dev_private; |
1387 | struct radeon_device *rdev = dev->dev_private; |
1389 | struct radeon_i2c_bus_rec i2c_bus; |
1388 | struct radeon_i2c_bus_rec i2c_bus; |
1390 | 1389 | ||
1391 | /* default for macs */ |
1390 | /* default for macs */ |
1392 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1391 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1393 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1392 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1394 | 1393 | ||
1395 | /* XXX some macs have duallink chips */ |
1394 | /* XXX some macs have duallink chips */ |
1396 | switch (rdev->mode_info.connector_table) { |
1395 | switch (rdev->mode_info.connector_table) { |
1397 | case CT_POWERBOOK_EXTERNAL: |
1396 | case CT_POWERBOOK_EXTERNAL: |
1398 | case CT_MINI_EXTERNAL: |
1397 | case CT_MINI_EXTERNAL: |
1399 | default: |
1398 | default: |
1400 | tmds->dvo_chip = DVO_SIL164; |
1399 | tmds->dvo_chip = DVO_SIL164; |
1401 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1400 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1402 | break; |
1401 | break; |
1403 | } |
1402 | } |
1404 | 1403 | ||
1405 | return true; |
1404 | return true; |
1406 | } |
1405 | } |
1407 | 1406 | ||
1408 | bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
1407 | bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
1409 | struct radeon_encoder_ext_tmds *tmds) |
1408 | struct radeon_encoder_ext_tmds *tmds) |
1410 | { |
1409 | { |
1411 | struct drm_device *dev = encoder->base.dev; |
1410 | struct drm_device *dev = encoder->base.dev; |
1412 | struct radeon_device *rdev = dev->dev_private; |
1411 | struct radeon_device *rdev = dev->dev_private; |
1413 | uint16_t offset; |
1412 | uint16_t offset; |
1414 | uint8_t ver; |
1413 | uint8_t ver; |
1415 | enum radeon_combios_ddc gpio; |
1414 | enum radeon_combios_ddc gpio; |
1416 | struct radeon_i2c_bus_rec i2c_bus; |
1415 | struct radeon_i2c_bus_rec i2c_bus; |
1417 | 1416 | ||
1418 | tmds->i2c_bus = NULL; |
1417 | tmds->i2c_bus = NULL; |
1419 | if (rdev->flags & RADEON_IS_IGP) { |
1418 | if (rdev->flags & RADEON_IS_IGP) { |
1420 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1419 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1421 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1420 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1422 | tmds->dvo_chip = DVO_SIL164; |
1421 | tmds->dvo_chip = DVO_SIL164; |
1423 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1422 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1424 | } else { |
1423 | } else { |
1425 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1424 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1426 | if (offset) { |
1425 | if (offset) { |
1427 | ver = RBIOS8(offset); |
1426 | ver = RBIOS8(offset); |
1428 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
1427 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
1429 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1428 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1430 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1429 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1431 | gpio = RBIOS8(offset + 4 + 3); |
1430 | gpio = RBIOS8(offset + 4 + 3); |
1432 | if (gpio == DDC_LCD) { |
1431 | if (gpio == DDC_LCD) { |
1433 | /* MM i2c */ |
1432 | /* MM i2c */ |
1434 | i2c_bus.valid = true; |
1433 | i2c_bus.valid = true; |
1435 | i2c_bus.hw_capable = true; |
1434 | i2c_bus.hw_capable = true; |
1436 | i2c_bus.mm_i2c = true; |
1435 | i2c_bus.mm_i2c = true; |
1437 | i2c_bus.i2c_id = 0xa0; |
1436 | i2c_bus.i2c_id = 0xa0; |
1438 | } else |
1437 | } else |
1439 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
1438 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
1440 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1439 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1441 | } |
1440 | } |
1442 | } |
1441 | } |
1443 | 1442 | ||
1444 | if (!tmds->i2c_bus) { |
1443 | if (!tmds->i2c_bus) { |
1445 | DRM_INFO("No valid Ext TMDS info found in BIOS\n"); |
1444 | DRM_INFO("No valid Ext TMDS info found in BIOS\n"); |
1446 | return false; |
1445 | return false; |
1447 | } |
1446 | } |
1448 | 1447 | ||
1449 | return true; |
1448 | return true; |
1450 | } |
1449 | } |
1451 | 1450 | ||
1452 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) |
1451 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) |
1453 | { |
1452 | { |
1454 | struct radeon_device *rdev = dev->dev_private; |
1453 | struct radeon_device *rdev = dev->dev_private; |
1455 | struct radeon_i2c_bus_rec ddc_i2c; |
1454 | struct radeon_i2c_bus_rec ddc_i2c; |
1456 | struct radeon_hpd hpd; |
1455 | struct radeon_hpd hpd; |
1457 | 1456 | ||
1458 | rdev->mode_info.connector_table = radeon_connector_table; |
1457 | rdev->mode_info.connector_table = radeon_connector_table; |
1459 | if (rdev->mode_info.connector_table == CT_NONE) { |
1458 | if (rdev->mode_info.connector_table == CT_NONE) { |
1460 | #ifdef CONFIG_PPC_PMAC |
1459 | #ifdef CONFIG_PPC_PMAC |
1461 | if (of_machine_is_compatible("PowerBook3,3")) { |
1460 | if (of_machine_is_compatible("PowerBook3,3")) { |
1462 | /* powerbook with VGA */ |
1461 | /* powerbook with VGA */ |
1463 | rdev->mode_info.connector_table = CT_POWERBOOK_VGA; |
1462 | rdev->mode_info.connector_table = CT_POWERBOOK_VGA; |
1464 | } else if (of_machine_is_compatible("PowerBook3,4") || |
1463 | } else if (of_machine_is_compatible("PowerBook3,4") || |
1465 | of_machine_is_compatible("PowerBook3,5")) { |
1464 | of_machine_is_compatible("PowerBook3,5")) { |
1466 | /* powerbook with internal tmds */ |
1465 | /* powerbook with internal tmds */ |
1467 | rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; |
1466 | rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; |
1468 | } else if (of_machine_is_compatible("PowerBook5,1") || |
1467 | } else if (of_machine_is_compatible("PowerBook5,1") || |
1469 | of_machine_is_compatible("PowerBook5,2") || |
1468 | of_machine_is_compatible("PowerBook5,2") || |
1470 | of_machine_is_compatible("PowerBook5,3") || |
1469 | of_machine_is_compatible("PowerBook5,3") || |
1471 | of_machine_is_compatible("PowerBook5,4") || |
1470 | of_machine_is_compatible("PowerBook5,4") || |
1472 | of_machine_is_compatible("PowerBook5,5")) { |
1471 | of_machine_is_compatible("PowerBook5,5")) { |
1473 | /* powerbook with external single link tmds (sil164) */ |
1472 | /* powerbook with external single link tmds (sil164) */ |
1474 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1473 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1475 | } else if (of_machine_is_compatible("PowerBook5,6")) { |
1474 | } else if (of_machine_is_compatible("PowerBook5,6")) { |
1476 | /* powerbook with external dual or single link tmds */ |
1475 | /* powerbook with external dual or single link tmds */ |
1477 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1476 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1478 | } else if (of_machine_is_compatible("PowerBook5,7") || |
1477 | } else if (of_machine_is_compatible("PowerBook5,7") || |
1479 | of_machine_is_compatible("PowerBook5,8") || |
1478 | of_machine_is_compatible("PowerBook5,8") || |
1480 | of_machine_is_compatible("PowerBook5,9")) { |
1479 | of_machine_is_compatible("PowerBook5,9")) { |
1481 | /* PowerBook6,2 ? */ |
1480 | /* PowerBook6,2 ? */ |
1482 | /* powerbook with external dual link tmds (sil1178?) */ |
1481 | /* powerbook with external dual link tmds (sil1178?) */ |
1483 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1482 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1484 | } else if (of_machine_is_compatible("PowerBook4,1") || |
1483 | } else if (of_machine_is_compatible("PowerBook4,1") || |
1485 | of_machine_is_compatible("PowerBook4,2") || |
1484 | of_machine_is_compatible("PowerBook4,2") || |
1486 | of_machine_is_compatible("PowerBook4,3") || |
1485 | of_machine_is_compatible("PowerBook4,3") || |
1487 | of_machine_is_compatible("PowerBook6,3") || |
1486 | of_machine_is_compatible("PowerBook6,3") || |
1488 | of_machine_is_compatible("PowerBook6,5") || |
1487 | of_machine_is_compatible("PowerBook6,5") || |
1489 | of_machine_is_compatible("PowerBook6,7")) { |
1488 | of_machine_is_compatible("PowerBook6,7")) { |
1490 | /* ibook */ |
1489 | /* ibook */ |
1491 | rdev->mode_info.connector_table = CT_IBOOK; |
1490 | rdev->mode_info.connector_table = CT_IBOOK; |
1492 | } else if (of_machine_is_compatible("PowerMac3,5")) { |
1491 | } else if (of_machine_is_compatible("PowerMac3,5")) { |
1493 | /* PowerMac G4 Silver radeon 7500 */ |
1492 | /* PowerMac G4 Silver radeon 7500 */ |
1494 | rdev->mode_info.connector_table = CT_MAC_G4_SILVER; |
1493 | rdev->mode_info.connector_table = CT_MAC_G4_SILVER; |
1495 | } else if (of_machine_is_compatible("PowerMac4,4")) { |
1494 | } else if (of_machine_is_compatible("PowerMac4,4")) { |
1496 | /* emac */ |
1495 | /* emac */ |
1497 | rdev->mode_info.connector_table = CT_EMAC; |
1496 | rdev->mode_info.connector_table = CT_EMAC; |
1498 | } else if (of_machine_is_compatible("PowerMac10,1")) { |
1497 | } else if (of_machine_is_compatible("PowerMac10,1")) { |
1499 | /* mini with internal tmds */ |
1498 | /* mini with internal tmds */ |
1500 | rdev->mode_info.connector_table = CT_MINI_INTERNAL; |
1499 | rdev->mode_info.connector_table = CT_MINI_INTERNAL; |
1501 | } else if (of_machine_is_compatible("PowerMac10,2")) { |
1500 | } else if (of_machine_is_compatible("PowerMac10,2")) { |
1502 | /* mini with external tmds */ |
1501 | /* mini with external tmds */ |
1503 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
1502 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
1504 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
1503 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
1505 | /* PowerMac8,1 ? */ |
1504 | /* PowerMac8,1 ? */ |
1506 | /* imac g5 isight */ |
1505 | /* imac g5 isight */ |
1507 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
1506 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
1508 | } else if ((rdev->pdev->device == 0x4a48) && |
1507 | } else if ((rdev->pdev->device == 0x4a48) && |
1509 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1508 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1510 | (rdev->pdev->subsystem_device == 0x4a48)) { |
1509 | (rdev->pdev->subsystem_device == 0x4a48)) { |
1511 | /* Mac X800 */ |
1510 | /* Mac X800 */ |
1512 | rdev->mode_info.connector_table = CT_MAC_X800; |
1511 | rdev->mode_info.connector_table = CT_MAC_X800; |
1513 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
1512 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
1514 | of_machine_is_compatible("PowerMac7,3")) && |
1513 | of_machine_is_compatible("PowerMac7,3")) && |
1515 | (rdev->pdev->device == 0x4150) && |
1514 | (rdev->pdev->device == 0x4150) && |
1516 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1515 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1517 | (rdev->pdev->subsystem_device == 0x4150)) { |
1516 | (rdev->pdev->subsystem_device == 0x4150)) { |
1518 | /* Mac G5 tower 9600 */ |
1517 | /* Mac G5 tower 9600 */ |
1519 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
1518 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
1520 | } else if ((rdev->pdev->device == 0x4c66) && |
1519 | } else if ((rdev->pdev->device == 0x4c66) && |
1521 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1520 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1522 | (rdev->pdev->subsystem_device == 0x4c66)) { |
1521 | (rdev->pdev->subsystem_device == 0x4c66)) { |
1523 | /* SAM440ep RV250 embedded board */ |
1522 | /* SAM440ep RV250 embedded board */ |
1524 | rdev->mode_info.connector_table = CT_SAM440EP; |
1523 | rdev->mode_info.connector_table = CT_SAM440EP; |
1525 | } else |
1524 | } else |
1526 | #endif /* CONFIG_PPC_PMAC */ |
1525 | #endif /* CONFIG_PPC_PMAC */ |
1527 | #ifdef CONFIG_PPC64 |
1526 | #ifdef CONFIG_PPC64 |
1528 | if (ASIC_IS_RN50(rdev)) |
1527 | if (ASIC_IS_RN50(rdev)) |
1529 | rdev->mode_info.connector_table = CT_RN50_POWER; |
1528 | rdev->mode_info.connector_table = CT_RN50_POWER; |
1530 | else |
1529 | else |
1531 | #endif |
1530 | #endif |
1532 | rdev->mode_info.connector_table = CT_GENERIC; |
1531 | rdev->mode_info.connector_table = CT_GENERIC; |
1533 | } |
1532 | } |
1534 | 1533 | ||
1535 | switch (rdev->mode_info.connector_table) { |
1534 | switch (rdev->mode_info.connector_table) { |
1536 | case CT_GENERIC: |
1535 | case CT_GENERIC: |
1537 | DRM_INFO("Connector Table: %d (generic)\n", |
1536 | DRM_INFO("Connector Table: %d (generic)\n", |
1538 | rdev->mode_info.connector_table); |
1537 | rdev->mode_info.connector_table); |
1539 | /* these are the most common settings */ |
1538 | /* these are the most common settings */ |
1540 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1539 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1541 | /* VGA - primary dac */ |
1540 | /* VGA - primary dac */ |
1542 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1541 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1543 | hpd.hpd = RADEON_HPD_NONE; |
1542 | hpd.hpd = RADEON_HPD_NONE; |
1544 | radeon_add_legacy_encoder(dev, |
1543 | radeon_add_legacy_encoder(dev, |
1545 | radeon_get_encoder_enum(dev, |
1544 | radeon_get_encoder_enum(dev, |
1546 | ATOM_DEVICE_CRT1_SUPPORT, |
1545 | ATOM_DEVICE_CRT1_SUPPORT, |
1547 | 1), |
1546 | 1), |
1548 | ATOM_DEVICE_CRT1_SUPPORT); |
1547 | ATOM_DEVICE_CRT1_SUPPORT); |
1549 | radeon_add_legacy_connector(dev, 0, |
1548 | radeon_add_legacy_connector(dev, 0, |
1550 | ATOM_DEVICE_CRT1_SUPPORT, |
1549 | ATOM_DEVICE_CRT1_SUPPORT, |
1551 | DRM_MODE_CONNECTOR_VGA, |
1550 | DRM_MODE_CONNECTOR_VGA, |
1552 | &ddc_i2c, |
1551 | &ddc_i2c, |
1553 | CONNECTOR_OBJECT_ID_VGA, |
1552 | CONNECTOR_OBJECT_ID_VGA, |
1554 | &hpd); |
1553 | &hpd); |
1555 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1554 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1556 | /* LVDS */ |
1555 | /* LVDS */ |
1557 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
1556 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
1558 | hpd.hpd = RADEON_HPD_NONE; |
1557 | hpd.hpd = RADEON_HPD_NONE; |
1559 | radeon_add_legacy_encoder(dev, |
1558 | radeon_add_legacy_encoder(dev, |
1560 | radeon_get_encoder_enum(dev, |
1559 | radeon_get_encoder_enum(dev, |
1561 | ATOM_DEVICE_LCD1_SUPPORT, |
1560 | ATOM_DEVICE_LCD1_SUPPORT, |
1562 | 0), |
1561 | 0), |
1563 | ATOM_DEVICE_LCD1_SUPPORT); |
1562 | ATOM_DEVICE_LCD1_SUPPORT); |
1564 | radeon_add_legacy_connector(dev, 0, |
1563 | radeon_add_legacy_connector(dev, 0, |
1565 | ATOM_DEVICE_LCD1_SUPPORT, |
1564 | ATOM_DEVICE_LCD1_SUPPORT, |
1566 | DRM_MODE_CONNECTOR_LVDS, |
1565 | DRM_MODE_CONNECTOR_LVDS, |
1567 | &ddc_i2c, |
1566 | &ddc_i2c, |
1568 | CONNECTOR_OBJECT_ID_LVDS, |
1567 | CONNECTOR_OBJECT_ID_LVDS, |
1569 | &hpd); |
1568 | &hpd); |
1570 | 1569 | ||
1571 | /* VGA - primary dac */ |
1570 | /* VGA - primary dac */ |
1572 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1571 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1573 | hpd.hpd = RADEON_HPD_NONE; |
1572 | hpd.hpd = RADEON_HPD_NONE; |
1574 | radeon_add_legacy_encoder(dev, |
1573 | radeon_add_legacy_encoder(dev, |
1575 | radeon_get_encoder_enum(dev, |
1574 | radeon_get_encoder_enum(dev, |
1576 | ATOM_DEVICE_CRT1_SUPPORT, |
1575 | ATOM_DEVICE_CRT1_SUPPORT, |
1577 | 1), |
1576 | 1), |
1578 | ATOM_DEVICE_CRT1_SUPPORT); |
1577 | ATOM_DEVICE_CRT1_SUPPORT); |
1579 | radeon_add_legacy_connector(dev, 1, |
1578 | radeon_add_legacy_connector(dev, 1, |
1580 | ATOM_DEVICE_CRT1_SUPPORT, |
1579 | ATOM_DEVICE_CRT1_SUPPORT, |
1581 | DRM_MODE_CONNECTOR_VGA, |
1580 | DRM_MODE_CONNECTOR_VGA, |
1582 | &ddc_i2c, |
1581 | &ddc_i2c, |
1583 | CONNECTOR_OBJECT_ID_VGA, |
1582 | CONNECTOR_OBJECT_ID_VGA, |
1584 | &hpd); |
1583 | &hpd); |
1585 | } else { |
1584 | } else { |
1586 | /* DVI-I - tv dac, int tmds */ |
1585 | /* DVI-I - tv dac, int tmds */ |
1587 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1586 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1588 | hpd.hpd = RADEON_HPD_1; |
1587 | hpd.hpd = RADEON_HPD_1; |
1589 | radeon_add_legacy_encoder(dev, |
1588 | radeon_add_legacy_encoder(dev, |
1590 | radeon_get_encoder_enum(dev, |
1589 | radeon_get_encoder_enum(dev, |
1591 | ATOM_DEVICE_DFP1_SUPPORT, |
1590 | ATOM_DEVICE_DFP1_SUPPORT, |
1592 | 0), |
1591 | 0), |
1593 | ATOM_DEVICE_DFP1_SUPPORT); |
1592 | ATOM_DEVICE_DFP1_SUPPORT); |
1594 | radeon_add_legacy_encoder(dev, |
1593 | radeon_add_legacy_encoder(dev, |
1595 | radeon_get_encoder_enum(dev, |
1594 | radeon_get_encoder_enum(dev, |
1596 | ATOM_DEVICE_CRT2_SUPPORT, |
1595 | ATOM_DEVICE_CRT2_SUPPORT, |
1597 | 2), |
1596 | 2), |
1598 | ATOM_DEVICE_CRT2_SUPPORT); |
1597 | ATOM_DEVICE_CRT2_SUPPORT); |
1599 | radeon_add_legacy_connector(dev, 0, |
1598 | radeon_add_legacy_connector(dev, 0, |
1600 | ATOM_DEVICE_DFP1_SUPPORT | |
1599 | ATOM_DEVICE_DFP1_SUPPORT | |
1601 | ATOM_DEVICE_CRT2_SUPPORT, |
1600 | ATOM_DEVICE_CRT2_SUPPORT, |
1602 | DRM_MODE_CONNECTOR_DVII, |
1601 | DRM_MODE_CONNECTOR_DVII, |
1603 | &ddc_i2c, |
1602 | &ddc_i2c, |
1604 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1603 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1605 | &hpd); |
1604 | &hpd); |
1606 | 1605 | ||
1607 | /* VGA - primary dac */ |
1606 | /* VGA - primary dac */ |
1608 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1607 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1609 | hpd.hpd = RADEON_HPD_NONE; |
1608 | hpd.hpd = RADEON_HPD_NONE; |
1610 | radeon_add_legacy_encoder(dev, |
1609 | radeon_add_legacy_encoder(dev, |
1611 | radeon_get_encoder_enum(dev, |
1610 | radeon_get_encoder_enum(dev, |
1612 | ATOM_DEVICE_CRT1_SUPPORT, |
1611 | ATOM_DEVICE_CRT1_SUPPORT, |
1613 | 1), |
1612 | 1), |
1614 | ATOM_DEVICE_CRT1_SUPPORT); |
1613 | ATOM_DEVICE_CRT1_SUPPORT); |
1615 | radeon_add_legacy_connector(dev, 1, |
1614 | radeon_add_legacy_connector(dev, 1, |
1616 | ATOM_DEVICE_CRT1_SUPPORT, |
1615 | ATOM_DEVICE_CRT1_SUPPORT, |
1617 | DRM_MODE_CONNECTOR_VGA, |
1616 | DRM_MODE_CONNECTOR_VGA, |
1618 | &ddc_i2c, |
1617 | &ddc_i2c, |
1619 | CONNECTOR_OBJECT_ID_VGA, |
1618 | CONNECTOR_OBJECT_ID_VGA, |
1620 | &hpd); |
1619 | &hpd); |
1621 | } |
1620 | } |
1622 | 1621 | ||
1623 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
1622 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
1624 | /* TV - tv dac */ |
1623 | /* TV - tv dac */ |
1625 | ddc_i2c.valid = false; |
1624 | ddc_i2c.valid = false; |
1626 | hpd.hpd = RADEON_HPD_NONE; |
1625 | hpd.hpd = RADEON_HPD_NONE; |
1627 | radeon_add_legacy_encoder(dev, |
1626 | radeon_add_legacy_encoder(dev, |
1628 | radeon_get_encoder_enum(dev, |
1627 | radeon_get_encoder_enum(dev, |
1629 | ATOM_DEVICE_TV1_SUPPORT, |
1628 | ATOM_DEVICE_TV1_SUPPORT, |
1630 | 2), |
1629 | 2), |
1631 | ATOM_DEVICE_TV1_SUPPORT); |
1630 | ATOM_DEVICE_TV1_SUPPORT); |
1632 | radeon_add_legacy_connector(dev, 2, |
1631 | radeon_add_legacy_connector(dev, 2, |
1633 | ATOM_DEVICE_TV1_SUPPORT, |
1632 | ATOM_DEVICE_TV1_SUPPORT, |
1634 | DRM_MODE_CONNECTOR_SVIDEO, |
1633 | DRM_MODE_CONNECTOR_SVIDEO, |
1635 | &ddc_i2c, |
1634 | &ddc_i2c, |
1636 | CONNECTOR_OBJECT_ID_SVIDEO, |
1635 | CONNECTOR_OBJECT_ID_SVIDEO, |
1637 | &hpd); |
1636 | &hpd); |
1638 | } |
1637 | } |
1639 | break; |
1638 | break; |
1640 | case CT_IBOOK: |
1639 | case CT_IBOOK: |
1641 | DRM_INFO("Connector Table: %d (ibook)\n", |
1640 | DRM_INFO("Connector Table: %d (ibook)\n", |
1642 | rdev->mode_info.connector_table); |
1641 | rdev->mode_info.connector_table); |
1643 | /* LVDS */ |
1642 | /* LVDS */ |
1644 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1643 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1645 | hpd.hpd = RADEON_HPD_NONE; |
1644 | hpd.hpd = RADEON_HPD_NONE; |
1646 | radeon_add_legacy_encoder(dev, |
1645 | radeon_add_legacy_encoder(dev, |
1647 | radeon_get_encoder_enum(dev, |
1646 | radeon_get_encoder_enum(dev, |
1648 | ATOM_DEVICE_LCD1_SUPPORT, |
1647 | ATOM_DEVICE_LCD1_SUPPORT, |
1649 | 0), |
1648 | 0), |
1650 | ATOM_DEVICE_LCD1_SUPPORT); |
1649 | ATOM_DEVICE_LCD1_SUPPORT); |
1651 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1650 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1652 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1651 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1653 | CONNECTOR_OBJECT_ID_LVDS, |
1652 | CONNECTOR_OBJECT_ID_LVDS, |
1654 | &hpd); |
1653 | &hpd); |
1655 | /* VGA - TV DAC */ |
1654 | /* VGA - TV DAC */ |
1656 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1655 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1657 | hpd.hpd = RADEON_HPD_NONE; |
1656 | hpd.hpd = RADEON_HPD_NONE; |
1658 | radeon_add_legacy_encoder(dev, |
1657 | radeon_add_legacy_encoder(dev, |
1659 | radeon_get_encoder_enum(dev, |
1658 | radeon_get_encoder_enum(dev, |
1660 | ATOM_DEVICE_CRT2_SUPPORT, |
1659 | ATOM_DEVICE_CRT2_SUPPORT, |
1661 | 2), |
1660 | 2), |
1662 | ATOM_DEVICE_CRT2_SUPPORT); |
1661 | ATOM_DEVICE_CRT2_SUPPORT); |
1663 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1662 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1664 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1663 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1665 | CONNECTOR_OBJECT_ID_VGA, |
1664 | CONNECTOR_OBJECT_ID_VGA, |
1666 | &hpd); |
1665 | &hpd); |
1667 | /* TV - TV DAC */ |
1666 | /* TV - TV DAC */ |
1668 | ddc_i2c.valid = false; |
1667 | ddc_i2c.valid = false; |
1669 | hpd.hpd = RADEON_HPD_NONE; |
1668 | hpd.hpd = RADEON_HPD_NONE; |
1670 | radeon_add_legacy_encoder(dev, |
1669 | radeon_add_legacy_encoder(dev, |
1671 | radeon_get_encoder_enum(dev, |
1670 | radeon_get_encoder_enum(dev, |
1672 | ATOM_DEVICE_TV1_SUPPORT, |
1671 | ATOM_DEVICE_TV1_SUPPORT, |
1673 | 2), |
1672 | 2), |
1674 | ATOM_DEVICE_TV1_SUPPORT); |
1673 | ATOM_DEVICE_TV1_SUPPORT); |
1675 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1674 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1676 | DRM_MODE_CONNECTOR_SVIDEO, |
1675 | DRM_MODE_CONNECTOR_SVIDEO, |
1677 | &ddc_i2c, |
1676 | &ddc_i2c, |
1678 | CONNECTOR_OBJECT_ID_SVIDEO, |
1677 | CONNECTOR_OBJECT_ID_SVIDEO, |
1679 | &hpd); |
1678 | &hpd); |
1680 | break; |
1679 | break; |
1681 | case CT_POWERBOOK_EXTERNAL: |
1680 | case CT_POWERBOOK_EXTERNAL: |
1682 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
1681 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
1683 | rdev->mode_info.connector_table); |
1682 | rdev->mode_info.connector_table); |
1684 | /* LVDS */ |
1683 | /* LVDS */ |
1685 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1684 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1686 | hpd.hpd = RADEON_HPD_NONE; |
1685 | hpd.hpd = RADEON_HPD_NONE; |
1687 | radeon_add_legacy_encoder(dev, |
1686 | radeon_add_legacy_encoder(dev, |
1688 | radeon_get_encoder_enum(dev, |
1687 | radeon_get_encoder_enum(dev, |
1689 | ATOM_DEVICE_LCD1_SUPPORT, |
1688 | ATOM_DEVICE_LCD1_SUPPORT, |
1690 | 0), |
1689 | 0), |
1691 | ATOM_DEVICE_LCD1_SUPPORT); |
1690 | ATOM_DEVICE_LCD1_SUPPORT); |
1692 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1691 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1693 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1692 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1694 | CONNECTOR_OBJECT_ID_LVDS, |
1693 | CONNECTOR_OBJECT_ID_LVDS, |
1695 | &hpd); |
1694 | &hpd); |
1696 | /* DVI-I - primary dac, ext tmds */ |
1695 | /* DVI-I - primary dac, ext tmds */ |
1697 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1696 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1698 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1697 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1699 | radeon_add_legacy_encoder(dev, |
1698 | radeon_add_legacy_encoder(dev, |
1700 | radeon_get_encoder_enum(dev, |
1699 | radeon_get_encoder_enum(dev, |
1701 | ATOM_DEVICE_DFP2_SUPPORT, |
1700 | ATOM_DEVICE_DFP2_SUPPORT, |
1702 | 0), |
1701 | 0), |
1703 | ATOM_DEVICE_DFP2_SUPPORT); |
1702 | ATOM_DEVICE_DFP2_SUPPORT); |
1704 | radeon_add_legacy_encoder(dev, |
1703 | radeon_add_legacy_encoder(dev, |
1705 | radeon_get_encoder_enum(dev, |
1704 | radeon_get_encoder_enum(dev, |
1706 | ATOM_DEVICE_CRT1_SUPPORT, |
1705 | ATOM_DEVICE_CRT1_SUPPORT, |
1707 | 1), |
1706 | 1), |
1708 | ATOM_DEVICE_CRT1_SUPPORT); |
1707 | ATOM_DEVICE_CRT1_SUPPORT); |
1709 | /* XXX some are SL */ |
1708 | /* XXX some are SL */ |
1710 | radeon_add_legacy_connector(dev, 1, |
1709 | radeon_add_legacy_connector(dev, 1, |
1711 | ATOM_DEVICE_DFP2_SUPPORT | |
1710 | ATOM_DEVICE_DFP2_SUPPORT | |
1712 | ATOM_DEVICE_CRT1_SUPPORT, |
1711 | ATOM_DEVICE_CRT1_SUPPORT, |
1713 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1712 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1714 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
1713 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
1715 | &hpd); |
1714 | &hpd); |
1716 | /* TV - TV DAC */ |
1715 | /* TV - TV DAC */ |
1717 | ddc_i2c.valid = false; |
1716 | ddc_i2c.valid = false; |
1718 | hpd.hpd = RADEON_HPD_NONE; |
1717 | hpd.hpd = RADEON_HPD_NONE; |
1719 | radeon_add_legacy_encoder(dev, |
1718 | radeon_add_legacy_encoder(dev, |
1720 | radeon_get_encoder_enum(dev, |
1719 | radeon_get_encoder_enum(dev, |
1721 | ATOM_DEVICE_TV1_SUPPORT, |
1720 | ATOM_DEVICE_TV1_SUPPORT, |
1722 | 2), |
1721 | 2), |
1723 | ATOM_DEVICE_TV1_SUPPORT); |
1722 | ATOM_DEVICE_TV1_SUPPORT); |
1724 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1723 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1725 | DRM_MODE_CONNECTOR_SVIDEO, |
1724 | DRM_MODE_CONNECTOR_SVIDEO, |
1726 | &ddc_i2c, |
1725 | &ddc_i2c, |
1727 | CONNECTOR_OBJECT_ID_SVIDEO, |
1726 | CONNECTOR_OBJECT_ID_SVIDEO, |
1728 | &hpd); |
1727 | &hpd); |
1729 | break; |
1728 | break; |
1730 | case CT_POWERBOOK_INTERNAL: |
1729 | case CT_POWERBOOK_INTERNAL: |
1731 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
1730 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
1732 | rdev->mode_info.connector_table); |
1731 | rdev->mode_info.connector_table); |
1733 | /* LVDS */ |
1732 | /* LVDS */ |
1734 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1733 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1735 | hpd.hpd = RADEON_HPD_NONE; |
1734 | hpd.hpd = RADEON_HPD_NONE; |
1736 | radeon_add_legacy_encoder(dev, |
1735 | radeon_add_legacy_encoder(dev, |
1737 | radeon_get_encoder_enum(dev, |
1736 | radeon_get_encoder_enum(dev, |
1738 | ATOM_DEVICE_LCD1_SUPPORT, |
1737 | ATOM_DEVICE_LCD1_SUPPORT, |
1739 | 0), |
1738 | 0), |
1740 | ATOM_DEVICE_LCD1_SUPPORT); |
1739 | ATOM_DEVICE_LCD1_SUPPORT); |
1741 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1740 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1742 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1741 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1743 | CONNECTOR_OBJECT_ID_LVDS, |
1742 | CONNECTOR_OBJECT_ID_LVDS, |
1744 | &hpd); |
1743 | &hpd); |
1745 | /* DVI-I - primary dac, int tmds */ |
1744 | /* DVI-I - primary dac, int tmds */ |
1746 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1745 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1747 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1746 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1748 | radeon_add_legacy_encoder(dev, |
1747 | radeon_add_legacy_encoder(dev, |
1749 | radeon_get_encoder_enum(dev, |
1748 | radeon_get_encoder_enum(dev, |
1750 | ATOM_DEVICE_DFP1_SUPPORT, |
1749 | ATOM_DEVICE_DFP1_SUPPORT, |
1751 | 0), |
1750 | 0), |
1752 | ATOM_DEVICE_DFP1_SUPPORT); |
1751 | ATOM_DEVICE_DFP1_SUPPORT); |
1753 | radeon_add_legacy_encoder(dev, |
1752 | radeon_add_legacy_encoder(dev, |
1754 | radeon_get_encoder_enum(dev, |
1753 | radeon_get_encoder_enum(dev, |
1755 | ATOM_DEVICE_CRT1_SUPPORT, |
1754 | ATOM_DEVICE_CRT1_SUPPORT, |
1756 | 1), |
1755 | 1), |
1757 | ATOM_DEVICE_CRT1_SUPPORT); |
1756 | ATOM_DEVICE_CRT1_SUPPORT); |
1758 | radeon_add_legacy_connector(dev, 1, |
1757 | radeon_add_legacy_connector(dev, 1, |
1759 | ATOM_DEVICE_DFP1_SUPPORT | |
1758 | ATOM_DEVICE_DFP1_SUPPORT | |
1760 | ATOM_DEVICE_CRT1_SUPPORT, |
1759 | ATOM_DEVICE_CRT1_SUPPORT, |
1761 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1760 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1762 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1761 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1763 | &hpd); |
1762 | &hpd); |
1764 | /* TV - TV DAC */ |
1763 | /* TV - TV DAC */ |
1765 | ddc_i2c.valid = false; |
1764 | ddc_i2c.valid = false; |
1766 | hpd.hpd = RADEON_HPD_NONE; |
1765 | hpd.hpd = RADEON_HPD_NONE; |
1767 | radeon_add_legacy_encoder(dev, |
1766 | radeon_add_legacy_encoder(dev, |
1768 | radeon_get_encoder_enum(dev, |
1767 | radeon_get_encoder_enum(dev, |
1769 | ATOM_DEVICE_TV1_SUPPORT, |
1768 | ATOM_DEVICE_TV1_SUPPORT, |
1770 | 2), |
1769 | 2), |
1771 | ATOM_DEVICE_TV1_SUPPORT); |
1770 | ATOM_DEVICE_TV1_SUPPORT); |
1772 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1771 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1773 | DRM_MODE_CONNECTOR_SVIDEO, |
1772 | DRM_MODE_CONNECTOR_SVIDEO, |
1774 | &ddc_i2c, |
1773 | &ddc_i2c, |
1775 | CONNECTOR_OBJECT_ID_SVIDEO, |
1774 | CONNECTOR_OBJECT_ID_SVIDEO, |
1776 | &hpd); |
1775 | &hpd); |
1777 | break; |
1776 | break; |
1778 | case CT_POWERBOOK_VGA: |
1777 | case CT_POWERBOOK_VGA: |
1779 | DRM_INFO("Connector Table: %d (powerbook vga)\n", |
1778 | DRM_INFO("Connector Table: %d (powerbook vga)\n", |
1780 | rdev->mode_info.connector_table); |
1779 | rdev->mode_info.connector_table); |
1781 | /* LVDS */ |
1780 | /* LVDS */ |
1782 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1781 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1783 | hpd.hpd = RADEON_HPD_NONE; |
1782 | hpd.hpd = RADEON_HPD_NONE; |
1784 | radeon_add_legacy_encoder(dev, |
1783 | radeon_add_legacy_encoder(dev, |
1785 | radeon_get_encoder_enum(dev, |
1784 | radeon_get_encoder_enum(dev, |
1786 | ATOM_DEVICE_LCD1_SUPPORT, |
1785 | ATOM_DEVICE_LCD1_SUPPORT, |
1787 | 0), |
1786 | 0), |
1788 | ATOM_DEVICE_LCD1_SUPPORT); |
1787 | ATOM_DEVICE_LCD1_SUPPORT); |
1789 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1788 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
1790 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1789 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
1791 | CONNECTOR_OBJECT_ID_LVDS, |
1790 | CONNECTOR_OBJECT_ID_LVDS, |
1792 | &hpd); |
1791 | &hpd); |
1793 | /* VGA - primary dac */ |
1792 | /* VGA - primary dac */ |
1794 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1793 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1795 | hpd.hpd = RADEON_HPD_NONE; |
1794 | hpd.hpd = RADEON_HPD_NONE; |
1796 | radeon_add_legacy_encoder(dev, |
1795 | radeon_add_legacy_encoder(dev, |
1797 | radeon_get_encoder_enum(dev, |
1796 | radeon_get_encoder_enum(dev, |
1798 | ATOM_DEVICE_CRT1_SUPPORT, |
1797 | ATOM_DEVICE_CRT1_SUPPORT, |
1799 | 1), |
1798 | 1), |
1800 | ATOM_DEVICE_CRT1_SUPPORT); |
1799 | ATOM_DEVICE_CRT1_SUPPORT); |
1801 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
1800 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
1802 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1801 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1803 | CONNECTOR_OBJECT_ID_VGA, |
1802 | CONNECTOR_OBJECT_ID_VGA, |
1804 | &hpd); |
1803 | &hpd); |
1805 | /* TV - TV DAC */ |
1804 | /* TV - TV DAC */ |
1806 | ddc_i2c.valid = false; |
1805 | ddc_i2c.valid = false; |
1807 | hpd.hpd = RADEON_HPD_NONE; |
1806 | hpd.hpd = RADEON_HPD_NONE; |
1808 | radeon_add_legacy_encoder(dev, |
1807 | radeon_add_legacy_encoder(dev, |
1809 | radeon_get_encoder_enum(dev, |
1808 | radeon_get_encoder_enum(dev, |
1810 | ATOM_DEVICE_TV1_SUPPORT, |
1809 | ATOM_DEVICE_TV1_SUPPORT, |
1811 | 2), |
1810 | 2), |
1812 | ATOM_DEVICE_TV1_SUPPORT); |
1811 | ATOM_DEVICE_TV1_SUPPORT); |
1813 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1812 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1814 | DRM_MODE_CONNECTOR_SVIDEO, |
1813 | DRM_MODE_CONNECTOR_SVIDEO, |
1815 | &ddc_i2c, |
1814 | &ddc_i2c, |
1816 | CONNECTOR_OBJECT_ID_SVIDEO, |
1815 | CONNECTOR_OBJECT_ID_SVIDEO, |
1817 | &hpd); |
1816 | &hpd); |
1818 | break; |
1817 | break; |
1819 | case CT_MINI_EXTERNAL: |
1818 | case CT_MINI_EXTERNAL: |
1820 | DRM_INFO("Connector Table: %d (mini external tmds)\n", |
1819 | DRM_INFO("Connector Table: %d (mini external tmds)\n", |
1821 | rdev->mode_info.connector_table); |
1820 | rdev->mode_info.connector_table); |
1822 | /* DVI-I - tv dac, ext tmds */ |
1821 | /* DVI-I - tv dac, ext tmds */ |
1823 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1822 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1824 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1823 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1825 | radeon_add_legacy_encoder(dev, |
1824 | radeon_add_legacy_encoder(dev, |
1826 | radeon_get_encoder_enum(dev, |
1825 | radeon_get_encoder_enum(dev, |
1827 | ATOM_DEVICE_DFP2_SUPPORT, |
1826 | ATOM_DEVICE_DFP2_SUPPORT, |
1828 | 0), |
1827 | 0), |
1829 | ATOM_DEVICE_DFP2_SUPPORT); |
1828 | ATOM_DEVICE_DFP2_SUPPORT); |
1830 | radeon_add_legacy_encoder(dev, |
1829 | radeon_add_legacy_encoder(dev, |
1831 | radeon_get_encoder_enum(dev, |
1830 | radeon_get_encoder_enum(dev, |
1832 | ATOM_DEVICE_CRT2_SUPPORT, |
1831 | ATOM_DEVICE_CRT2_SUPPORT, |
1833 | 2), |
1832 | 2), |
1834 | ATOM_DEVICE_CRT2_SUPPORT); |
1833 | ATOM_DEVICE_CRT2_SUPPORT); |
1835 | /* XXX are any DL? */ |
1834 | /* XXX are any DL? */ |
1836 | radeon_add_legacy_connector(dev, 0, |
1835 | radeon_add_legacy_connector(dev, 0, |
1837 | ATOM_DEVICE_DFP2_SUPPORT | |
1836 | ATOM_DEVICE_DFP2_SUPPORT | |
1838 | ATOM_DEVICE_CRT2_SUPPORT, |
1837 | ATOM_DEVICE_CRT2_SUPPORT, |
1839 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1838 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1840 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1839 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1841 | &hpd); |
1840 | &hpd); |
1842 | /* TV - TV DAC */ |
1841 | /* TV - TV DAC */ |
1843 | ddc_i2c.valid = false; |
1842 | ddc_i2c.valid = false; |
1844 | hpd.hpd = RADEON_HPD_NONE; |
1843 | hpd.hpd = RADEON_HPD_NONE; |
1845 | radeon_add_legacy_encoder(dev, |
1844 | radeon_add_legacy_encoder(dev, |
1846 | radeon_get_encoder_enum(dev, |
1845 | radeon_get_encoder_enum(dev, |
1847 | ATOM_DEVICE_TV1_SUPPORT, |
1846 | ATOM_DEVICE_TV1_SUPPORT, |
1848 | 2), |
1847 | 2), |
1849 | ATOM_DEVICE_TV1_SUPPORT); |
1848 | ATOM_DEVICE_TV1_SUPPORT); |
1850 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1849 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1851 | DRM_MODE_CONNECTOR_SVIDEO, |
1850 | DRM_MODE_CONNECTOR_SVIDEO, |
1852 | &ddc_i2c, |
1851 | &ddc_i2c, |
1853 | CONNECTOR_OBJECT_ID_SVIDEO, |
1852 | CONNECTOR_OBJECT_ID_SVIDEO, |
1854 | &hpd); |
1853 | &hpd); |
1855 | break; |
1854 | break; |
1856 | case CT_MINI_INTERNAL: |
1855 | case CT_MINI_INTERNAL: |
1857 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
1856 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
1858 | rdev->mode_info.connector_table); |
1857 | rdev->mode_info.connector_table); |
1859 | /* DVI-I - tv dac, int tmds */ |
1858 | /* DVI-I - tv dac, int tmds */ |
1860 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1859 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1861 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1860 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1862 | radeon_add_legacy_encoder(dev, |
1861 | radeon_add_legacy_encoder(dev, |
1863 | radeon_get_encoder_enum(dev, |
1862 | radeon_get_encoder_enum(dev, |
1864 | ATOM_DEVICE_DFP1_SUPPORT, |
1863 | ATOM_DEVICE_DFP1_SUPPORT, |
1865 | 0), |
1864 | 0), |
1866 | ATOM_DEVICE_DFP1_SUPPORT); |
1865 | ATOM_DEVICE_DFP1_SUPPORT); |
1867 | radeon_add_legacy_encoder(dev, |
1866 | radeon_add_legacy_encoder(dev, |
1868 | radeon_get_encoder_enum(dev, |
1867 | radeon_get_encoder_enum(dev, |
1869 | ATOM_DEVICE_CRT2_SUPPORT, |
1868 | ATOM_DEVICE_CRT2_SUPPORT, |
1870 | 2), |
1869 | 2), |
1871 | ATOM_DEVICE_CRT2_SUPPORT); |
1870 | ATOM_DEVICE_CRT2_SUPPORT); |
1872 | radeon_add_legacy_connector(dev, 0, |
1871 | radeon_add_legacy_connector(dev, 0, |
1873 | ATOM_DEVICE_DFP1_SUPPORT | |
1872 | ATOM_DEVICE_DFP1_SUPPORT | |
1874 | ATOM_DEVICE_CRT2_SUPPORT, |
1873 | ATOM_DEVICE_CRT2_SUPPORT, |
1875 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1874 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
1876 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1875 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1877 | &hpd); |
1876 | &hpd); |
1878 | /* TV - TV DAC */ |
1877 | /* TV - TV DAC */ |
1879 | ddc_i2c.valid = false; |
1878 | ddc_i2c.valid = false; |
1880 | hpd.hpd = RADEON_HPD_NONE; |
1879 | hpd.hpd = RADEON_HPD_NONE; |
1881 | radeon_add_legacy_encoder(dev, |
1880 | radeon_add_legacy_encoder(dev, |
1882 | radeon_get_encoder_enum(dev, |
1881 | radeon_get_encoder_enum(dev, |
1883 | ATOM_DEVICE_TV1_SUPPORT, |
1882 | ATOM_DEVICE_TV1_SUPPORT, |
1884 | 2), |
1883 | 2), |
1885 | ATOM_DEVICE_TV1_SUPPORT); |
1884 | ATOM_DEVICE_TV1_SUPPORT); |
1886 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1885 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, |
1887 | DRM_MODE_CONNECTOR_SVIDEO, |
1886 | DRM_MODE_CONNECTOR_SVIDEO, |
1888 | &ddc_i2c, |
1887 | &ddc_i2c, |
1889 | CONNECTOR_OBJECT_ID_SVIDEO, |
1888 | CONNECTOR_OBJECT_ID_SVIDEO, |
1890 | &hpd); |
1889 | &hpd); |
1891 | break; |
1890 | break; |
1892 | case CT_IMAC_G5_ISIGHT: |
1891 | case CT_IMAC_G5_ISIGHT: |
1893 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
1892 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
1894 | rdev->mode_info.connector_table); |
1893 | rdev->mode_info.connector_table); |
1895 | /* DVI-D - int tmds */ |
1894 | /* DVI-D - int tmds */ |
1896 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1895 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1897 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1896 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1898 | radeon_add_legacy_encoder(dev, |
1897 | radeon_add_legacy_encoder(dev, |
1899 | radeon_get_encoder_enum(dev, |
1898 | radeon_get_encoder_enum(dev, |
1900 | ATOM_DEVICE_DFP1_SUPPORT, |
1899 | ATOM_DEVICE_DFP1_SUPPORT, |
1901 | 0), |
1900 | 0), |
1902 | ATOM_DEVICE_DFP1_SUPPORT); |
1901 | ATOM_DEVICE_DFP1_SUPPORT); |
1903 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, |
1902 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, |
1904 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
1903 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
1905 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
1904 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
1906 | &hpd); |
1905 | &hpd); |
1907 | /* VGA - tv dac */ |
1906 | /* VGA - tv dac */ |
1908 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1907 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1909 | hpd.hpd = RADEON_HPD_NONE; |
1908 | hpd.hpd = RADEON_HPD_NONE; |
1910 | radeon_add_legacy_encoder(dev, |
1909 | radeon_add_legacy_encoder(dev, |
1911 | radeon_get_encoder_enum(dev, |
1910 | radeon_get_encoder_enum(dev, |
1912 | ATOM_DEVICE_CRT2_SUPPORT, |
1911 | ATOM_DEVICE_CRT2_SUPPORT, |
1913 | 2), |
1912 | 2), |
1914 | ATOM_DEVICE_CRT2_SUPPORT); |
1913 | ATOM_DEVICE_CRT2_SUPPORT); |
1915 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1914 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1916 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1915 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1917 | CONNECTOR_OBJECT_ID_VGA, |
1916 | CONNECTOR_OBJECT_ID_VGA, |
1918 | &hpd); |
1917 | &hpd); |
1919 | /* TV - TV DAC */ |
1918 | /* TV - TV DAC */ |
1920 | ddc_i2c.valid = false; |
1919 | ddc_i2c.valid = false; |
1921 | hpd.hpd = RADEON_HPD_NONE; |
1920 | hpd.hpd = RADEON_HPD_NONE; |
1922 | radeon_add_legacy_encoder(dev, |
1921 | radeon_add_legacy_encoder(dev, |
1923 | radeon_get_encoder_enum(dev, |
1922 | radeon_get_encoder_enum(dev, |
1924 | ATOM_DEVICE_TV1_SUPPORT, |
1923 | ATOM_DEVICE_TV1_SUPPORT, |
1925 | 2), |
1924 | 2), |
1926 | ATOM_DEVICE_TV1_SUPPORT); |
1925 | ATOM_DEVICE_TV1_SUPPORT); |
1927 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1926 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1928 | DRM_MODE_CONNECTOR_SVIDEO, |
1927 | DRM_MODE_CONNECTOR_SVIDEO, |
1929 | &ddc_i2c, |
1928 | &ddc_i2c, |
1930 | CONNECTOR_OBJECT_ID_SVIDEO, |
1929 | CONNECTOR_OBJECT_ID_SVIDEO, |
1931 | &hpd); |
1930 | &hpd); |
1932 | break; |
1931 | break; |
1933 | case CT_EMAC: |
1932 | case CT_EMAC: |
1934 | DRM_INFO("Connector Table: %d (emac)\n", |
1933 | DRM_INFO("Connector Table: %d (emac)\n", |
1935 | rdev->mode_info.connector_table); |
1934 | rdev->mode_info.connector_table); |
1936 | /* VGA - primary dac */ |
1935 | /* VGA - primary dac */ |
1937 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1936 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1938 | hpd.hpd = RADEON_HPD_NONE; |
1937 | hpd.hpd = RADEON_HPD_NONE; |
1939 | radeon_add_legacy_encoder(dev, |
1938 | radeon_add_legacy_encoder(dev, |
1940 | radeon_get_encoder_enum(dev, |
1939 | radeon_get_encoder_enum(dev, |
1941 | ATOM_DEVICE_CRT1_SUPPORT, |
1940 | ATOM_DEVICE_CRT1_SUPPORT, |
1942 | 1), |
1941 | 1), |
1943 | ATOM_DEVICE_CRT1_SUPPORT); |
1942 | ATOM_DEVICE_CRT1_SUPPORT); |
1944 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1943 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1945 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1944 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1946 | CONNECTOR_OBJECT_ID_VGA, |
1945 | CONNECTOR_OBJECT_ID_VGA, |
1947 | &hpd); |
1946 | &hpd); |
1948 | /* VGA - tv dac */ |
1947 | /* VGA - tv dac */ |
1949 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1948 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1950 | hpd.hpd = RADEON_HPD_NONE; |
1949 | hpd.hpd = RADEON_HPD_NONE; |
1951 | radeon_add_legacy_encoder(dev, |
1950 | radeon_add_legacy_encoder(dev, |
1952 | radeon_get_encoder_enum(dev, |
1951 | radeon_get_encoder_enum(dev, |
1953 | ATOM_DEVICE_CRT2_SUPPORT, |
1952 | ATOM_DEVICE_CRT2_SUPPORT, |
1954 | 2), |
1953 | 2), |
1955 | ATOM_DEVICE_CRT2_SUPPORT); |
1954 | ATOM_DEVICE_CRT2_SUPPORT); |
1956 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1955 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1957 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1956 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1958 | CONNECTOR_OBJECT_ID_VGA, |
1957 | CONNECTOR_OBJECT_ID_VGA, |
1959 | &hpd); |
1958 | &hpd); |
1960 | /* TV - TV DAC */ |
1959 | /* TV - TV DAC */ |
1961 | ddc_i2c.valid = false; |
1960 | ddc_i2c.valid = false; |
1962 | hpd.hpd = RADEON_HPD_NONE; |
1961 | hpd.hpd = RADEON_HPD_NONE; |
1963 | radeon_add_legacy_encoder(dev, |
1962 | radeon_add_legacy_encoder(dev, |
1964 | radeon_get_encoder_enum(dev, |
1963 | radeon_get_encoder_enum(dev, |
1965 | ATOM_DEVICE_TV1_SUPPORT, |
1964 | ATOM_DEVICE_TV1_SUPPORT, |
1966 | 2), |
1965 | 2), |
1967 | ATOM_DEVICE_TV1_SUPPORT); |
1966 | ATOM_DEVICE_TV1_SUPPORT); |
1968 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1967 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
1969 | DRM_MODE_CONNECTOR_SVIDEO, |
1968 | DRM_MODE_CONNECTOR_SVIDEO, |
1970 | &ddc_i2c, |
1969 | &ddc_i2c, |
1971 | CONNECTOR_OBJECT_ID_SVIDEO, |
1970 | CONNECTOR_OBJECT_ID_SVIDEO, |
1972 | &hpd); |
1971 | &hpd); |
1973 | break; |
1972 | break; |
1974 | case CT_RN50_POWER: |
1973 | case CT_RN50_POWER: |
1975 | DRM_INFO("Connector Table: %d (rn50-power)\n", |
1974 | DRM_INFO("Connector Table: %d (rn50-power)\n", |
1976 | rdev->mode_info.connector_table); |
1975 | rdev->mode_info.connector_table); |
1977 | /* VGA - primary dac */ |
1976 | /* VGA - primary dac */ |
1978 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1977 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1979 | hpd.hpd = RADEON_HPD_NONE; |
1978 | hpd.hpd = RADEON_HPD_NONE; |
1980 | radeon_add_legacy_encoder(dev, |
1979 | radeon_add_legacy_encoder(dev, |
1981 | radeon_get_encoder_enum(dev, |
1980 | radeon_get_encoder_enum(dev, |
1982 | ATOM_DEVICE_CRT1_SUPPORT, |
1981 | ATOM_DEVICE_CRT1_SUPPORT, |
1983 | 1), |
1982 | 1), |
1984 | ATOM_DEVICE_CRT1_SUPPORT); |
1983 | ATOM_DEVICE_CRT1_SUPPORT); |
1985 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1984 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
1986 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1985 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1987 | CONNECTOR_OBJECT_ID_VGA, |
1986 | CONNECTOR_OBJECT_ID_VGA, |
1988 | &hpd); |
1987 | &hpd); |
1989 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1988 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1990 | hpd.hpd = RADEON_HPD_NONE; |
1989 | hpd.hpd = RADEON_HPD_NONE; |
1991 | radeon_add_legacy_encoder(dev, |
1990 | radeon_add_legacy_encoder(dev, |
1992 | radeon_get_encoder_enum(dev, |
1991 | radeon_get_encoder_enum(dev, |
1993 | ATOM_DEVICE_CRT2_SUPPORT, |
1992 | ATOM_DEVICE_CRT2_SUPPORT, |
1994 | 2), |
1993 | 2), |
1995 | ATOM_DEVICE_CRT2_SUPPORT); |
1994 | ATOM_DEVICE_CRT2_SUPPORT); |
1996 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1995 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
1997 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1996 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
1998 | CONNECTOR_OBJECT_ID_VGA, |
1997 | CONNECTOR_OBJECT_ID_VGA, |
1999 | &hpd); |
1998 | &hpd); |
2000 | break; |
1999 | break; |
2001 | case CT_MAC_X800: |
2000 | case CT_MAC_X800: |
2002 | DRM_INFO("Connector Table: %d (mac x800)\n", |
2001 | DRM_INFO("Connector Table: %d (mac x800)\n", |
2003 | rdev->mode_info.connector_table); |
2002 | rdev->mode_info.connector_table); |
2004 | /* DVI - primary dac, internal tmds */ |
2003 | /* DVI - primary dac, internal tmds */ |
2005 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2004 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2006 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2005 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2007 | radeon_add_legacy_encoder(dev, |
2006 | radeon_add_legacy_encoder(dev, |
2008 | radeon_get_encoder_enum(dev, |
2007 | radeon_get_encoder_enum(dev, |
2009 | ATOM_DEVICE_DFP1_SUPPORT, |
2008 | ATOM_DEVICE_DFP1_SUPPORT, |
2010 | 0), |
2009 | 0), |
2011 | ATOM_DEVICE_DFP1_SUPPORT); |
2010 | ATOM_DEVICE_DFP1_SUPPORT); |
2012 | radeon_add_legacy_encoder(dev, |
2011 | radeon_add_legacy_encoder(dev, |
2013 | radeon_get_encoder_enum(dev, |
2012 | radeon_get_encoder_enum(dev, |
2014 | ATOM_DEVICE_CRT1_SUPPORT, |
2013 | ATOM_DEVICE_CRT1_SUPPORT, |
2015 | 1), |
2014 | 1), |
2016 | ATOM_DEVICE_CRT1_SUPPORT); |
2015 | ATOM_DEVICE_CRT1_SUPPORT); |
2017 | radeon_add_legacy_connector(dev, 0, |
2016 | radeon_add_legacy_connector(dev, 0, |
2018 | ATOM_DEVICE_DFP1_SUPPORT | |
2017 | ATOM_DEVICE_DFP1_SUPPORT | |
2019 | ATOM_DEVICE_CRT1_SUPPORT, |
2018 | ATOM_DEVICE_CRT1_SUPPORT, |
2020 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2019 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2021 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2020 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2022 | &hpd); |
2021 | &hpd); |
2023 | /* DVI - tv dac, dvo */ |
2022 | /* DVI - tv dac, dvo */ |
2024 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2023 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2025 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2024 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2026 | radeon_add_legacy_encoder(dev, |
2025 | radeon_add_legacy_encoder(dev, |
2027 | radeon_get_encoder_enum(dev, |
2026 | radeon_get_encoder_enum(dev, |
2028 | ATOM_DEVICE_DFP2_SUPPORT, |
2027 | ATOM_DEVICE_DFP2_SUPPORT, |
2029 | 0), |
2028 | 0), |
2030 | ATOM_DEVICE_DFP2_SUPPORT); |
2029 | ATOM_DEVICE_DFP2_SUPPORT); |
2031 | radeon_add_legacy_encoder(dev, |
2030 | radeon_add_legacy_encoder(dev, |
2032 | radeon_get_encoder_enum(dev, |
2031 | radeon_get_encoder_enum(dev, |
2033 | ATOM_DEVICE_CRT2_SUPPORT, |
2032 | ATOM_DEVICE_CRT2_SUPPORT, |
2034 | 2), |
2033 | 2), |
2035 | ATOM_DEVICE_CRT2_SUPPORT); |
2034 | ATOM_DEVICE_CRT2_SUPPORT); |
2036 | radeon_add_legacy_connector(dev, 1, |
2035 | radeon_add_legacy_connector(dev, 1, |
2037 | ATOM_DEVICE_DFP2_SUPPORT | |
2036 | ATOM_DEVICE_DFP2_SUPPORT | |
2038 | ATOM_DEVICE_CRT2_SUPPORT, |
2037 | ATOM_DEVICE_CRT2_SUPPORT, |
2039 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2038 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2040 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
2039 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
2041 | &hpd); |
2040 | &hpd); |
2042 | break; |
2041 | break; |
2043 | case CT_MAC_G5_9600: |
2042 | case CT_MAC_G5_9600: |
2044 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", |
2043 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", |
2045 | rdev->mode_info.connector_table); |
2044 | rdev->mode_info.connector_table); |
2046 | /* DVI - tv dac, dvo */ |
2045 | /* DVI - tv dac, dvo */ |
2047 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2046 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2048 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2047 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2049 | radeon_add_legacy_encoder(dev, |
2048 | radeon_add_legacy_encoder(dev, |
2050 | radeon_get_encoder_enum(dev, |
2049 | radeon_get_encoder_enum(dev, |
2051 | ATOM_DEVICE_DFP2_SUPPORT, |
2050 | ATOM_DEVICE_DFP2_SUPPORT, |
2052 | 0), |
2051 | 0), |
2053 | ATOM_DEVICE_DFP2_SUPPORT); |
2052 | ATOM_DEVICE_DFP2_SUPPORT); |
2054 | radeon_add_legacy_encoder(dev, |
2053 | radeon_add_legacy_encoder(dev, |
2055 | radeon_get_encoder_enum(dev, |
2054 | radeon_get_encoder_enum(dev, |
2056 | ATOM_DEVICE_CRT2_SUPPORT, |
2055 | ATOM_DEVICE_CRT2_SUPPORT, |
2057 | 2), |
2056 | 2), |
2058 | ATOM_DEVICE_CRT2_SUPPORT); |
2057 | ATOM_DEVICE_CRT2_SUPPORT); |
2059 | radeon_add_legacy_connector(dev, 0, |
2058 | radeon_add_legacy_connector(dev, 0, |
2060 | ATOM_DEVICE_DFP2_SUPPORT | |
2059 | ATOM_DEVICE_DFP2_SUPPORT | |
2061 | ATOM_DEVICE_CRT2_SUPPORT, |
2060 | ATOM_DEVICE_CRT2_SUPPORT, |
2062 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2061 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2063 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2062 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2064 | &hpd); |
2063 | &hpd); |
2065 | /* ADC - primary dac, internal tmds */ |
2064 | /* ADC - primary dac, internal tmds */ |
2066 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2065 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2067 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2066 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2068 | radeon_add_legacy_encoder(dev, |
2067 | radeon_add_legacy_encoder(dev, |
2069 | radeon_get_encoder_enum(dev, |
2068 | radeon_get_encoder_enum(dev, |
2070 | ATOM_DEVICE_DFP1_SUPPORT, |
2069 | ATOM_DEVICE_DFP1_SUPPORT, |
2071 | 0), |
2070 | 0), |
2072 | ATOM_DEVICE_DFP1_SUPPORT); |
2071 | ATOM_DEVICE_DFP1_SUPPORT); |
2073 | radeon_add_legacy_encoder(dev, |
2072 | radeon_add_legacy_encoder(dev, |
2074 | radeon_get_encoder_enum(dev, |
2073 | radeon_get_encoder_enum(dev, |
2075 | ATOM_DEVICE_CRT1_SUPPORT, |
2074 | ATOM_DEVICE_CRT1_SUPPORT, |
2076 | 1), |
2075 | 1), |
2077 | ATOM_DEVICE_CRT1_SUPPORT); |
2076 | ATOM_DEVICE_CRT1_SUPPORT); |
2078 | radeon_add_legacy_connector(dev, 1, |
2077 | radeon_add_legacy_connector(dev, 1, |
2079 | ATOM_DEVICE_DFP1_SUPPORT | |
2078 | ATOM_DEVICE_DFP1_SUPPORT | |
2080 | ATOM_DEVICE_CRT1_SUPPORT, |
2079 | ATOM_DEVICE_CRT1_SUPPORT, |
2081 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2080 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2082 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2081 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2083 | &hpd); |
2082 | &hpd); |
2084 | /* TV - TV DAC */ |
2083 | /* TV - TV DAC */ |
2085 | ddc_i2c.valid = false; |
2084 | ddc_i2c.valid = false; |
2086 | hpd.hpd = RADEON_HPD_NONE; |
2085 | hpd.hpd = RADEON_HPD_NONE; |
2087 | radeon_add_legacy_encoder(dev, |
2086 | radeon_add_legacy_encoder(dev, |
2088 | radeon_get_encoder_enum(dev, |
2087 | radeon_get_encoder_enum(dev, |
2089 | ATOM_DEVICE_TV1_SUPPORT, |
2088 | ATOM_DEVICE_TV1_SUPPORT, |
2090 | 2), |
2089 | 2), |
2091 | ATOM_DEVICE_TV1_SUPPORT); |
2090 | ATOM_DEVICE_TV1_SUPPORT); |
2092 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
2091 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
2093 | DRM_MODE_CONNECTOR_SVIDEO, |
2092 | DRM_MODE_CONNECTOR_SVIDEO, |
2094 | &ddc_i2c, |
2093 | &ddc_i2c, |
2095 | CONNECTOR_OBJECT_ID_SVIDEO, |
2094 | CONNECTOR_OBJECT_ID_SVIDEO, |
2096 | &hpd); |
2095 | &hpd); |
2097 | break; |
2096 | break; |
2098 | case CT_SAM440EP: |
2097 | case CT_SAM440EP: |
2099 | DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", |
2098 | DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", |
2100 | rdev->mode_info.connector_table); |
2099 | rdev->mode_info.connector_table); |
2101 | /* LVDS */ |
2100 | /* LVDS */ |
2102 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
2101 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
2103 | hpd.hpd = RADEON_HPD_NONE; |
2102 | hpd.hpd = RADEON_HPD_NONE; |
2104 | radeon_add_legacy_encoder(dev, |
2103 | radeon_add_legacy_encoder(dev, |
2105 | radeon_get_encoder_enum(dev, |
2104 | radeon_get_encoder_enum(dev, |
2106 | ATOM_DEVICE_LCD1_SUPPORT, |
2105 | ATOM_DEVICE_LCD1_SUPPORT, |
2107 | 0), |
2106 | 0), |
2108 | ATOM_DEVICE_LCD1_SUPPORT); |
2107 | ATOM_DEVICE_LCD1_SUPPORT); |
2109 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
2108 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, |
2110 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
2109 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
2111 | CONNECTOR_OBJECT_ID_LVDS, |
2110 | CONNECTOR_OBJECT_ID_LVDS, |
2112 | &hpd); |
2111 | &hpd); |
2113 | /* DVI-I - secondary dac, int tmds */ |
2112 | /* DVI-I - secondary dac, int tmds */ |
2114 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2113 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2115 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2114 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2116 | radeon_add_legacy_encoder(dev, |
2115 | radeon_add_legacy_encoder(dev, |
2117 | radeon_get_encoder_enum(dev, |
2116 | radeon_get_encoder_enum(dev, |
2118 | ATOM_DEVICE_DFP1_SUPPORT, |
2117 | ATOM_DEVICE_DFP1_SUPPORT, |
2119 | 0), |
2118 | 0), |
2120 | ATOM_DEVICE_DFP1_SUPPORT); |
2119 | ATOM_DEVICE_DFP1_SUPPORT); |
2121 | radeon_add_legacy_encoder(dev, |
2120 | radeon_add_legacy_encoder(dev, |
2122 | radeon_get_encoder_enum(dev, |
2121 | radeon_get_encoder_enum(dev, |
2123 | ATOM_DEVICE_CRT2_SUPPORT, |
2122 | ATOM_DEVICE_CRT2_SUPPORT, |
2124 | 2), |
2123 | 2), |
2125 | ATOM_DEVICE_CRT2_SUPPORT); |
2124 | ATOM_DEVICE_CRT2_SUPPORT); |
2126 | radeon_add_legacy_connector(dev, 1, |
2125 | radeon_add_legacy_connector(dev, 1, |
2127 | ATOM_DEVICE_DFP1_SUPPORT | |
2126 | ATOM_DEVICE_DFP1_SUPPORT | |
2128 | ATOM_DEVICE_CRT2_SUPPORT, |
2127 | ATOM_DEVICE_CRT2_SUPPORT, |
2129 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2128 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2130 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2129 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2131 | &hpd); |
2130 | &hpd); |
2132 | /* VGA - primary dac */ |
2131 | /* VGA - primary dac */ |
2133 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2132 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2134 | hpd.hpd = RADEON_HPD_NONE; |
2133 | hpd.hpd = RADEON_HPD_NONE; |
2135 | radeon_add_legacy_encoder(dev, |
2134 | radeon_add_legacy_encoder(dev, |
2136 | radeon_get_encoder_enum(dev, |
2135 | radeon_get_encoder_enum(dev, |
2137 | ATOM_DEVICE_CRT1_SUPPORT, |
2136 | ATOM_DEVICE_CRT1_SUPPORT, |
2138 | 1), |
2137 | 1), |
2139 | ATOM_DEVICE_CRT1_SUPPORT); |
2138 | ATOM_DEVICE_CRT1_SUPPORT); |
2140 | radeon_add_legacy_connector(dev, 2, |
2139 | radeon_add_legacy_connector(dev, 2, |
2141 | ATOM_DEVICE_CRT1_SUPPORT, |
2140 | ATOM_DEVICE_CRT1_SUPPORT, |
2142 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
2141 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
2143 | CONNECTOR_OBJECT_ID_VGA, |
2142 | CONNECTOR_OBJECT_ID_VGA, |
2144 | &hpd); |
2143 | &hpd); |
2145 | /* TV - TV DAC */ |
2144 | /* TV - TV DAC */ |
2146 | ddc_i2c.valid = false; |
2145 | ddc_i2c.valid = false; |
2147 | hpd.hpd = RADEON_HPD_NONE; |
2146 | hpd.hpd = RADEON_HPD_NONE; |
2148 | radeon_add_legacy_encoder(dev, |
2147 | radeon_add_legacy_encoder(dev, |
2149 | radeon_get_encoder_enum(dev, |
2148 | radeon_get_encoder_enum(dev, |
2150 | ATOM_DEVICE_TV1_SUPPORT, |
2149 | ATOM_DEVICE_TV1_SUPPORT, |
2151 | 2), |
2150 | 2), |
2152 | ATOM_DEVICE_TV1_SUPPORT); |
2151 | ATOM_DEVICE_TV1_SUPPORT); |
2153 | radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, |
2152 | radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, |
2154 | DRM_MODE_CONNECTOR_SVIDEO, |
2153 | DRM_MODE_CONNECTOR_SVIDEO, |
2155 | &ddc_i2c, |
2154 | &ddc_i2c, |
2156 | CONNECTOR_OBJECT_ID_SVIDEO, |
2155 | CONNECTOR_OBJECT_ID_SVIDEO, |
2157 | &hpd); |
2156 | &hpd); |
2158 | break; |
2157 | break; |
2159 | case CT_MAC_G4_SILVER: |
2158 | case CT_MAC_G4_SILVER: |
2160 | DRM_INFO("Connector Table: %d (mac g4 silver)\n", |
2159 | DRM_INFO("Connector Table: %d (mac g4 silver)\n", |
2161 | rdev->mode_info.connector_table); |
2160 | rdev->mode_info.connector_table); |
2162 | /* DVI-I - tv dac, int tmds */ |
2161 | /* DVI-I - tv dac, int tmds */ |
2163 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2162 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2164 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2163 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2165 | radeon_add_legacy_encoder(dev, |
2164 | radeon_add_legacy_encoder(dev, |
2166 | radeon_get_encoder_enum(dev, |
2165 | radeon_get_encoder_enum(dev, |
2167 | ATOM_DEVICE_DFP1_SUPPORT, |
2166 | ATOM_DEVICE_DFP1_SUPPORT, |
2168 | 0), |
2167 | 0), |
2169 | ATOM_DEVICE_DFP1_SUPPORT); |
2168 | ATOM_DEVICE_DFP1_SUPPORT); |
2170 | radeon_add_legacy_encoder(dev, |
2169 | radeon_add_legacy_encoder(dev, |
2171 | radeon_get_encoder_enum(dev, |
2170 | radeon_get_encoder_enum(dev, |
2172 | ATOM_DEVICE_CRT2_SUPPORT, |
2171 | ATOM_DEVICE_CRT2_SUPPORT, |
2173 | 2), |
2172 | 2), |
2174 | ATOM_DEVICE_CRT2_SUPPORT); |
2173 | ATOM_DEVICE_CRT2_SUPPORT); |
2175 | radeon_add_legacy_connector(dev, 0, |
2174 | radeon_add_legacy_connector(dev, 0, |
2176 | ATOM_DEVICE_DFP1_SUPPORT | |
2175 | ATOM_DEVICE_DFP1_SUPPORT | |
2177 | ATOM_DEVICE_CRT2_SUPPORT, |
2176 | ATOM_DEVICE_CRT2_SUPPORT, |
2178 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2177 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
2179 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2178 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2180 | &hpd); |
2179 | &hpd); |
2181 | /* VGA - primary dac */ |
2180 | /* VGA - primary dac */ |
2182 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2181 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2183 | hpd.hpd = RADEON_HPD_NONE; |
2182 | hpd.hpd = RADEON_HPD_NONE; |
2184 | radeon_add_legacy_encoder(dev, |
2183 | radeon_add_legacy_encoder(dev, |
2185 | radeon_get_encoder_enum(dev, |
2184 | radeon_get_encoder_enum(dev, |
2186 | ATOM_DEVICE_CRT1_SUPPORT, |
2185 | ATOM_DEVICE_CRT1_SUPPORT, |
2187 | 1), |
2186 | 1), |
2188 | ATOM_DEVICE_CRT1_SUPPORT); |
2187 | ATOM_DEVICE_CRT1_SUPPORT); |
2189 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
2188 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, |
2190 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
2189 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
2191 | CONNECTOR_OBJECT_ID_VGA, |
2190 | CONNECTOR_OBJECT_ID_VGA, |
2192 | &hpd); |
2191 | &hpd); |
2193 | /* TV - TV DAC */ |
2192 | /* TV - TV DAC */ |
2194 | ddc_i2c.valid = false; |
2193 | ddc_i2c.valid = false; |
2195 | hpd.hpd = RADEON_HPD_NONE; |
2194 | hpd.hpd = RADEON_HPD_NONE; |
2196 | radeon_add_legacy_encoder(dev, |
2195 | radeon_add_legacy_encoder(dev, |
2197 | radeon_get_encoder_enum(dev, |
2196 | radeon_get_encoder_enum(dev, |
2198 | ATOM_DEVICE_TV1_SUPPORT, |
2197 | ATOM_DEVICE_TV1_SUPPORT, |
2199 | 2), |
2198 | 2), |
2200 | ATOM_DEVICE_TV1_SUPPORT); |
2199 | ATOM_DEVICE_TV1_SUPPORT); |
2201 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
2200 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
2202 | DRM_MODE_CONNECTOR_SVIDEO, |
2201 | DRM_MODE_CONNECTOR_SVIDEO, |
2203 | &ddc_i2c, |
2202 | &ddc_i2c, |
2204 | CONNECTOR_OBJECT_ID_SVIDEO, |
2203 | CONNECTOR_OBJECT_ID_SVIDEO, |
2205 | &hpd); |
2204 | &hpd); |
2206 | break; |
2205 | break; |
2207 | default: |
2206 | default: |
2208 | DRM_INFO("Connector table: %d (invalid)\n", |
2207 | DRM_INFO("Connector table: %d (invalid)\n", |
2209 | rdev->mode_info.connector_table); |
2208 | rdev->mode_info.connector_table); |
2210 | return false; |
2209 | return false; |
2211 | } |
2210 | } |
2212 | 2211 | ||
2213 | radeon_link_encoder_connector(dev); |
2212 | radeon_link_encoder_connector(dev); |
2214 | 2213 | ||
2215 | return true; |
2214 | return true; |
2216 | } |
2215 | } |
2217 | 2216 | ||
2218 | static bool radeon_apply_legacy_quirks(struct drm_device *dev, |
2217 | static bool radeon_apply_legacy_quirks(struct drm_device *dev, |
2219 | int bios_index, |
2218 | int bios_index, |
2220 | enum radeon_combios_connector |
2219 | enum radeon_combios_connector |
2221 | *legacy_connector, |
2220 | *legacy_connector, |
2222 | struct radeon_i2c_bus_rec *ddc_i2c, |
2221 | struct radeon_i2c_bus_rec *ddc_i2c, |
2223 | struct radeon_hpd *hpd) |
2222 | struct radeon_hpd *hpd) |
2224 | { |
2223 | { |
2225 | 2224 | ||
2226 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
2225 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
2227 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
2226 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
2228 | if (dev->pdev->device == 0x515e && |
2227 | if (dev->pdev->device == 0x515e && |
2229 | dev->pdev->subsystem_vendor == 0x1014) { |
2228 | dev->pdev->subsystem_vendor == 0x1014) { |
2230 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
2229 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
2231 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
2230 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
2232 | return false; |
2231 | return false; |
2233 | } |
2232 | } |
2234 | 2233 | ||
2235 | /* X300 card with extra non-existent DVI port */ |
2234 | /* X300 card with extra non-existent DVI port */ |
2236 | if (dev->pdev->device == 0x5B60 && |
2235 | if (dev->pdev->device == 0x5B60 && |
2237 | dev->pdev->subsystem_vendor == 0x17af && |
2236 | dev->pdev->subsystem_vendor == 0x17af && |
2238 | dev->pdev->subsystem_device == 0x201e && bios_index == 2) { |
2237 | dev->pdev->subsystem_device == 0x201e && bios_index == 2) { |
2239 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
2238 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
2240 | return false; |
2239 | return false; |
2241 | } |
2240 | } |
2242 | 2241 | ||
2243 | return true; |
2242 | return true; |
2244 | } |
2243 | } |
2245 | 2244 | ||
2246 | static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) |
2245 | static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) |
2247 | { |
2246 | { |
2248 | /* Acer 5102 has non-existent TV port */ |
2247 | /* Acer 5102 has non-existent TV port */ |
2249 | if (dev->pdev->device == 0x5975 && |
2248 | if (dev->pdev->device == 0x5975 && |
2250 | dev->pdev->subsystem_vendor == 0x1025 && |
2249 | dev->pdev->subsystem_vendor == 0x1025 && |
2251 | dev->pdev->subsystem_device == 0x009f) |
2250 | dev->pdev->subsystem_device == 0x009f) |
2252 | return false; |
2251 | return false; |
2253 | 2252 | ||
2254 | /* HP dc5750 has non-existent TV port */ |
2253 | /* HP dc5750 has non-existent TV port */ |
2255 | if (dev->pdev->device == 0x5974 && |
2254 | if (dev->pdev->device == 0x5974 && |
2256 | dev->pdev->subsystem_vendor == 0x103c && |
2255 | dev->pdev->subsystem_vendor == 0x103c && |
2257 | dev->pdev->subsystem_device == 0x280a) |
2256 | dev->pdev->subsystem_device == 0x280a) |
2258 | return false; |
2257 | return false; |
2259 | 2258 | ||
2260 | /* MSI S270 has non-existent TV port */ |
2259 | /* MSI S270 has non-existent TV port */ |
2261 | if (dev->pdev->device == 0x5955 && |
2260 | if (dev->pdev->device == 0x5955 && |
2262 | dev->pdev->subsystem_vendor == 0x1462 && |
2261 | dev->pdev->subsystem_vendor == 0x1462 && |
2263 | dev->pdev->subsystem_device == 0x0131) |
2262 | dev->pdev->subsystem_device == 0x0131) |
2264 | return false; |
2263 | return false; |
2265 | 2264 | ||
2266 | return true; |
2265 | return true; |
2267 | } |
2266 | } |
2268 | 2267 | ||
2269 | static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) |
2268 | static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) |
2270 | { |
2269 | { |
2271 | struct radeon_device *rdev = dev->dev_private; |
2270 | struct radeon_device *rdev = dev->dev_private; |
2272 | uint32_t ext_tmds_info; |
2271 | uint32_t ext_tmds_info; |
2273 | 2272 | ||
2274 | if (rdev->flags & RADEON_IS_IGP) { |
2273 | if (rdev->flags & RADEON_IS_IGP) { |
2275 | if (is_dvi_d) |
2274 | if (is_dvi_d) |
2276 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
2275 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
2277 | else |
2276 | else |
2278 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2277 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2279 | } |
2278 | } |
2280 | ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2279 | ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2281 | if (ext_tmds_info) { |
2280 | if (ext_tmds_info) { |
2282 | uint8_t rev = RBIOS8(ext_tmds_info); |
2281 | uint8_t rev = RBIOS8(ext_tmds_info); |
2283 | uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); |
2282 | uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); |
2284 | if (rev >= 3) { |
2283 | if (rev >= 3) { |
2285 | if (is_dvi_d) |
2284 | if (is_dvi_d) |
2286 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
2285 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
2287 | else |
2286 | else |
2288 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
2287 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
2289 | } else { |
2288 | } else { |
2290 | if (flags & 1) { |
2289 | if (flags & 1) { |
2291 | if (is_dvi_d) |
2290 | if (is_dvi_d) |
2292 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
2291 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
2293 | else |
2292 | else |
2294 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
2293 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
2295 | } |
2294 | } |
2296 | } |
2295 | } |
2297 | } |
2296 | } |
2298 | if (is_dvi_d) |
2297 | if (is_dvi_d) |
2299 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
2298 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
2300 | else |
2299 | else |
2301 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2300 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2302 | } |
2301 | } |
2303 | 2302 | ||
2304 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) |
2303 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) |
2305 | { |
2304 | { |
2306 | struct radeon_device *rdev = dev->dev_private; |
2305 | struct radeon_device *rdev = dev->dev_private; |
2307 | uint32_t conn_info, entry, devices; |
2306 | uint32_t conn_info, entry, devices; |
2308 | uint16_t tmp, connector_object_id; |
2307 | uint16_t tmp, connector_object_id; |
2309 | enum radeon_combios_ddc ddc_type; |
2308 | enum radeon_combios_ddc ddc_type; |
2310 | enum radeon_combios_connector connector; |
2309 | enum radeon_combios_connector connector; |
2311 | int i = 0; |
2310 | int i = 0; |
2312 | struct radeon_i2c_bus_rec ddc_i2c; |
2311 | struct radeon_i2c_bus_rec ddc_i2c; |
2313 | struct radeon_hpd hpd; |
2312 | struct radeon_hpd hpd; |
2314 | 2313 | ||
2315 | conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); |
2314 | conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); |
2316 | if (conn_info) { |
2315 | if (conn_info) { |
2317 | for (i = 0; i < 4; i++) { |
2316 | for (i = 0; i < 4; i++) { |
2318 | entry = conn_info + 2 + i * 2; |
2317 | entry = conn_info + 2 + i * 2; |
2319 | 2318 | ||
2320 | if (!RBIOS16(entry)) |
2319 | if (!RBIOS16(entry)) |
2321 | break; |
2320 | break; |
2322 | 2321 | ||
2323 | tmp = RBIOS16(entry); |
2322 | tmp = RBIOS16(entry); |
2324 | 2323 | ||
2325 | connector = (tmp >> 12) & 0xf; |
2324 | connector = (tmp >> 12) & 0xf; |
2326 | 2325 | ||
2327 | ddc_type = (tmp >> 8) & 0xf; |
2326 | ddc_type = (tmp >> 8) & 0xf; |
2328 | if (ddc_type == 5) |
2327 | if (ddc_type == 5) |
2329 | ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); |
2328 | ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); |
2330 | else |
2329 | else |
2331 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2330 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2332 | 2331 | ||
2333 | switch (connector) { |
2332 | switch (connector) { |
2334 | case CONNECTOR_PROPRIETARY_LEGACY: |
2333 | case CONNECTOR_PROPRIETARY_LEGACY: |
2335 | case CONNECTOR_DVI_I_LEGACY: |
2334 | case CONNECTOR_DVI_I_LEGACY: |
2336 | case CONNECTOR_DVI_D_LEGACY: |
2335 | case CONNECTOR_DVI_D_LEGACY: |
2337 | if ((tmp >> 4) & 0x1) |
2336 | if ((tmp >> 4) & 0x1) |
2338 | hpd.hpd = RADEON_HPD_2; |
2337 | hpd.hpd = RADEON_HPD_2; |
2339 | else |
2338 | else |
2340 | hpd.hpd = RADEON_HPD_1; |
2339 | hpd.hpd = RADEON_HPD_1; |
2341 | break; |
2340 | break; |
2342 | default: |
2341 | default: |
2343 | hpd.hpd = RADEON_HPD_NONE; |
2342 | hpd.hpd = RADEON_HPD_NONE; |
2344 | break; |
2343 | break; |
2345 | } |
2344 | } |
2346 | 2345 | ||
2347 | if (!radeon_apply_legacy_quirks(dev, i, &connector, |
2346 | if (!radeon_apply_legacy_quirks(dev, i, &connector, |
2348 | &ddc_i2c, &hpd)) |
2347 | &ddc_i2c, &hpd)) |
2349 | continue; |
2348 | continue; |
2350 | 2349 | ||
2351 | switch (connector) { |
2350 | switch (connector) { |
2352 | case CONNECTOR_PROPRIETARY_LEGACY: |
2351 | case CONNECTOR_PROPRIETARY_LEGACY: |
2353 | if ((tmp >> 4) & 0x1) |
2352 | if ((tmp >> 4) & 0x1) |
2354 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2353 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2355 | else |
2354 | else |
2356 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2355 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2357 | radeon_add_legacy_encoder(dev, |
2356 | radeon_add_legacy_encoder(dev, |
2358 | radeon_get_encoder_enum |
2357 | radeon_get_encoder_enum |
2359 | (dev, devices, 0), |
2358 | (dev, devices, 0), |
2360 | devices); |
2359 | devices); |
2361 | radeon_add_legacy_connector(dev, i, devices, |
2360 | radeon_add_legacy_connector(dev, i, devices, |
2362 | legacy_connector_convert |
2361 | legacy_connector_convert |
2363 | [connector], |
2362 | [connector], |
2364 | &ddc_i2c, |
2363 | &ddc_i2c, |
2365 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
2364 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
2366 | &hpd); |
2365 | &hpd); |
2367 | break; |
2366 | break; |
2368 | case CONNECTOR_CRT_LEGACY: |
2367 | case CONNECTOR_CRT_LEGACY: |
2369 | if (tmp & 0x1) { |
2368 | if (tmp & 0x1) { |
2370 | devices = ATOM_DEVICE_CRT2_SUPPORT; |
2369 | devices = ATOM_DEVICE_CRT2_SUPPORT; |
2371 | radeon_add_legacy_encoder(dev, |
2370 | radeon_add_legacy_encoder(dev, |
2372 | radeon_get_encoder_enum |
2371 | radeon_get_encoder_enum |
2373 | (dev, |
2372 | (dev, |
2374 | ATOM_DEVICE_CRT2_SUPPORT, |
2373 | ATOM_DEVICE_CRT2_SUPPORT, |
2375 | 2), |
2374 | 2), |
2376 | ATOM_DEVICE_CRT2_SUPPORT); |
2375 | ATOM_DEVICE_CRT2_SUPPORT); |
2377 | } else { |
2376 | } else { |
2378 | devices = ATOM_DEVICE_CRT1_SUPPORT; |
2377 | devices = ATOM_DEVICE_CRT1_SUPPORT; |
2379 | radeon_add_legacy_encoder(dev, |
2378 | radeon_add_legacy_encoder(dev, |
2380 | radeon_get_encoder_enum |
2379 | radeon_get_encoder_enum |
2381 | (dev, |
2380 | (dev, |
2382 | ATOM_DEVICE_CRT1_SUPPORT, |
2381 | ATOM_DEVICE_CRT1_SUPPORT, |
2383 | 1), |
2382 | 1), |
2384 | ATOM_DEVICE_CRT1_SUPPORT); |
2383 | ATOM_DEVICE_CRT1_SUPPORT); |
2385 | } |
2384 | } |
2386 | radeon_add_legacy_connector(dev, |
2385 | radeon_add_legacy_connector(dev, |
2387 | i, |
2386 | i, |
2388 | devices, |
2387 | devices, |
2389 | legacy_connector_convert |
2388 | legacy_connector_convert |
2390 | [connector], |
2389 | [connector], |
2391 | &ddc_i2c, |
2390 | &ddc_i2c, |
2392 | CONNECTOR_OBJECT_ID_VGA, |
2391 | CONNECTOR_OBJECT_ID_VGA, |
2393 | &hpd); |
2392 | &hpd); |
2394 | break; |
2393 | break; |
2395 | case CONNECTOR_DVI_I_LEGACY: |
2394 | case CONNECTOR_DVI_I_LEGACY: |
2396 | devices = 0; |
2395 | devices = 0; |
2397 | if (tmp & 0x1) { |
2396 | if (tmp & 0x1) { |
2398 | devices |= ATOM_DEVICE_CRT2_SUPPORT; |
2397 | devices |= ATOM_DEVICE_CRT2_SUPPORT; |
2399 | radeon_add_legacy_encoder(dev, |
2398 | radeon_add_legacy_encoder(dev, |
2400 | radeon_get_encoder_enum |
2399 | radeon_get_encoder_enum |
2401 | (dev, |
2400 | (dev, |
2402 | ATOM_DEVICE_CRT2_SUPPORT, |
2401 | ATOM_DEVICE_CRT2_SUPPORT, |
2403 | 2), |
2402 | 2), |
2404 | ATOM_DEVICE_CRT2_SUPPORT); |
2403 | ATOM_DEVICE_CRT2_SUPPORT); |
2405 | } else { |
2404 | } else { |
2406 | devices |= ATOM_DEVICE_CRT1_SUPPORT; |
2405 | devices |= ATOM_DEVICE_CRT1_SUPPORT; |
2407 | radeon_add_legacy_encoder(dev, |
2406 | radeon_add_legacy_encoder(dev, |
2408 | radeon_get_encoder_enum |
2407 | radeon_get_encoder_enum |
2409 | (dev, |
2408 | (dev, |
2410 | ATOM_DEVICE_CRT1_SUPPORT, |
2409 | ATOM_DEVICE_CRT1_SUPPORT, |
2411 | 1), |
2410 | 1), |
2412 | ATOM_DEVICE_CRT1_SUPPORT); |
2411 | ATOM_DEVICE_CRT1_SUPPORT); |
2413 | } |
2412 | } |
2414 | /* RV100 board with external TDMS bit mis-set. |
2413 | /* RV100 board with external TDMS bit mis-set. |
2415 | * Actually uses internal TMDS, clear the bit. |
2414 | * Actually uses internal TMDS, clear the bit. |
2416 | */ |
2415 | */ |
2417 | if (dev->pdev->device == 0x5159 && |
2416 | if (dev->pdev->device == 0x5159 && |
2418 | dev->pdev->subsystem_vendor == 0x1014 && |
2417 | dev->pdev->subsystem_vendor == 0x1014 && |
2419 | dev->pdev->subsystem_device == 0x029A) { |
2418 | dev->pdev->subsystem_device == 0x029A) { |
2420 | tmp &= ~(1 << 4); |
2419 | tmp &= ~(1 << 4); |
2421 | } |
2420 | } |
2422 | if ((tmp >> 4) & 0x1) { |
2421 | if ((tmp >> 4) & 0x1) { |
2423 | devices |= ATOM_DEVICE_DFP2_SUPPORT; |
2422 | devices |= ATOM_DEVICE_DFP2_SUPPORT; |
2424 | radeon_add_legacy_encoder(dev, |
2423 | radeon_add_legacy_encoder(dev, |
2425 | radeon_get_encoder_enum |
2424 | radeon_get_encoder_enum |
2426 | (dev, |
2425 | (dev, |
2427 | ATOM_DEVICE_DFP2_SUPPORT, |
2426 | ATOM_DEVICE_DFP2_SUPPORT, |
2428 | 0), |
2427 | 0), |
2429 | ATOM_DEVICE_DFP2_SUPPORT); |
2428 | ATOM_DEVICE_DFP2_SUPPORT); |
2430 | connector_object_id = combios_check_dl_dvi(dev, 0); |
2429 | connector_object_id = combios_check_dl_dvi(dev, 0); |
2431 | } else { |
2430 | } else { |
2432 | devices |= ATOM_DEVICE_DFP1_SUPPORT; |
2431 | devices |= ATOM_DEVICE_DFP1_SUPPORT; |
2433 | radeon_add_legacy_encoder(dev, |
2432 | radeon_add_legacy_encoder(dev, |
2434 | radeon_get_encoder_enum |
2433 | radeon_get_encoder_enum |
2435 | (dev, |
2434 | (dev, |
2436 | ATOM_DEVICE_DFP1_SUPPORT, |
2435 | ATOM_DEVICE_DFP1_SUPPORT, |
2437 | 0), |
2436 | 0), |
2438 | ATOM_DEVICE_DFP1_SUPPORT); |
2437 | ATOM_DEVICE_DFP1_SUPPORT); |
2439 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2438 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2440 | } |
2439 | } |
2441 | radeon_add_legacy_connector(dev, |
2440 | radeon_add_legacy_connector(dev, |
2442 | i, |
2441 | i, |
2443 | devices, |
2442 | devices, |
2444 | legacy_connector_convert |
2443 | legacy_connector_convert |
2445 | [connector], |
2444 | [connector], |
2446 | &ddc_i2c, |
2445 | &ddc_i2c, |
2447 | connector_object_id, |
2446 | connector_object_id, |
2448 | &hpd); |
2447 | &hpd); |
2449 | break; |
2448 | break; |
2450 | case CONNECTOR_DVI_D_LEGACY: |
2449 | case CONNECTOR_DVI_D_LEGACY: |
2451 | if ((tmp >> 4) & 0x1) { |
2450 | if ((tmp >> 4) & 0x1) { |
2452 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2451 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
2453 | connector_object_id = combios_check_dl_dvi(dev, 1); |
2452 | connector_object_id = combios_check_dl_dvi(dev, 1); |
2454 | } else { |
2453 | } else { |
2455 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2454 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
2456 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2455 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2457 | } |
2456 | } |
2458 | radeon_add_legacy_encoder(dev, |
2457 | radeon_add_legacy_encoder(dev, |
2459 | radeon_get_encoder_enum |
2458 | radeon_get_encoder_enum |
2460 | (dev, devices, 0), |
2459 | (dev, devices, 0), |
2461 | devices); |
2460 | devices); |
2462 | radeon_add_legacy_connector(dev, i, devices, |
2461 | radeon_add_legacy_connector(dev, i, devices, |
2463 | legacy_connector_convert |
2462 | legacy_connector_convert |
2464 | [connector], |
2463 | [connector], |
2465 | &ddc_i2c, |
2464 | &ddc_i2c, |
2466 | connector_object_id, |
2465 | connector_object_id, |
2467 | &hpd); |
2466 | &hpd); |
2468 | break; |
2467 | break; |
2469 | case CONNECTOR_CTV_LEGACY: |
2468 | case CONNECTOR_CTV_LEGACY: |
2470 | case CONNECTOR_STV_LEGACY: |
2469 | case CONNECTOR_STV_LEGACY: |
2471 | radeon_add_legacy_encoder(dev, |
2470 | radeon_add_legacy_encoder(dev, |
2472 | radeon_get_encoder_enum |
2471 | radeon_get_encoder_enum |
2473 | (dev, |
2472 | (dev, |
2474 | ATOM_DEVICE_TV1_SUPPORT, |
2473 | ATOM_DEVICE_TV1_SUPPORT, |
2475 | 2), |
2474 | 2), |
2476 | ATOM_DEVICE_TV1_SUPPORT); |
2475 | ATOM_DEVICE_TV1_SUPPORT); |
2477 | radeon_add_legacy_connector(dev, i, |
2476 | radeon_add_legacy_connector(dev, i, |
2478 | ATOM_DEVICE_TV1_SUPPORT, |
2477 | ATOM_DEVICE_TV1_SUPPORT, |
2479 | legacy_connector_convert |
2478 | legacy_connector_convert |
2480 | [connector], |
2479 | [connector], |
2481 | &ddc_i2c, |
2480 | &ddc_i2c, |
2482 | CONNECTOR_OBJECT_ID_SVIDEO, |
2481 | CONNECTOR_OBJECT_ID_SVIDEO, |
2483 | &hpd); |
2482 | &hpd); |
2484 | break; |
2483 | break; |
2485 | default: |
2484 | default: |
2486 | DRM_ERROR("Unknown connector type: %d\n", |
2485 | DRM_ERROR("Unknown connector type: %d\n", |
2487 | connector); |
2486 | connector); |
2488 | continue; |
2487 | continue; |
2489 | } |
2488 | } |
2490 | 2489 | ||
2491 | } |
2490 | } |
2492 | } else { |
2491 | } else { |
2493 | uint16_t tmds_info = |
2492 | uint16_t tmds_info = |
2494 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2493 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2495 | if (tmds_info) { |
2494 | if (tmds_info) { |
2496 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
2495 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
2497 | 2496 | ||
2498 | radeon_add_legacy_encoder(dev, |
2497 | radeon_add_legacy_encoder(dev, |
2499 | radeon_get_encoder_enum(dev, |
2498 | radeon_get_encoder_enum(dev, |
2500 | ATOM_DEVICE_CRT1_SUPPORT, |
2499 | ATOM_DEVICE_CRT1_SUPPORT, |
2501 | 1), |
2500 | 1), |
2502 | ATOM_DEVICE_CRT1_SUPPORT); |
2501 | ATOM_DEVICE_CRT1_SUPPORT); |
2503 | radeon_add_legacy_encoder(dev, |
2502 | radeon_add_legacy_encoder(dev, |
2504 | radeon_get_encoder_enum(dev, |
2503 | radeon_get_encoder_enum(dev, |
2505 | ATOM_DEVICE_DFP1_SUPPORT, |
2504 | ATOM_DEVICE_DFP1_SUPPORT, |
2506 | 0), |
2505 | 0), |
2507 | ATOM_DEVICE_DFP1_SUPPORT); |
2506 | ATOM_DEVICE_DFP1_SUPPORT); |
2508 | 2507 | ||
2509 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2508 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2510 | hpd.hpd = RADEON_HPD_1; |
2509 | hpd.hpd = RADEON_HPD_1; |
2511 | radeon_add_legacy_connector(dev, |
2510 | radeon_add_legacy_connector(dev, |
2512 | 0, |
2511 | 0, |
2513 | ATOM_DEVICE_CRT1_SUPPORT | |
2512 | ATOM_DEVICE_CRT1_SUPPORT | |
2514 | ATOM_DEVICE_DFP1_SUPPORT, |
2513 | ATOM_DEVICE_DFP1_SUPPORT, |
2515 | DRM_MODE_CONNECTOR_DVII, |
2514 | DRM_MODE_CONNECTOR_DVII, |
2516 | &ddc_i2c, |
2515 | &ddc_i2c, |
2517 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2516 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2518 | &hpd); |
2517 | &hpd); |
2519 | } else { |
2518 | } else { |
2520 | uint16_t crt_info = |
2519 | uint16_t crt_info = |
2521 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2520 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2522 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
2521 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
2523 | if (crt_info) { |
2522 | if (crt_info) { |
2524 | radeon_add_legacy_encoder(dev, |
2523 | radeon_add_legacy_encoder(dev, |
2525 | radeon_get_encoder_enum(dev, |
2524 | radeon_get_encoder_enum(dev, |
2526 | ATOM_DEVICE_CRT1_SUPPORT, |
2525 | ATOM_DEVICE_CRT1_SUPPORT, |
2527 | 1), |
2526 | 1), |
2528 | ATOM_DEVICE_CRT1_SUPPORT); |
2527 | ATOM_DEVICE_CRT1_SUPPORT); |
2529 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2528 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2530 | hpd.hpd = RADEON_HPD_NONE; |
2529 | hpd.hpd = RADEON_HPD_NONE; |
2531 | radeon_add_legacy_connector(dev, |
2530 | radeon_add_legacy_connector(dev, |
2532 | 0, |
2531 | 0, |
2533 | ATOM_DEVICE_CRT1_SUPPORT, |
2532 | ATOM_DEVICE_CRT1_SUPPORT, |
2534 | DRM_MODE_CONNECTOR_VGA, |
2533 | DRM_MODE_CONNECTOR_VGA, |
2535 | &ddc_i2c, |
2534 | &ddc_i2c, |
2536 | CONNECTOR_OBJECT_ID_VGA, |
2535 | CONNECTOR_OBJECT_ID_VGA, |
2537 | &hpd); |
2536 | &hpd); |
2538 | } else { |
2537 | } else { |
2539 | DRM_DEBUG_KMS("No connector info found\n"); |
2538 | DRM_DEBUG_KMS("No connector info found\n"); |
2540 | return false; |
2539 | return false; |
2541 | } |
2540 | } |
2542 | } |
2541 | } |
2543 | } |
2542 | } |
2544 | 2543 | ||
2545 | if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { |
2544 | if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { |
2546 | uint16_t lcd_info = |
2545 | uint16_t lcd_info = |
2547 | combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
2546 | combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
2548 | if (lcd_info) { |
2547 | if (lcd_info) { |
2549 | uint16_t lcd_ddc_info = |
2548 | uint16_t lcd_ddc_info = |
2550 | combios_get_table_offset(dev, |
2549 | combios_get_table_offset(dev, |
2551 | COMBIOS_LCD_DDC_INFO_TABLE); |
2550 | COMBIOS_LCD_DDC_INFO_TABLE); |
2552 | 2551 | ||
2553 | radeon_add_legacy_encoder(dev, |
2552 | radeon_add_legacy_encoder(dev, |
2554 | radeon_get_encoder_enum(dev, |
2553 | radeon_get_encoder_enum(dev, |
2555 | ATOM_DEVICE_LCD1_SUPPORT, |
2554 | ATOM_DEVICE_LCD1_SUPPORT, |
2556 | 0), |
2555 | 0), |
2557 | ATOM_DEVICE_LCD1_SUPPORT); |
2556 | ATOM_DEVICE_LCD1_SUPPORT); |
2558 | 2557 | ||
2559 | if (lcd_ddc_info) { |
2558 | if (lcd_ddc_info) { |
2560 | ddc_type = RBIOS8(lcd_ddc_info + 2); |
2559 | ddc_type = RBIOS8(lcd_ddc_info + 2); |
2561 | switch (ddc_type) { |
2560 | switch (ddc_type) { |
2562 | case DDC_LCD: |
2561 | case DDC_LCD: |
2563 | ddc_i2c = |
2562 | ddc_i2c = |
2564 | combios_setup_i2c_bus(rdev, |
2563 | combios_setup_i2c_bus(rdev, |
2565 | DDC_LCD, |
2564 | DDC_LCD, |
2566 | RBIOS32(lcd_ddc_info + 3), |
2565 | RBIOS32(lcd_ddc_info + 3), |
2567 | RBIOS32(lcd_ddc_info + 7)); |
2566 | RBIOS32(lcd_ddc_info + 7)); |
2568 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2567 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2569 | break; |
2568 | break; |
2570 | case DDC_GPIO: |
2569 | case DDC_GPIO: |
2571 | ddc_i2c = |
2570 | ddc_i2c = |
2572 | combios_setup_i2c_bus(rdev, |
2571 | combios_setup_i2c_bus(rdev, |
2573 | DDC_GPIO, |
2572 | DDC_GPIO, |
2574 | RBIOS32(lcd_ddc_info + 3), |
2573 | RBIOS32(lcd_ddc_info + 3), |
2575 | RBIOS32(lcd_ddc_info + 7)); |
2574 | RBIOS32(lcd_ddc_info + 7)); |
2576 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2575 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2577 | break; |
2576 | break; |
2578 | default: |
2577 | default: |
2579 | ddc_i2c = |
2578 | ddc_i2c = |
2580 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2579 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2581 | break; |
2580 | break; |
2582 | } |
2581 | } |
2583 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
2582 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
2584 | } else |
2583 | } else |
2585 | ddc_i2c.valid = false; |
2584 | ddc_i2c.valid = false; |
2586 | 2585 | ||
2587 | hpd.hpd = RADEON_HPD_NONE; |
2586 | hpd.hpd = RADEON_HPD_NONE; |
2588 | radeon_add_legacy_connector(dev, |
2587 | radeon_add_legacy_connector(dev, |
2589 | 5, |
2588 | 5, |
2590 | ATOM_DEVICE_LCD1_SUPPORT, |
2589 | ATOM_DEVICE_LCD1_SUPPORT, |
2591 | DRM_MODE_CONNECTOR_LVDS, |
2590 | DRM_MODE_CONNECTOR_LVDS, |
2592 | &ddc_i2c, |
2591 | &ddc_i2c, |
2593 | CONNECTOR_OBJECT_ID_LVDS, |
2592 | CONNECTOR_OBJECT_ID_LVDS, |
2594 | &hpd); |
2593 | &hpd); |
2595 | } |
2594 | } |
2596 | } |
2595 | } |
2597 | 2596 | ||
2598 | /* check TV table */ |
2597 | /* check TV table */ |
2599 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
2598 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
2600 | uint32_t tv_info = |
2599 | uint32_t tv_info = |
2601 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
2600 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
2602 | if (tv_info) { |
2601 | if (tv_info) { |
2603 | if (RBIOS8(tv_info + 6) == 'T') { |
2602 | if (RBIOS8(tv_info + 6) == 'T') { |
2604 | if (radeon_apply_legacy_tv_quirks(dev)) { |
2603 | if (radeon_apply_legacy_tv_quirks(dev)) { |
2605 | hpd.hpd = RADEON_HPD_NONE; |
2604 | hpd.hpd = RADEON_HPD_NONE; |
2606 | ddc_i2c.valid = false; |
2605 | ddc_i2c.valid = false; |
2607 | radeon_add_legacy_encoder(dev, |
2606 | radeon_add_legacy_encoder(dev, |
2608 | radeon_get_encoder_enum |
2607 | radeon_get_encoder_enum |
2609 | (dev, |
2608 | (dev, |
2610 | ATOM_DEVICE_TV1_SUPPORT, |
2609 | ATOM_DEVICE_TV1_SUPPORT, |
2611 | 2), |
2610 | 2), |
2612 | ATOM_DEVICE_TV1_SUPPORT); |
2611 | ATOM_DEVICE_TV1_SUPPORT); |
2613 | radeon_add_legacy_connector(dev, 6, |
2612 | radeon_add_legacy_connector(dev, 6, |
2614 | ATOM_DEVICE_TV1_SUPPORT, |
2613 | ATOM_DEVICE_TV1_SUPPORT, |
2615 | DRM_MODE_CONNECTOR_SVIDEO, |
2614 | DRM_MODE_CONNECTOR_SVIDEO, |
2616 | &ddc_i2c, |
2615 | &ddc_i2c, |
2617 | CONNECTOR_OBJECT_ID_SVIDEO, |
2616 | CONNECTOR_OBJECT_ID_SVIDEO, |
2618 | &hpd); |
2617 | &hpd); |
2619 | } |
2618 | } |
2620 | } |
2619 | } |
2621 | } |
2620 | } |
2622 | } |
2621 | } |
2623 | 2622 | ||
2624 | radeon_link_encoder_connector(dev); |
2623 | radeon_link_encoder_connector(dev); |
2625 | 2624 | ||
2626 | return true; |
2625 | return true; |
2627 | } |
2626 | } |
2628 | 2627 | ||
2629 | static const char *thermal_controller_names[] = { |
2628 | static const char *thermal_controller_names[] = { |
2630 | "NONE", |
2629 | "NONE", |
2631 | "lm63", |
2630 | "lm63", |
2632 | "adm1032", |
2631 | "adm1032", |
2633 | }; |
2632 | }; |
2634 | 2633 | ||
2635 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2634 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2636 | { |
2635 | { |
2637 | struct drm_device *dev = rdev->ddev; |
2636 | struct drm_device *dev = rdev->ddev; |
2638 | u16 offset, misc, misc2 = 0; |
2637 | u16 offset, misc, misc2 = 0; |
2639 | u8 rev, blocks, tmp; |
2638 | u8 rev, blocks, tmp; |
2640 | int state_index = 0; |
2639 | int state_index = 0; |
2641 | struct radeon_i2c_bus_rec i2c_bus; |
2640 | struct radeon_i2c_bus_rec i2c_bus; |
2642 | 2641 | ||
2643 | rdev->pm.default_power_state_index = -1; |
2642 | rdev->pm.default_power_state_index = -1; |
2644 | 2643 | ||
2645 | /* allocate 2 power states */ |
2644 | /* allocate 2 power states */ |
2646 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); |
2645 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); |
2647 | if (rdev->pm.power_state) { |
2646 | if (rdev->pm.power_state) { |
2648 | /* allocate 1 clock mode per state */ |
2647 | /* allocate 1 clock mode per state */ |
2649 | rdev->pm.power_state[0].clock_info = |
2648 | rdev->pm.power_state[0].clock_info = |
2650 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
2649 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
2651 | rdev->pm.power_state[1].clock_info = |
2650 | rdev->pm.power_state[1].clock_info = |
2652 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
2651 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
2653 | if (!rdev->pm.power_state[0].clock_info || |
2652 | if (!rdev->pm.power_state[0].clock_info || |
2654 | !rdev->pm.power_state[1].clock_info) |
2653 | !rdev->pm.power_state[1].clock_info) |
2655 | goto pm_failed; |
2654 | goto pm_failed; |
2656 | } else |
2655 | } else |
2657 | goto pm_failed; |
2656 | goto pm_failed; |
2658 | 2657 | ||
2659 | /* check for a thermal chip */ |
2658 | /* check for a thermal chip */ |
2660 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
2659 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
2661 | if (offset) { |
2660 | if (offset) { |
2662 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
2661 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
2663 | 2662 | ||
2664 | rev = RBIOS8(offset); |
2663 | rev = RBIOS8(offset); |
2665 | 2664 | ||
2666 | if (rev == 0) { |
2665 | if (rev == 0) { |
2667 | thermal_controller = RBIOS8(offset + 3); |
2666 | thermal_controller = RBIOS8(offset + 3); |
2668 | gpio = RBIOS8(offset + 4) & 0x3f; |
2667 | gpio = RBIOS8(offset + 4) & 0x3f; |
2669 | i2c_addr = RBIOS8(offset + 5); |
2668 | i2c_addr = RBIOS8(offset + 5); |
2670 | } else if (rev == 1) { |
2669 | } else if (rev == 1) { |
2671 | thermal_controller = RBIOS8(offset + 4); |
2670 | thermal_controller = RBIOS8(offset + 4); |
2672 | gpio = RBIOS8(offset + 5) & 0x3f; |
2671 | gpio = RBIOS8(offset + 5) & 0x3f; |
2673 | i2c_addr = RBIOS8(offset + 6); |
2672 | i2c_addr = RBIOS8(offset + 6); |
2674 | } else if (rev == 2) { |
2673 | } else if (rev == 2) { |
2675 | thermal_controller = RBIOS8(offset + 4); |
2674 | thermal_controller = RBIOS8(offset + 4); |
2676 | gpio = RBIOS8(offset + 5) & 0x3f; |
2675 | gpio = RBIOS8(offset + 5) & 0x3f; |
2677 | i2c_addr = RBIOS8(offset + 6); |
2676 | i2c_addr = RBIOS8(offset + 6); |
2678 | clk_bit = RBIOS8(offset + 0xa); |
2677 | clk_bit = RBIOS8(offset + 0xa); |
2679 | data_bit = RBIOS8(offset + 0xb); |
2678 | data_bit = RBIOS8(offset + 0xb); |
2680 | } |
2679 | } |
2681 | if ((thermal_controller > 0) && (thermal_controller < 3)) { |
2680 | if ((thermal_controller > 0) && (thermal_controller < 3)) { |
2682 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2681 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2683 | thermal_controller_names[thermal_controller], |
2682 | thermal_controller_names[thermal_controller], |
2684 | i2c_addr >> 1); |
2683 | i2c_addr >> 1); |
2685 | if (gpio == DDC_LCD) { |
2684 | if (gpio == DDC_LCD) { |
2686 | /* MM i2c */ |
2685 | /* MM i2c */ |
2687 | i2c_bus.valid = true; |
2686 | i2c_bus.valid = true; |
2688 | i2c_bus.hw_capable = true; |
2687 | i2c_bus.hw_capable = true; |
2689 | i2c_bus.mm_i2c = true; |
2688 | i2c_bus.mm_i2c = true; |
2690 | i2c_bus.i2c_id = 0xa0; |
2689 | i2c_bus.i2c_id = 0xa0; |
2691 | } else if (gpio == DDC_GPIO) |
2690 | } else if (gpio == DDC_GPIO) |
2692 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
2691 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
2693 | else |
2692 | else |
2694 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
2693 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
2695 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2694 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2696 | if (rdev->pm.i2c_bus) { |
2695 | if (rdev->pm.i2c_bus) { |
2697 | struct i2c_board_info info = { }; |
2696 | struct i2c_board_info info = { }; |
2698 | const char *name = thermal_controller_names[thermal_controller]; |
2697 | const char *name = thermal_controller_names[thermal_controller]; |
2699 | info.addr = i2c_addr >> 1; |
2698 | info.addr = i2c_addr >> 1; |
2700 | strlcpy(info.type, name, sizeof(info.type)); |
2699 | strlcpy(info.type, name, sizeof(info.type)); |
2701 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
2700 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
2702 | } |
2701 | } |
2703 | } |
2702 | } |
2704 | } else { |
2703 | } else { |
2705 | /* boards with a thermal chip, but no overdrive table */ |
2704 | /* boards with a thermal chip, but no overdrive table */ |
2706 | 2705 | ||
2707 | /* Asus 9600xt has an f75375 on the monid bus */ |
2706 | /* Asus 9600xt has an f75375 on the monid bus */ |
2708 | if ((dev->pdev->device == 0x4152) && |
2707 | if ((dev->pdev->device == 0x4152) && |
2709 | (dev->pdev->subsystem_vendor == 0x1043) && |
2708 | (dev->pdev->subsystem_vendor == 0x1043) && |
2710 | (dev->pdev->subsystem_device == 0xc002)) { |
2709 | (dev->pdev->subsystem_device == 0xc002)) { |
2711 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2710 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2712 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2711 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2713 | if (rdev->pm.i2c_bus) { |
2712 | if (rdev->pm.i2c_bus) { |
2714 | struct i2c_board_info info = { }; |
2713 | struct i2c_board_info info = { }; |
2715 | const char *name = "f75375"; |
2714 | const char *name = "f75375"; |
2716 | info.addr = 0x28; |
2715 | info.addr = 0x28; |
2717 | strlcpy(info.type, name, sizeof(info.type)); |
2716 | strlcpy(info.type, name, sizeof(info.type)); |
2718 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
2717 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
2719 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2718 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
2720 | name, info.addr); |
2719 | name, info.addr); |
2721 | } |
2720 | } |
2722 | } |
2721 | } |
2723 | } |
2722 | } |
2724 | 2723 | ||
2725 | if (rdev->flags & RADEON_IS_MOBILITY) { |
2724 | if (rdev->flags & RADEON_IS_MOBILITY) { |
2726 | offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); |
2725 | offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); |
2727 | if (offset) { |
2726 | if (offset) { |
2728 | rev = RBIOS8(offset); |
2727 | rev = RBIOS8(offset); |
2729 | blocks = RBIOS8(offset + 0x2); |
2728 | blocks = RBIOS8(offset + 0x2); |
2730 | /* power mode 0 tends to be the only valid one */ |
2729 | /* power mode 0 tends to be the only valid one */ |
2731 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2730 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2732 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); |
2731 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); |
2733 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); |
2732 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); |
2734 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2733 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2735 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2734 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2736 | goto default_mode; |
2735 | goto default_mode; |
2737 | rdev->pm.power_state[state_index].type = |
2736 | rdev->pm.power_state[state_index].type = |
2738 | POWER_STATE_TYPE_BATTERY; |
2737 | POWER_STATE_TYPE_BATTERY; |
2739 | misc = RBIOS16(offset + 0x5 + 0x0); |
2738 | misc = RBIOS16(offset + 0x5 + 0x0); |
2740 | if (rev > 4) |
2739 | if (rev > 4) |
2741 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
2740 | misc2 = RBIOS16(offset + 0x5 + 0xe); |
2742 | rdev->pm.power_state[state_index].misc = misc; |
2741 | rdev->pm.power_state[state_index].misc = misc; |
2743 | rdev->pm.power_state[state_index].misc2 = misc2; |
2742 | rdev->pm.power_state[state_index].misc2 = misc2; |
2744 | if (misc & 0x4) { |
2743 | if (misc & 0x4) { |
2745 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2744 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2746 | if (misc & 0x8) |
2745 | if (misc & 0x8) |
2747 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2746 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2748 | true; |
2747 | true; |
2749 | else |
2748 | else |
2750 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2749 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2751 | false; |
2750 | false; |
2752 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; |
2751 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; |
2753 | if (rev < 6) { |
2752 | if (rev < 6) { |
2754 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2753 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2755 | RBIOS16(offset + 0x5 + 0xb) * 4; |
2754 | RBIOS16(offset + 0x5 + 0xb) * 4; |
2756 | tmp = RBIOS8(offset + 0x5 + 0xd); |
2755 | tmp = RBIOS8(offset + 0x5 + 0xd); |
2757 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2756 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2758 | } else { |
2757 | } else { |
2759 | u8 entries = RBIOS8(offset + 0x5 + 0xb); |
2758 | u8 entries = RBIOS8(offset + 0x5 + 0xb); |
2760 | u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); |
2759 | u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); |
2761 | if (entries && voltage_table_offset) { |
2760 | if (entries && voltage_table_offset) { |
2762 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2761 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2763 | RBIOS16(voltage_table_offset) * 4; |
2762 | RBIOS16(voltage_table_offset) * 4; |
2764 | tmp = RBIOS8(voltage_table_offset + 0x2); |
2763 | tmp = RBIOS8(voltage_table_offset + 0x2); |
2765 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2764 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2766 | } else |
2765 | } else |
2767 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; |
2766 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; |
2768 | } |
2767 | } |
2769 | switch ((misc2 & 0x700) >> 8) { |
2768 | switch ((misc2 & 0x700) >> 8) { |
2770 | case 0: |
2769 | case 0: |
2771 | default: |
2770 | default: |
2772 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; |
2771 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; |
2773 | break; |
2772 | break; |
2774 | case 1: |
2773 | case 1: |
2775 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; |
2774 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; |
2776 | break; |
2775 | break; |
2777 | case 2: |
2776 | case 2: |
2778 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; |
2777 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; |
2779 | break; |
2778 | break; |
2780 | case 3: |
2779 | case 3: |
2781 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; |
2780 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; |
2782 | break; |
2781 | break; |
2783 | case 4: |
2782 | case 4: |
2784 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; |
2783 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; |
2785 | break; |
2784 | break; |
2786 | } |
2785 | } |
2787 | } else |
2786 | } else |
2788 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2787 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2789 | if (rev > 6) |
2788 | if (rev > 6) |
2790 | rdev->pm.power_state[state_index].pcie_lanes = |
2789 | rdev->pm.power_state[state_index].pcie_lanes = |
2791 | RBIOS8(offset + 0x5 + 0x10); |
2790 | RBIOS8(offset + 0x5 + 0x10); |
2792 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2791 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
2793 | state_index++; |
2792 | state_index++; |
2794 | } else { |
2793 | } else { |
2795 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2794 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2796 | } |
2795 | } |
2797 | } else { |
2796 | } else { |
2798 | /* XXX figure out some good default low power mode for desktop cards */ |
2797 | /* XXX figure out some good default low power mode for desktop cards */ |
2799 | } |
2798 | } |
2800 | 2799 | ||
2801 | default_mode: |
2800 | default_mode: |
2802 | /* add the default mode */ |
2801 | /* add the default mode */ |
2803 | rdev->pm.power_state[state_index].type = |
2802 | rdev->pm.power_state[state_index].type = |
2804 | POWER_STATE_TYPE_DEFAULT; |
2803 | POWER_STATE_TYPE_DEFAULT; |
2805 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2804 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2806 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
2805 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
2807 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2806 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2808 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
2807 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
2809 | if ((state_index > 0) && |
2808 | if ((state_index > 0) && |
2810 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
2809 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
2811 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
2810 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
2812 | rdev->pm.power_state[0].clock_info[0].voltage; |
2811 | rdev->pm.power_state[0].clock_info[0].voltage; |
2813 | else |
2812 | else |
2814 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2813 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2815 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
2814 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
2816 | rdev->pm.power_state[state_index].flags = 0; |
2815 | rdev->pm.power_state[state_index].flags = 0; |
2817 | rdev->pm.default_power_state_index = state_index; |
2816 | rdev->pm.default_power_state_index = state_index; |
2818 | rdev->pm.num_power_states = state_index + 1; |
2817 | rdev->pm.num_power_states = state_index + 1; |
2819 | 2818 | ||
2820 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2819 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2821 | rdev->pm.current_clock_mode_index = 0; |
2820 | rdev->pm.current_clock_mode_index = 0; |
2822 | return; |
2821 | return; |
2823 | 2822 | ||
2824 | pm_failed: |
2823 | pm_failed: |
2825 | rdev->pm.default_power_state_index = state_index; |
2824 | rdev->pm.default_power_state_index = state_index; |
2826 | rdev->pm.num_power_states = 0; |
2825 | rdev->pm.num_power_states = 0; |
2827 | 2826 | ||
2828 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2827 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2829 | rdev->pm.current_clock_mode_index = 0; |
2828 | rdev->pm.current_clock_mode_index = 0; |
2830 | } |
2829 | } |
2831 | 2830 | ||
2832 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2831 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2833 | { |
2832 | { |
2834 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2833 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2835 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2834 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2836 | 2835 | ||
2837 | if (!tmds) |
2836 | if (!tmds) |
2838 | return; |
2837 | return; |
2839 | 2838 | ||
2840 | switch (tmds->dvo_chip) { |
2839 | switch (tmds->dvo_chip) { |
2841 | case DVO_SIL164: |
2840 | case DVO_SIL164: |
2842 | /* sil 164 */ |
2841 | /* sil 164 */ |
2843 | radeon_i2c_put_byte(tmds->i2c_bus, |
2842 | radeon_i2c_put_byte(tmds->i2c_bus, |
2844 | tmds->slave_addr, |
2843 | tmds->slave_addr, |
2845 | 0x08, 0x30); |
2844 | 0x08, 0x30); |
2846 | radeon_i2c_put_byte(tmds->i2c_bus, |
2845 | radeon_i2c_put_byte(tmds->i2c_bus, |
2847 | tmds->slave_addr, |
2846 | tmds->slave_addr, |
2848 | 0x09, 0x00); |
2847 | 0x09, 0x00); |
2849 | radeon_i2c_put_byte(tmds->i2c_bus, |
2848 | radeon_i2c_put_byte(tmds->i2c_bus, |
2850 | tmds->slave_addr, |
2849 | tmds->slave_addr, |
2851 | 0x0a, 0x90); |
2850 | 0x0a, 0x90); |
2852 | radeon_i2c_put_byte(tmds->i2c_bus, |
2851 | radeon_i2c_put_byte(tmds->i2c_bus, |
2853 | tmds->slave_addr, |
2852 | tmds->slave_addr, |
2854 | 0x0c, 0x89); |
2853 | 0x0c, 0x89); |
2855 | radeon_i2c_put_byte(tmds->i2c_bus, |
2854 | radeon_i2c_put_byte(tmds->i2c_bus, |
2856 | tmds->slave_addr, |
2855 | tmds->slave_addr, |
2857 | 0x08, 0x3b); |
2856 | 0x08, 0x3b); |
2858 | break; |
2857 | break; |
2859 | case DVO_SIL1178: |
2858 | case DVO_SIL1178: |
2860 | /* sil 1178 - untested */ |
2859 | /* sil 1178 - untested */ |
2861 | /* |
2860 | /* |
2862 | * 0x0f, 0x44 |
2861 | * 0x0f, 0x44 |
2863 | * 0x0f, 0x4c |
2862 | * 0x0f, 0x4c |
2864 | * 0x0e, 0x01 |
2863 | * 0x0e, 0x01 |
2865 | * 0x0a, 0x80 |
2864 | * 0x0a, 0x80 |
2866 | * 0x09, 0x30 |
2865 | * 0x09, 0x30 |
2867 | * 0x0c, 0xc9 |
2866 | * 0x0c, 0xc9 |
2868 | * 0x0d, 0x70 |
2867 | * 0x0d, 0x70 |
2869 | * 0x08, 0x32 |
2868 | * 0x08, 0x32 |
2870 | * 0x08, 0x33 |
2869 | * 0x08, 0x33 |
2871 | */ |
2870 | */ |
2872 | break; |
2871 | break; |
2873 | default: |
2872 | default: |
2874 | break; |
2873 | break; |
2875 | } |
2874 | } |
2876 | 2875 | ||
2877 | } |
2876 | } |
2878 | 2877 | ||
2879 | bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) |
2878 | bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) |
2880 | { |
2879 | { |
2881 | struct drm_device *dev = encoder->dev; |
2880 | struct drm_device *dev = encoder->dev; |
2882 | struct radeon_device *rdev = dev->dev_private; |
2881 | struct radeon_device *rdev = dev->dev_private; |
2883 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2882 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
2884 | uint16_t offset; |
2883 | uint16_t offset; |
2885 | uint8_t blocks, slave_addr, rev; |
2884 | uint8_t blocks, slave_addr, rev; |
2886 | uint32_t index, id; |
2885 | uint32_t index, id; |
2887 | uint32_t reg, val, and_mask, or_mask; |
2886 | uint32_t reg, val, and_mask, or_mask; |
2888 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2887 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2889 | 2888 | ||
2890 | if (!tmds) |
2889 | if (!tmds) |
2891 | return false; |
2890 | return false; |
2892 | 2891 | ||
2893 | if (rdev->flags & RADEON_IS_IGP) { |
2892 | if (rdev->flags & RADEON_IS_IGP) { |
2894 | offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); |
2893 | offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); |
2895 | rev = RBIOS8(offset); |
2894 | rev = RBIOS8(offset); |
2896 | if (offset) { |
2895 | if (offset) { |
2897 | rev = RBIOS8(offset); |
2896 | rev = RBIOS8(offset); |
2898 | if (rev > 1) { |
2897 | if (rev > 1) { |
2899 | blocks = RBIOS8(offset + 3); |
2898 | blocks = RBIOS8(offset + 3); |
2900 | index = offset + 4; |
2899 | index = offset + 4; |
2901 | while (blocks > 0) { |
2900 | while (blocks > 0) { |
2902 | id = RBIOS16(index); |
2901 | id = RBIOS16(index); |
2903 | index += 2; |
2902 | index += 2; |
2904 | switch (id >> 13) { |
2903 | switch (id >> 13) { |
2905 | case 0: |
2904 | case 0: |
2906 | reg = (id & 0x1fff) * 4; |
2905 | reg = (id & 0x1fff) * 4; |
2907 | val = RBIOS32(index); |
2906 | val = RBIOS32(index); |
2908 | index += 4; |
2907 | index += 4; |
2909 | WREG32(reg, val); |
2908 | WREG32(reg, val); |
2910 | break; |
2909 | break; |
2911 | case 2: |
2910 | case 2: |
2912 | reg = (id & 0x1fff) * 4; |
2911 | reg = (id & 0x1fff) * 4; |
2913 | and_mask = RBIOS32(index); |
2912 | and_mask = RBIOS32(index); |
2914 | index += 4; |
2913 | index += 4; |
2915 | or_mask = RBIOS32(index); |
2914 | or_mask = RBIOS32(index); |
2916 | index += 4; |
2915 | index += 4; |
2917 | val = RREG32(reg); |
2916 | val = RREG32(reg); |
2918 | val = (val & and_mask) | or_mask; |
2917 | val = (val & and_mask) | or_mask; |
2919 | WREG32(reg, val); |
2918 | WREG32(reg, val); |
2920 | break; |
2919 | break; |
2921 | case 3: |
2920 | case 3: |
2922 | val = RBIOS16(index); |
2921 | val = RBIOS16(index); |
2923 | index += 2; |
2922 | index += 2; |
2924 | udelay(val); |
2923 | udelay(val); |
2925 | break; |
2924 | break; |
2926 | case 4: |
2925 | case 4: |
2927 | val = RBIOS16(index); |
2926 | val = RBIOS16(index); |
2928 | index += 2; |
2927 | index += 2; |
2929 | mdelay(val); |
2928 | mdelay(val); |
2930 | break; |
2929 | break; |
2931 | case 6: |
2930 | case 6: |
2932 | slave_addr = id & 0xff; |
2931 | slave_addr = id & 0xff; |
2933 | slave_addr >>= 1; /* 7 bit addressing */ |
2932 | slave_addr >>= 1; /* 7 bit addressing */ |
2934 | index++; |
2933 | index++; |
2935 | reg = RBIOS8(index); |
2934 | reg = RBIOS8(index); |
2936 | index++; |
2935 | index++; |
2937 | val = RBIOS8(index); |
2936 | val = RBIOS8(index); |
2938 | index++; |
2937 | index++; |
2939 | radeon_i2c_put_byte(tmds->i2c_bus, |
2938 | radeon_i2c_put_byte(tmds->i2c_bus, |
2940 | slave_addr, |
2939 | slave_addr, |
2941 | reg, val); |
2940 | reg, val); |
2942 | break; |
2941 | break; |
2943 | default: |
2942 | default: |
2944 | DRM_ERROR("Unknown id %d\n", id >> 13); |
2943 | DRM_ERROR("Unknown id %d\n", id >> 13); |
2945 | break; |
2944 | break; |
2946 | } |
2945 | } |
2947 | blocks--; |
2946 | blocks--; |
2948 | } |
2947 | } |
2949 | return true; |
2948 | return true; |
2950 | } |
2949 | } |
2951 | } |
2950 | } |
2952 | } else { |
2951 | } else { |
2953 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2952 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2954 | if (offset) { |
2953 | if (offset) { |
2955 | index = offset + 10; |
2954 | index = offset + 10; |
2956 | id = RBIOS16(index); |
2955 | id = RBIOS16(index); |
2957 | while (id != 0xffff) { |
2956 | while (id != 0xffff) { |
2958 | index += 2; |
2957 | index += 2; |
2959 | switch (id >> 13) { |
2958 | switch (id >> 13) { |
2960 | case 0: |
2959 | case 0: |
2961 | reg = (id & 0x1fff) * 4; |
2960 | reg = (id & 0x1fff) * 4; |
2962 | val = RBIOS32(index); |
2961 | val = RBIOS32(index); |
2963 | WREG32(reg, val); |
2962 | WREG32(reg, val); |
2964 | break; |
2963 | break; |
2965 | case 2: |
2964 | case 2: |
2966 | reg = (id & 0x1fff) * 4; |
2965 | reg = (id & 0x1fff) * 4; |
2967 | and_mask = RBIOS32(index); |
2966 | and_mask = RBIOS32(index); |
2968 | index += 4; |
2967 | index += 4; |
2969 | or_mask = RBIOS32(index); |
2968 | or_mask = RBIOS32(index); |
2970 | index += 4; |
2969 | index += 4; |
2971 | val = RREG32(reg); |
2970 | val = RREG32(reg); |
2972 | val = (val & and_mask) | or_mask; |
2971 | val = (val & and_mask) | or_mask; |
2973 | WREG32(reg, val); |
2972 | WREG32(reg, val); |
2974 | break; |
2973 | break; |
2975 | case 4: |
2974 | case 4: |
2976 | val = RBIOS16(index); |
2975 | val = RBIOS16(index); |
2977 | index += 2; |
2976 | index += 2; |
2978 | udelay(val); |
2977 | udelay(val); |
2979 | break; |
2978 | break; |
2980 | case 5: |
2979 | case 5: |
2981 | reg = id & 0x1fff; |
2980 | reg = id & 0x1fff; |
2982 | and_mask = RBIOS32(index); |
2981 | and_mask = RBIOS32(index); |
2983 | index += 4; |
2982 | index += 4; |
2984 | or_mask = RBIOS32(index); |
2983 | or_mask = RBIOS32(index); |
2985 | index += 4; |
2984 | index += 4; |
2986 | val = RREG32_PLL(reg); |
2985 | val = RREG32_PLL(reg); |
2987 | val = (val & and_mask) | or_mask; |
2986 | val = (val & and_mask) | or_mask; |
2988 | WREG32_PLL(reg, val); |
2987 | WREG32_PLL(reg, val); |
2989 | break; |
2988 | break; |
2990 | case 6: |
2989 | case 6: |
2991 | reg = id & 0x1fff; |
2990 | reg = id & 0x1fff; |
2992 | val = RBIOS8(index); |
2991 | val = RBIOS8(index); |
2993 | index += 1; |
2992 | index += 1; |
2994 | radeon_i2c_put_byte(tmds->i2c_bus, |
2993 | radeon_i2c_put_byte(tmds->i2c_bus, |
2995 | tmds->slave_addr, |
2994 | tmds->slave_addr, |
2996 | reg, val); |
2995 | reg, val); |
2997 | break; |
2996 | break; |
2998 | default: |
2997 | default: |
2999 | DRM_ERROR("Unknown id %d\n", id >> 13); |
2998 | DRM_ERROR("Unknown id %d\n", id >> 13); |
3000 | break; |
2999 | break; |
3001 | } |
3000 | } |
3002 | id = RBIOS16(index); |
3001 | id = RBIOS16(index); |
3003 | } |
3002 | } |
3004 | return true; |
3003 | return true; |
3005 | } |
3004 | } |
3006 | } |
3005 | } |
3007 | return false; |
3006 | return false; |
3008 | } |
3007 | } |
3009 | 3008 | ||
3010 | static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) |
3009 | static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) |
3011 | { |
3010 | { |
3012 | struct radeon_device *rdev = dev->dev_private; |
3011 | struct radeon_device *rdev = dev->dev_private; |
3013 | 3012 | ||
3014 | if (offset) { |
3013 | if (offset) { |
3015 | while (RBIOS16(offset)) { |
3014 | while (RBIOS16(offset)) { |
3016 | uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); |
3015 | uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); |
3017 | uint32_t addr = (RBIOS16(offset) & 0x1fff); |
3016 | uint32_t addr = (RBIOS16(offset) & 0x1fff); |
3018 | uint32_t val, and_mask, or_mask; |
3017 | uint32_t val, and_mask, or_mask; |
3019 | uint32_t tmp; |
3018 | uint32_t tmp; |
3020 | 3019 | ||
3021 | offset += 2; |
3020 | offset += 2; |
3022 | switch (cmd) { |
3021 | switch (cmd) { |
3023 | case 0: |
3022 | case 0: |
3024 | val = RBIOS32(offset); |
3023 | val = RBIOS32(offset); |
3025 | offset += 4; |
3024 | offset += 4; |
3026 | WREG32(addr, val); |
3025 | WREG32(addr, val); |
3027 | break; |
3026 | break; |
3028 | case 1: |
3027 | case 1: |
3029 | val = RBIOS32(offset); |
3028 | val = RBIOS32(offset); |
3030 | offset += 4; |
3029 | offset += 4; |
3031 | WREG32(addr, val); |
3030 | WREG32(addr, val); |
3032 | break; |
3031 | break; |
3033 | case 2: |
3032 | case 2: |
3034 | and_mask = RBIOS32(offset); |
3033 | and_mask = RBIOS32(offset); |
3035 | offset += 4; |
3034 | offset += 4; |
3036 | or_mask = RBIOS32(offset); |
3035 | or_mask = RBIOS32(offset); |
3037 | offset += 4; |
3036 | offset += 4; |
3038 | tmp = RREG32(addr); |
3037 | tmp = RREG32(addr); |
3039 | tmp &= and_mask; |
3038 | tmp &= and_mask; |
3040 | tmp |= or_mask; |
3039 | tmp |= or_mask; |
3041 | WREG32(addr, tmp); |
3040 | WREG32(addr, tmp); |
3042 | break; |
3041 | break; |
3043 | case 3: |
3042 | case 3: |
3044 | and_mask = RBIOS32(offset); |
3043 | and_mask = RBIOS32(offset); |
3045 | offset += 4; |
3044 | offset += 4; |
3046 | or_mask = RBIOS32(offset); |
3045 | or_mask = RBIOS32(offset); |
3047 | offset += 4; |
3046 | offset += 4; |
3048 | tmp = RREG32(addr); |
3047 | tmp = RREG32(addr); |
3049 | tmp &= and_mask; |
3048 | tmp &= and_mask; |
3050 | tmp |= or_mask; |
3049 | tmp |= or_mask; |
3051 | WREG32(addr, tmp); |
3050 | WREG32(addr, tmp); |
3052 | break; |
3051 | break; |
3053 | case 4: |
3052 | case 4: |
3054 | val = RBIOS16(offset); |
3053 | val = RBIOS16(offset); |
3055 | offset += 2; |
3054 | offset += 2; |
3056 | udelay(val); |
3055 | udelay(val); |
3057 | break; |
3056 | break; |
3058 | case 5: |
3057 | case 5: |
3059 | val = RBIOS16(offset); |
3058 | val = RBIOS16(offset); |
3060 | offset += 2; |
3059 | offset += 2; |
3061 | switch (addr) { |
3060 | switch (addr) { |
3062 | case 8: |
3061 | case 8: |
3063 | while (val--) { |
3062 | while (val--) { |
3064 | if (! |
3063 | if (! |
3065 | (RREG32_PLL |
3064 | (RREG32_PLL |
3066 | (RADEON_CLK_PWRMGT_CNTL) & |
3065 | (RADEON_CLK_PWRMGT_CNTL) & |
3067 | RADEON_MC_BUSY)) |
3066 | RADEON_MC_BUSY)) |
3068 | break; |
3067 | break; |
3069 | } |
3068 | } |
3070 | break; |
3069 | break; |
3071 | case 9: |
3070 | case 9: |
3072 | while (val--) { |
3071 | while (val--) { |
3073 | if ((RREG32(RADEON_MC_STATUS) & |
3072 | if ((RREG32(RADEON_MC_STATUS) & |
3074 | RADEON_MC_IDLE)) |
3073 | RADEON_MC_IDLE)) |
3075 | break; |
3074 | break; |
3076 | } |
3075 | } |
3077 | break; |
3076 | break; |
3078 | default: |
3077 | default: |
3079 | break; |
3078 | break; |
3080 | } |
3079 | } |
3081 | break; |
3080 | break; |
3082 | default: |
3081 | default: |
3083 | break; |
3082 | break; |
3084 | } |
3083 | } |
3085 | } |
3084 | } |
3086 | } |
3085 | } |
3087 | } |
3086 | } |
3088 | 3087 | ||
3089 | static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) |
3088 | static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) |
3090 | { |
3089 | { |
3091 | struct radeon_device *rdev = dev->dev_private; |
3090 | struct radeon_device *rdev = dev->dev_private; |
3092 | 3091 | ||
3093 | if (offset) { |
3092 | if (offset) { |
3094 | while (RBIOS8(offset)) { |
3093 | while (RBIOS8(offset)) { |
3095 | uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); |
3094 | uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); |
3096 | uint8_t addr = (RBIOS8(offset) & 0x3f); |
3095 | uint8_t addr = (RBIOS8(offset) & 0x3f); |
3097 | uint32_t val, shift, tmp; |
3096 | uint32_t val, shift, tmp; |
3098 | uint32_t and_mask, or_mask; |
3097 | uint32_t and_mask, or_mask; |
3099 | 3098 | ||
3100 | offset++; |
3099 | offset++; |
3101 | switch (cmd) { |
3100 | switch (cmd) { |
3102 | case 0: |
3101 | case 0: |
3103 | val = RBIOS32(offset); |
3102 | val = RBIOS32(offset); |
3104 | offset += 4; |
3103 | offset += 4; |
3105 | WREG32_PLL(addr, val); |
3104 | WREG32_PLL(addr, val); |
3106 | break; |
3105 | break; |
3107 | case 1: |
3106 | case 1: |
3108 | shift = RBIOS8(offset) * 8; |
3107 | shift = RBIOS8(offset) * 8; |
3109 | offset++; |
3108 | offset++; |
3110 | and_mask = RBIOS8(offset) << shift; |
3109 | and_mask = RBIOS8(offset) << shift; |
3111 | and_mask |= ~(0xff << shift); |
3110 | and_mask |= ~(0xff << shift); |
3112 | offset++; |
3111 | offset++; |
3113 | or_mask = RBIOS8(offset) << shift; |
3112 | or_mask = RBIOS8(offset) << shift; |
3114 | offset++; |
3113 | offset++; |
3115 | tmp = RREG32_PLL(addr); |
3114 | tmp = RREG32_PLL(addr); |
3116 | tmp &= and_mask; |
3115 | tmp &= and_mask; |
3117 | tmp |= or_mask; |
3116 | tmp |= or_mask; |
3118 | WREG32_PLL(addr, tmp); |
3117 | WREG32_PLL(addr, tmp); |
3119 | break; |
3118 | break; |
3120 | case 2: |
3119 | case 2: |
3121 | case 3: |
3120 | case 3: |
3122 | tmp = 1000; |
3121 | tmp = 1000; |
3123 | switch (addr) { |
3122 | switch (addr) { |
3124 | case 1: |
3123 | case 1: |
3125 | udelay(150); |
3124 | udelay(150); |
3126 | break; |
3125 | break; |
3127 | case 2: |
3126 | case 2: |
3128 | mdelay(1); |
3127 | mdelay(1); |
3129 | break; |
3128 | break; |
3130 | case 3: |
3129 | case 3: |
3131 | while (tmp--) { |
3130 | while (tmp--) { |
3132 | if (! |
3131 | if (! |
3133 | (RREG32_PLL |
3132 | (RREG32_PLL |
3134 | (RADEON_CLK_PWRMGT_CNTL) & |
3133 | (RADEON_CLK_PWRMGT_CNTL) & |
3135 | RADEON_MC_BUSY)) |
3134 | RADEON_MC_BUSY)) |
3136 | break; |
3135 | break; |
3137 | } |
3136 | } |
3138 | break; |
3137 | break; |
3139 | case 4: |
3138 | case 4: |
3140 | while (tmp--) { |
3139 | while (tmp--) { |
3141 | if (RREG32_PLL |
3140 | if (RREG32_PLL |
3142 | (RADEON_CLK_PWRMGT_CNTL) & |
3141 | (RADEON_CLK_PWRMGT_CNTL) & |
3143 | RADEON_DLL_READY) |
3142 | RADEON_DLL_READY) |
3144 | break; |
3143 | break; |
3145 | } |
3144 | } |
3146 | break; |
3145 | break; |
3147 | case 5: |
3146 | case 5: |
3148 | tmp = |
3147 | tmp = |
3149 | RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
3148 | RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
3150 | if (tmp & RADEON_CG_NO1_DEBUG_0) { |
3149 | if (tmp & RADEON_CG_NO1_DEBUG_0) { |
3151 | #if 0 |
3150 | #if 0 |
3152 | uint32_t mclk_cntl = |
3151 | uint32_t mclk_cntl = |
3153 | RREG32_PLL |
3152 | RREG32_PLL |
3154 | (RADEON_MCLK_CNTL); |
3153 | (RADEON_MCLK_CNTL); |
3155 | mclk_cntl &= 0xffff0000; |
3154 | mclk_cntl &= 0xffff0000; |
3156 | /*mclk_cntl |= 0x00001111;*//* ??? */ |
3155 | /*mclk_cntl |= 0x00001111;*//* ??? */ |
3157 | WREG32_PLL(RADEON_MCLK_CNTL, |
3156 | WREG32_PLL(RADEON_MCLK_CNTL, |
3158 | mclk_cntl); |
3157 | mclk_cntl); |
3159 | mdelay(10); |
3158 | mdelay(10); |
3160 | #endif |
3159 | #endif |
3161 | WREG32_PLL |
3160 | WREG32_PLL |
3162 | (RADEON_CLK_PWRMGT_CNTL, |
3161 | (RADEON_CLK_PWRMGT_CNTL, |
3163 | tmp & |
3162 | tmp & |
3164 | ~RADEON_CG_NO1_DEBUG_0); |
3163 | ~RADEON_CG_NO1_DEBUG_0); |
3165 | mdelay(10); |
3164 | mdelay(10); |
3166 | } |
3165 | } |
3167 | break; |
3166 | break; |
3168 | default: |
3167 | default: |
3169 | break; |
3168 | break; |
3170 | } |
3169 | } |
3171 | break; |
3170 | break; |
3172 | default: |
3171 | default: |
3173 | break; |
3172 | break; |
3174 | } |
3173 | } |
3175 | } |
3174 | } |
3176 | } |
3175 | } |
3177 | } |
3176 | } |
3178 | 3177 | ||
3179 | static void combios_parse_ram_reset_table(struct drm_device *dev, |
3178 | static void combios_parse_ram_reset_table(struct drm_device *dev, |
3180 | uint16_t offset) |
3179 | uint16_t offset) |
3181 | { |
3180 | { |
3182 | struct radeon_device *rdev = dev->dev_private; |
3181 | struct radeon_device *rdev = dev->dev_private; |
3183 | uint32_t tmp; |
3182 | uint32_t tmp; |
3184 | 3183 | ||
3185 | if (offset) { |
3184 | if (offset) { |
3186 | uint8_t val = RBIOS8(offset); |
3185 | uint8_t val = RBIOS8(offset); |
3187 | while (val != 0xff) { |
3186 | while (val != 0xff) { |
3188 | offset++; |
3187 | offset++; |
3189 | 3188 | ||
3190 | if (val == 0x0f) { |
3189 | if (val == 0x0f) { |
3191 | uint32_t channel_complete_mask; |
3190 | uint32_t channel_complete_mask; |
3192 | 3191 | ||
3193 | if (ASIC_IS_R300(rdev)) |
3192 | if (ASIC_IS_R300(rdev)) |
3194 | channel_complete_mask = |
3193 | channel_complete_mask = |
3195 | R300_MEM_PWRUP_COMPLETE; |
3194 | R300_MEM_PWRUP_COMPLETE; |
3196 | else |
3195 | else |
3197 | channel_complete_mask = |
3196 | channel_complete_mask = |
3198 | RADEON_MEM_PWRUP_COMPLETE; |
3197 | RADEON_MEM_PWRUP_COMPLETE; |
3199 | tmp = 20000; |
3198 | tmp = 20000; |
3200 | while (tmp--) { |
3199 | while (tmp--) { |
3201 | if ((RREG32(RADEON_MEM_STR_CNTL) & |
3200 | if ((RREG32(RADEON_MEM_STR_CNTL) & |
3202 | channel_complete_mask) == |
3201 | channel_complete_mask) == |
3203 | channel_complete_mask) |
3202 | channel_complete_mask) |
3204 | break; |
3203 | break; |
3205 | } |
3204 | } |
3206 | } else { |
3205 | } else { |
3207 | uint32_t or_mask = RBIOS16(offset); |
3206 | uint32_t or_mask = RBIOS16(offset); |
3208 | offset += 2; |
3207 | offset += 2; |
3209 | 3208 | ||
3210 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3209 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3211 | tmp &= RADEON_SDRAM_MODE_MASK; |
3210 | tmp &= RADEON_SDRAM_MODE_MASK; |
3212 | tmp |= or_mask; |
3211 | tmp |= or_mask; |
3213 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
3212 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
3214 | 3213 | ||
3215 | or_mask = val << 24; |
3214 | or_mask = val << 24; |
3216 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3215 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
3217 | tmp &= RADEON_B3MEM_RESET_MASK; |
3216 | tmp &= RADEON_B3MEM_RESET_MASK; |
3218 | tmp |= or_mask; |
3217 | tmp |= or_mask; |
3219 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
3218 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); |
3220 | } |
3219 | } |
3221 | val = RBIOS8(offset); |
3220 | val = RBIOS8(offset); |
3222 | } |
3221 | } |
3223 | } |
3222 | } |
3224 | } |
3223 | } |
3225 | 3224 | ||
3226 | static uint32_t combios_detect_ram(struct drm_device *dev, int ram, |
3225 | static uint32_t combios_detect_ram(struct drm_device *dev, int ram, |
3227 | int mem_addr_mapping) |
3226 | int mem_addr_mapping) |
3228 | { |
3227 | { |
3229 | struct radeon_device *rdev = dev->dev_private; |
3228 | struct radeon_device *rdev = dev->dev_private; |
3230 | uint32_t mem_cntl; |
3229 | uint32_t mem_cntl; |
3231 | uint32_t mem_size; |
3230 | uint32_t mem_size; |
3232 | uint32_t addr = 0; |
3231 | uint32_t addr = 0; |
3233 | 3232 | ||
3234 | mem_cntl = RREG32(RADEON_MEM_CNTL); |
3233 | mem_cntl = RREG32(RADEON_MEM_CNTL); |
3235 | if (mem_cntl & RV100_HALF_MODE) |
3234 | if (mem_cntl & RV100_HALF_MODE) |
3236 | ram /= 2; |
3235 | ram /= 2; |
3237 | mem_size = ram; |
3236 | mem_size = ram; |
3238 | mem_cntl &= ~(0xff << 8); |
3237 | mem_cntl &= ~(0xff << 8); |
3239 | mem_cntl |= (mem_addr_mapping & 0xff) << 8; |
3238 | mem_cntl |= (mem_addr_mapping & 0xff) << 8; |
3240 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3239 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3241 | RREG32(RADEON_MEM_CNTL); |
3240 | RREG32(RADEON_MEM_CNTL); |
3242 | 3241 | ||
3243 | /* sdram reset ? */ |
3242 | /* sdram reset ? */ |
3244 | 3243 | ||
3245 | /* something like this???? */ |
3244 | /* something like this???? */ |
3246 | while (ram--) { |
3245 | while (ram--) { |
3247 | addr = ram * 1024 * 1024; |
3246 | addr = ram * 1024 * 1024; |
3248 | /* write to each page */ |
3247 | /* write to each page */ |
3249 | WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); |
3248 | WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); |
3250 | /* read back and verify */ |
3249 | /* read back and verify */ |
3251 | if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) |
3250 | if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) |
3252 | return 0; |
3251 | return 0; |
3253 | } |
3252 | } |
3254 | 3253 | ||
3255 | return mem_size; |
3254 | return mem_size; |
3256 | } |
3255 | } |
3257 | 3256 | ||
3258 | static void combios_write_ram_size(struct drm_device *dev) |
3257 | static void combios_write_ram_size(struct drm_device *dev) |
3259 | { |
3258 | { |
3260 | struct radeon_device *rdev = dev->dev_private; |
3259 | struct radeon_device *rdev = dev->dev_private; |
3261 | uint8_t rev; |
3260 | uint8_t rev; |
3262 | uint16_t offset; |
3261 | uint16_t offset; |
3263 | uint32_t mem_size = 0; |
3262 | uint32_t mem_size = 0; |
3264 | uint32_t mem_cntl = 0; |
3263 | uint32_t mem_cntl = 0; |
3265 | 3264 | ||
3266 | /* should do something smarter here I guess... */ |
3265 | /* should do something smarter here I guess... */ |
3267 | if (rdev->flags & RADEON_IS_IGP) |
3266 | if (rdev->flags & RADEON_IS_IGP) |
3268 | return; |
3267 | return; |
3269 | 3268 | ||
3270 | /* first check detected mem table */ |
3269 | /* first check detected mem table */ |
3271 | offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); |
3270 | offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); |
3272 | if (offset) { |
3271 | if (offset) { |
3273 | rev = RBIOS8(offset); |
3272 | rev = RBIOS8(offset); |
3274 | if (rev < 3) { |
3273 | if (rev < 3) { |
3275 | mem_cntl = RBIOS32(offset + 1); |
3274 | mem_cntl = RBIOS32(offset + 1); |
3276 | mem_size = RBIOS16(offset + 5); |
3275 | mem_size = RBIOS16(offset + 5); |
3277 | if ((rdev->family < CHIP_R200) && |
3276 | if ((rdev->family < CHIP_R200) && |
3278 | !ASIC_IS_RN50(rdev)) |
3277 | !ASIC_IS_RN50(rdev)) |
3279 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3278 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3280 | } |
3279 | } |
3281 | } |
3280 | } |
3282 | 3281 | ||
3283 | if (!mem_size) { |
3282 | if (!mem_size) { |
3284 | offset = |
3283 | offset = |
3285 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
3284 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
3286 | if (offset) { |
3285 | if (offset) { |
3287 | rev = RBIOS8(offset - 1); |
3286 | rev = RBIOS8(offset - 1); |
3288 | if (rev < 1) { |
3287 | if (rev < 1) { |
3289 | if ((rdev->family < CHIP_R200) |
3288 | if ((rdev->family < CHIP_R200) |
3290 | && !ASIC_IS_RN50(rdev)) { |
3289 | && !ASIC_IS_RN50(rdev)) { |
3291 | int ram = 0; |
3290 | int ram = 0; |
3292 | int mem_addr_mapping = 0; |
3291 | int mem_addr_mapping = 0; |
3293 | 3292 | ||
3294 | while (RBIOS8(offset)) { |
3293 | while (RBIOS8(offset)) { |
3295 | ram = RBIOS8(offset); |
3294 | ram = RBIOS8(offset); |
3296 | mem_addr_mapping = |
3295 | mem_addr_mapping = |
3297 | RBIOS8(offset + 1); |
3296 | RBIOS8(offset + 1); |
3298 | if (mem_addr_mapping != 0x25) |
3297 | if (mem_addr_mapping != 0x25) |
3299 | ram *= 2; |
3298 | ram *= 2; |
3300 | mem_size = |
3299 | mem_size = |
3301 | combios_detect_ram(dev, ram, |
3300 | combios_detect_ram(dev, ram, |
3302 | mem_addr_mapping); |
3301 | mem_addr_mapping); |
3303 | if (mem_size) |
3302 | if (mem_size) |
3304 | break; |
3303 | break; |
3305 | offset += 2; |
3304 | offset += 2; |
3306 | } |
3305 | } |
3307 | } else |
3306 | } else |
3308 | mem_size = RBIOS8(offset); |
3307 | mem_size = RBIOS8(offset); |
3309 | } else { |
3308 | } else { |
3310 | mem_size = RBIOS8(offset); |
3309 | mem_size = RBIOS8(offset); |
3311 | mem_size *= 2; /* convert to MB */ |
3310 | mem_size *= 2; /* convert to MB */ |
3312 | } |
3311 | } |
3313 | } |
3312 | } |
3314 | } |
3313 | } |
3315 | 3314 | ||
3316 | mem_size *= (1024 * 1024); /* convert to bytes */ |
3315 | mem_size *= (1024 * 1024); /* convert to bytes */ |
3317 | WREG32(RADEON_CONFIG_MEMSIZE, mem_size); |
3316 | WREG32(RADEON_CONFIG_MEMSIZE, mem_size); |
3318 | } |
3317 | } |
3319 | 3318 | ||
3320 | void radeon_combios_asic_init(struct drm_device *dev) |
3319 | void radeon_combios_asic_init(struct drm_device *dev) |
3321 | { |
3320 | { |
3322 | struct radeon_device *rdev = dev->dev_private; |
3321 | struct radeon_device *rdev = dev->dev_private; |
3323 | uint16_t table; |
3322 | uint16_t table; |
3324 | 3323 | ||
3325 | /* port hardcoded mac stuff from radeonfb */ |
3324 | /* port hardcoded mac stuff from radeonfb */ |
3326 | if (rdev->bios == NULL) |
3325 | if (rdev->bios == NULL) |
3327 | return; |
3326 | return; |
3328 | 3327 | ||
3329 | /* ASIC INIT 1 */ |
3328 | /* ASIC INIT 1 */ |
3330 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); |
3329 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); |
3331 | if (table) |
3330 | if (table) |
3332 | combios_parse_mmio_table(dev, table); |
3331 | combios_parse_mmio_table(dev, table); |
3333 | 3332 | ||
3334 | /* PLL INIT */ |
3333 | /* PLL INIT */ |
3335 | table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); |
3334 | table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); |
3336 | if (table) |
3335 | if (table) |
3337 | combios_parse_pll_table(dev, table); |
3336 | combios_parse_pll_table(dev, table); |
3338 | 3337 | ||
3339 | /* ASIC INIT 2 */ |
3338 | /* ASIC INIT 2 */ |
3340 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); |
3339 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); |
3341 | if (table) |
3340 | if (table) |
3342 | combios_parse_mmio_table(dev, table); |
3341 | combios_parse_mmio_table(dev, table); |
3343 | 3342 | ||
3344 | if (!(rdev->flags & RADEON_IS_IGP)) { |
3343 | if (!(rdev->flags & RADEON_IS_IGP)) { |
3345 | /* ASIC INIT 4 */ |
3344 | /* ASIC INIT 4 */ |
3346 | table = |
3345 | table = |
3347 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); |
3346 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); |
3348 | if (table) |
3347 | if (table) |
3349 | combios_parse_mmio_table(dev, table); |
3348 | combios_parse_mmio_table(dev, table); |
3350 | 3349 | ||
3351 | /* RAM RESET */ |
3350 | /* RAM RESET */ |
3352 | table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); |
3351 | table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); |
3353 | if (table) |
3352 | if (table) |
3354 | combios_parse_ram_reset_table(dev, table); |
3353 | combios_parse_ram_reset_table(dev, table); |
3355 | 3354 | ||
3356 | /* ASIC INIT 3 */ |
3355 | /* ASIC INIT 3 */ |
3357 | table = |
3356 | table = |
3358 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); |
3357 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); |
3359 | if (table) |
3358 | if (table) |
3360 | combios_parse_mmio_table(dev, table); |
3359 | combios_parse_mmio_table(dev, table); |
3361 | 3360 | ||
3362 | /* write CONFIG_MEMSIZE */ |
3361 | /* write CONFIG_MEMSIZE */ |
3363 | combios_write_ram_size(dev); |
3362 | combios_write_ram_size(dev); |
3364 | } |
3363 | } |
3365 | 3364 | ||
3366 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
3365 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
3367 | * - it hangs on resume inside the dynclk 1 table. |
3366 | * - it hangs on resume inside the dynclk 1 table. |
3368 | */ |
3367 | */ |
3369 | if (rdev->family == CHIP_RS480 && |
3368 | if (rdev->family == CHIP_RS480 && |
3370 | rdev->pdev->subsystem_vendor == 0x103c && |
3369 | rdev->pdev->subsystem_vendor == 0x103c && |
3371 | rdev->pdev->subsystem_device == 0x308b) |
3370 | rdev->pdev->subsystem_device == 0x308b) |
3372 | return; |
3371 | return; |
3373 | 3372 | ||
3374 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
3373 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
3375 | * - it hangs on resume inside the dynclk 1 table. |
3374 | * - it hangs on resume inside the dynclk 1 table. |
3376 | */ |
3375 | */ |
3377 | if (rdev->family == CHIP_RS480 && |
3376 | if (rdev->family == CHIP_RS480 && |
3378 | rdev->pdev->subsystem_vendor == 0x103c && |
3377 | rdev->pdev->subsystem_vendor == 0x103c && |
3379 | rdev->pdev->subsystem_device == 0x30a4) |
3378 | rdev->pdev->subsystem_device == 0x30a4) |
3380 | return; |
3379 | return; |
3381 | 3380 | ||
3382 | /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume |
3381 | /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume |
3383 | * - it hangs on resume inside the dynclk 1 table. |
3382 | * - it hangs on resume inside the dynclk 1 table. |
3384 | */ |
3383 | */ |
3385 | if (rdev->family == CHIP_RS480 && |
3384 | if (rdev->family == CHIP_RS480 && |
3386 | rdev->pdev->subsystem_vendor == 0x103c && |
3385 | rdev->pdev->subsystem_vendor == 0x103c && |
3387 | rdev->pdev->subsystem_device == 0x30ae) |
3386 | rdev->pdev->subsystem_device == 0x30ae) |
3388 | return; |
3387 | return; |
3389 | 3388 | ||
3390 | /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume |
3389 | /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume |
3391 | * - it hangs on resume inside the dynclk 1 table. |
3390 | * - it hangs on resume inside the dynclk 1 table. |
3392 | */ |
3391 | */ |
3393 | if (rdev->family == CHIP_RS480 && |
3392 | if (rdev->family == CHIP_RS480 && |
3394 | rdev->pdev->subsystem_vendor == 0x103c && |
3393 | rdev->pdev->subsystem_vendor == 0x103c && |
3395 | rdev->pdev->subsystem_device == 0x280a) |
3394 | rdev->pdev->subsystem_device == 0x280a) |
3396 | return; |
3395 | return; |
3397 | 3396 | ||
3398 | /* DYN CLK 1 */ |
3397 | /* DYN CLK 1 */ |
3399 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
3398 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
3400 | if (table) |
3399 | if (table) |
3401 | combios_parse_pll_table(dev, table); |
3400 | combios_parse_pll_table(dev, table); |
3402 | 3401 | ||
3403 | } |
3402 | } |
3404 | 3403 | ||
3405 | void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) |
3404 | void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) |
3406 | { |
3405 | { |
3407 | struct radeon_device *rdev = dev->dev_private; |
3406 | struct radeon_device *rdev = dev->dev_private; |
3408 | uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; |
3407 | uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; |
3409 | 3408 | ||
3410 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
3409 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
3411 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3410 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3412 | bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); |
3411 | bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); |
3413 | 3412 | ||
3414 | /* let the bios control the backlight */ |
3413 | /* let the bios control the backlight */ |
3415 | bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; |
3414 | bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; |
3416 | 3415 | ||
3417 | /* tell the bios not to handle mode switching */ |
3416 | /* tell the bios not to handle mode switching */ |
3418 | bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | |
3417 | bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | |
3419 | RADEON_ACC_MODE_CHANGE); |
3418 | RADEON_ACC_MODE_CHANGE); |
3420 | 3419 | ||
3421 | /* tell the bios a driver is loaded */ |
3420 | /* tell the bios a driver is loaded */ |
3422 | bios_7_scratch |= RADEON_DRV_LOADED; |
3421 | bios_7_scratch |= RADEON_DRV_LOADED; |
3423 | 3422 | ||
3424 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
3423 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
3425 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3424 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3426 | WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); |
3425 | WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); |
3427 | } |
3426 | } |
3428 | 3427 | ||
3429 | void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) |
3428 | void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) |
3430 | { |
3429 | { |
3431 | struct drm_device *dev = encoder->dev; |
3430 | struct drm_device *dev = encoder->dev; |
3432 | struct radeon_device *rdev = dev->dev_private; |
3431 | struct radeon_device *rdev = dev->dev_private; |
3433 | uint32_t bios_6_scratch; |
3432 | uint32_t bios_6_scratch; |
3434 | 3433 | ||
3435 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3434 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3436 | 3435 | ||
3437 | if (lock) |
3436 | if (lock) |
3438 | bios_6_scratch |= RADEON_DRIVER_CRITICAL; |
3437 | bios_6_scratch |= RADEON_DRIVER_CRITICAL; |
3439 | else |
3438 | else |
3440 | bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; |
3439 | bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; |
3441 | 3440 | ||
3442 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3441 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3443 | } |
3442 | } |
3444 | 3443 | ||
3445 | void |
3444 | void |
3446 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
3445 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
3447 | struct drm_encoder *encoder, |
3446 | struct drm_encoder *encoder, |
3448 | bool connected) |
3447 | bool connected) |
3449 | { |
3448 | { |
3450 | struct drm_device *dev = connector->dev; |
3449 | struct drm_device *dev = connector->dev; |
3451 | struct radeon_device *rdev = dev->dev_private; |
3450 | struct radeon_device *rdev = dev->dev_private; |
3452 | struct radeon_connector *radeon_connector = |
3451 | struct radeon_connector *radeon_connector = |
3453 | to_radeon_connector(connector); |
3452 | to_radeon_connector(connector); |
3454 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3453 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3455 | uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); |
3454 | uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); |
3456 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
3455 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
3457 | 3456 | ||
3458 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
3457 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
3459 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
3458 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
3460 | if (connected) { |
3459 | if (connected) { |
3461 | DRM_DEBUG_KMS("TV1 connected\n"); |
3460 | DRM_DEBUG_KMS("TV1 connected\n"); |
3462 | /* fix me */ |
3461 | /* fix me */ |
3463 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
3462 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
3464 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3463 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3465 | bios_5_scratch |= RADEON_TV1_ON; |
3464 | bios_5_scratch |= RADEON_TV1_ON; |
3466 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
3465 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
3467 | } else { |
3466 | } else { |
3468 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
3467 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
3469 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3468 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3470 | bios_5_scratch &= ~RADEON_TV1_ON; |
3469 | bios_5_scratch &= ~RADEON_TV1_ON; |
3471 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
3470 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
3472 | } |
3471 | } |
3473 | } |
3472 | } |
3474 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
3473 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
3475 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
3474 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
3476 | if (connected) { |
3475 | if (connected) { |
3477 | DRM_DEBUG_KMS("LCD1 connected\n"); |
3476 | DRM_DEBUG_KMS("LCD1 connected\n"); |
3478 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3477 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3479 | bios_5_scratch |= RADEON_LCD1_ON; |
3478 | bios_5_scratch |= RADEON_LCD1_ON; |
3480 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
3479 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
3481 | } else { |
3480 | } else { |
3482 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
3481 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
3483 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3482 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3484 | bios_5_scratch &= ~RADEON_LCD1_ON; |
3483 | bios_5_scratch &= ~RADEON_LCD1_ON; |
3485 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
3484 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
3486 | } |
3485 | } |
3487 | } |
3486 | } |
3488 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
3487 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
3489 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
3488 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
3490 | if (connected) { |
3489 | if (connected) { |
3491 | DRM_DEBUG_KMS("CRT1 connected\n"); |
3490 | DRM_DEBUG_KMS("CRT1 connected\n"); |
3492 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3491 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3493 | bios_5_scratch |= RADEON_CRT1_ON; |
3492 | bios_5_scratch |= RADEON_CRT1_ON; |
3494 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
3493 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
3495 | } else { |
3494 | } else { |
3496 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
3495 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
3497 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3496 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3498 | bios_5_scratch &= ~RADEON_CRT1_ON; |
3497 | bios_5_scratch &= ~RADEON_CRT1_ON; |
3499 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
3498 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
3500 | } |
3499 | } |
3501 | } |
3500 | } |
3502 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
3501 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
3503 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
3502 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
3504 | if (connected) { |
3503 | if (connected) { |
3505 | DRM_DEBUG_KMS("CRT2 connected\n"); |
3504 | DRM_DEBUG_KMS("CRT2 connected\n"); |
3506 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3505 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3507 | bios_5_scratch |= RADEON_CRT2_ON; |
3506 | bios_5_scratch |= RADEON_CRT2_ON; |
3508 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
3507 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
3509 | } else { |
3508 | } else { |
3510 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
3509 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
3511 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3510 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3512 | bios_5_scratch &= ~RADEON_CRT2_ON; |
3511 | bios_5_scratch &= ~RADEON_CRT2_ON; |
3513 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
3512 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
3514 | } |
3513 | } |
3515 | } |
3514 | } |
3516 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
3515 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
3517 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
3516 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
3518 | if (connected) { |
3517 | if (connected) { |
3519 | DRM_DEBUG_KMS("DFP1 connected\n"); |
3518 | DRM_DEBUG_KMS("DFP1 connected\n"); |
3520 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3519 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3521 | bios_5_scratch |= RADEON_DFP1_ON; |
3520 | bios_5_scratch |= RADEON_DFP1_ON; |
3522 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
3521 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
3523 | } else { |
3522 | } else { |
3524 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
3523 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
3525 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3524 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3526 | bios_5_scratch &= ~RADEON_DFP1_ON; |
3525 | bios_5_scratch &= ~RADEON_DFP1_ON; |
3527 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
3526 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
3528 | } |
3527 | } |
3529 | } |
3528 | } |
3530 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
3529 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
3531 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
3530 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
3532 | if (connected) { |
3531 | if (connected) { |
3533 | DRM_DEBUG_KMS("DFP2 connected\n"); |
3532 | DRM_DEBUG_KMS("DFP2 connected\n"); |
3534 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3533 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3535 | bios_5_scratch |= RADEON_DFP2_ON; |
3534 | bios_5_scratch |= RADEON_DFP2_ON; |
3536 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
3535 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
3537 | } else { |
3536 | } else { |
3538 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
3537 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
3539 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3538 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3540 | bios_5_scratch &= ~RADEON_DFP2_ON; |
3539 | bios_5_scratch &= ~RADEON_DFP2_ON; |
3541 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
3540 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
3542 | } |
3541 | } |
3543 | } |
3542 | } |
3544 | WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); |
3543 | WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); |
3545 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
3544 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
3546 | } |
3545 | } |
3547 | 3546 | ||
3548 | void |
3547 | void |
3549 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
3548 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
3550 | { |
3549 | { |
3551 | struct drm_device *dev = encoder->dev; |
3550 | struct drm_device *dev = encoder->dev; |
3552 | struct radeon_device *rdev = dev->dev_private; |
3551 | struct radeon_device *rdev = dev->dev_private; |
3553 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3552 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3554 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
3553 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); |
3555 | 3554 | ||
3556 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
3555 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
3557 | bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; |
3556 | bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; |
3558 | bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); |
3557 | bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); |
3559 | } |
3558 | } |
3560 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
3559 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
3561 | bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; |
3560 | bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; |
3562 | bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); |
3561 | bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); |
3563 | } |
3562 | } |
3564 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
3563 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
3565 | bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; |
3564 | bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; |
3566 | bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); |
3565 | bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); |
3567 | } |
3566 | } |
3568 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
3567 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
3569 | bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; |
3568 | bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; |
3570 | bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); |
3569 | bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); |
3571 | } |
3570 | } |
3572 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
3571 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
3573 | bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; |
3572 | bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; |
3574 | bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); |
3573 | bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); |
3575 | } |
3574 | } |
3576 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
3575 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
3577 | bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; |
3576 | bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; |
3578 | bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); |
3577 | bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); |
3579 | } |
3578 | } |
3580 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
3579 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); |
3581 | } |
3580 | } |
3582 | 3581 | ||
3583 | void |
3582 | void |
3584 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
3583 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
3585 | { |
3584 | { |
3586 | struct drm_device *dev = encoder->dev; |
3585 | struct drm_device *dev = encoder->dev; |
3587 | struct radeon_device *rdev = dev->dev_private; |
3586 | struct radeon_device *rdev = dev->dev_private; |
3588 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3587 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
3589 | uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3588 | uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
3590 | 3589 | ||
3591 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
3590 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
3592 | if (on) |
3591 | if (on) |
3593 | bios_6_scratch |= RADEON_TV_DPMS_ON; |
3592 | bios_6_scratch |= RADEON_TV_DPMS_ON; |
3594 | else |
3593 | else |
3595 | bios_6_scratch &= ~RADEON_TV_DPMS_ON; |
3594 | bios_6_scratch &= ~RADEON_TV_DPMS_ON; |
3596 | } |
3595 | } |
3597 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
3596 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
3598 | if (on) |
3597 | if (on) |
3599 | bios_6_scratch |= RADEON_CRT_DPMS_ON; |
3598 | bios_6_scratch |= RADEON_CRT_DPMS_ON; |
3600 | else |
3599 | else |
3601 | bios_6_scratch &= ~RADEON_CRT_DPMS_ON; |
3600 | bios_6_scratch &= ~RADEON_CRT_DPMS_ON; |
3602 | } |
3601 | } |
3603 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
3602 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
3604 | if (on) |
3603 | if (on) |
3605 | bios_6_scratch |= RADEON_LCD_DPMS_ON; |
3604 | bios_6_scratch |= RADEON_LCD_DPMS_ON; |
3606 | else |
3605 | else |
3607 | bios_6_scratch &= ~RADEON_LCD_DPMS_ON; |
3606 | bios_6_scratch &= ~RADEON_LCD_DPMS_ON; |
3608 | } |
3607 | } |
3609 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
3608 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
3610 | if (on) |
3609 | if (on) |
3611 | bios_6_scratch |= RADEON_DFP_DPMS_ON; |
3610 | bios_6_scratch |= RADEON_DFP_DPMS_ON; |
3612 | else |
3611 | else |
3613 | bios_6_scratch &= ~RADEON_DFP_DPMS_ON; |
3612 | bios_6_scratch &= ~RADEON_DFP_DPMS_ON; |
3614 | } |
3613 | } |
3615 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3614 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
3616 | }><>><>><>><>><>><>>>>>><>><>><>><>><>><>><>><>>><>><>>><>>>>>>>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>>><>><>><>><>>> |
3615 | }><>><>><>><>><>><>>>>>><>><>><>><>><>><>><>><>>><>><>>><>>>>>>>>>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>>><>><>><>><>>> |