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Rev 2160 Rev 2997
Line 22... Line 22...
22
 * OTHER DEALINGS IN THE SOFTWARE.
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
23
 *
24
 * Authors: Dave Airlie
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
25
 *          Alex Deucher
26
 */
26
 */
27
#include "drmP.h"
27
#include 
28
#include "radeon_drm.h"
28
#include 
29
#include "radeon.h"
29
#include "radeon.h"
30
#include "atom.h"
30
#include "atom.h"
Line 31... Line 31...
31
 
31
 
32
#ifdef CONFIG_PPC_PMAC
32
#ifdef CONFIG_PPC_PMAC
Line 618... Line 618...
618
		i2c.en_data_mask = 0x80;
618
		i2c.en_data_mask = 0x80;
619
		i2c.y_clk_mask = (0x20 << 8);
619
		i2c.y_clk_mask = (0x20 << 8);
620
		i2c.y_data_mask = 0x80;
620
		i2c.y_data_mask = 0x80;
621
	} else {
621
	} else {
622
		/* default masks for ddc pads */
622
		/* default masks for ddc pads */
623
	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
623
		i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
624
	i2c.mask_data_mask = RADEON_GPIO_EN_0;
624
		i2c.mask_data_mask = RADEON_GPIO_MASK_0;
625
	i2c.a_clk_mask = RADEON_GPIO_A_1;
625
	i2c.a_clk_mask = RADEON_GPIO_A_1;
626
	i2c.a_data_mask = RADEON_GPIO_A_0;
626
	i2c.a_data_mask = RADEON_GPIO_A_0;
627
		i2c.en_clk_mask = RADEON_GPIO_EN_1;
627
		i2c.en_clk_mask = RADEON_GPIO_EN_1;
628
		i2c.en_data_mask = RADEON_GPIO_EN_0;
628
		i2c.en_data_mask = RADEON_GPIO_EN_0;
629
		i2c.y_clk_mask = RADEON_GPIO_Y_1;
629
		i2c.y_clk_mask = RADEON_GPIO_Y_1;
Line 717... Line 717...
717
		i2c.valid = false;
717
		i2c.valid = false;
Line 718... Line 718...
718
 
718
 
719
	return i2c;
719
	return i2c;
Line -... Line 720...
-
 
720
}
-
 
721
 
-
 
722
static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
-
 
723
{
-
 
724
	struct drm_device *dev = rdev->ddev;
-
 
725
	struct radeon_i2c_bus_rec i2c;
-
 
726
	u16 offset;
-
 
727
	u8 id, blocks, clk, data;
-
 
728
	int i;
-
 
729
 
-
 
730
	i2c.valid = false;
-
 
731
 
-
 
732
	offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
-
 
733
	if (offset) {
-
 
734
		blocks = RBIOS8(offset + 2);
-
 
735
		for (i = 0; i < blocks; i++) {
-
 
736
			id = RBIOS8(offset + 3 + (i * 5) + 0);
-
 
737
			if (id == 136) {
-
 
738
				clk = RBIOS8(offset + 3 + (i * 5) + 3);
-
 
739
				data = RBIOS8(offset + 3 + (i * 5) + 4);
-
 
740
				/* gpiopad */
-
 
741
				i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
-
 
742
							    (1 << clk), (1 << data));
-
 
743
				break;
-
 
744
			}
-
 
745
		}
-
 
746
	}
-
 
747
	return i2c;
720
}
748
}
721
 
749
 
722
void radeon_combios_i2c_init(struct radeon_device *rdev)
750
void radeon_combios_i2c_init(struct radeon_device *rdev)
723
{
751
{
Line 753... Line 781...
753
	    rdev->family == CHIP_R350) {
781
	    rdev->family == CHIP_R350) {
754
		/* only 2 sw i2c pads */
782
		/* only 2 sw i2c pads */
755
	} else if (rdev->family == CHIP_RS300 ||
783
	} else if (rdev->family == CHIP_RS300 ||
756
	    rdev->family == CHIP_RS400 ||
784
	    rdev->family == CHIP_RS400 ||
757
	    rdev->family == CHIP_RS480) {
785
	    rdev->family == CHIP_RS480) {
758
		u16 offset;
-
 
759
		u8 id, blocks, clk, data;
-
 
760
		int i;
-
 
761
 
-
 
762
		/* 0x68 */
786
		/* 0x68 */
763
		i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
787
		i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
764
		rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
788
		rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
Line 765... Line -...
765
 
-
 
766
		offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
-
 
767
		if (offset) {
-
 
768
			blocks = RBIOS8(offset + 2);
-
 
769
			for (i = 0; i < blocks; i++) {
-
 
770
				id = RBIOS8(offset + 3 + (i * 5) + 0);
-
 
771
				if (id == 136) {
-
 
772
					clk = RBIOS8(offset + 3 + (i * 5) + 3);
-
 
773
					data = RBIOS8(offset + 3 + (i * 5) + 4);
789
 
774
					/* gpiopad */
790
					/* gpiopad */
775
					i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
791
		i2c = radeon_combios_get_i2c_info_from_table(rdev);
776
								    (1 << clk), (1 << data));
792
		if (i2c.valid)
777
					rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
-
 
778
					break;
-
 
779
				}
-
 
780
			}
-
 
781
		}
793
					rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
782
	} else if ((rdev->family == CHIP_R200) ||
794
	} else if ((rdev->family == CHIP_R200) ||
783
		   (rdev->family >= CHIP_R300)) {
795
		   (rdev->family >= CHIP_R300)) {
784
		/* 0x68 */
796
		/* 0x68 */
785
		i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
797
		i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
Line 1559... Line 1571...
1559
			   (rdev->pdev->device == 0x4150) &&
1571
			   (rdev->pdev->device == 0x4150) &&
1560
			   (rdev->pdev->subsystem_vendor == 0x1002) &&
1572
			   (rdev->pdev->subsystem_vendor == 0x1002) &&
1561
			   (rdev->pdev->subsystem_device == 0x4150)) {
1573
			   (rdev->pdev->subsystem_device == 0x4150)) {
1562
			/* Mac G5 tower 9600 */
1574
			/* Mac G5 tower 9600 */
1563
			rdev->mode_info.connector_table = CT_MAC_G5_9600;
1575
			rdev->mode_info.connector_table = CT_MAC_G5_9600;
-
 
1576
		} else if ((rdev->pdev->device == 0x4c66) &&
-
 
1577
			   (rdev->pdev->subsystem_vendor == 0x1002) &&
-
 
1578
			   (rdev->pdev->subsystem_device == 0x4c66)) {
-
 
1579
			/* SAM440ep RV250 embedded board */
-
 
1580
			rdev->mode_info.connector_table = CT_SAM440EP;
1564
		} else
1581
		} else
1565
#endif /* CONFIG_PPC_PMAC */
1582
#endif /* CONFIG_PPC_PMAC */
1566
#ifdef CONFIG_PPC64
1583
#ifdef CONFIG_PPC64
1567
		if (ASIC_IS_RN50(rdev))
1584
		if (ASIC_IS_RN50(rdev))
1568
			rdev->mode_info.connector_table = CT_RN50_POWER;
1585
			rdev->mode_info.connector_table = CT_RN50_POWER;
Line 2132... Line 2149...
2132
					    DRM_MODE_CONNECTOR_SVIDEO,
2149
					    DRM_MODE_CONNECTOR_SVIDEO,
2133
					    &ddc_i2c,
2150
					    &ddc_i2c,
2134
					    CONNECTOR_OBJECT_ID_SVIDEO,
2151
					    CONNECTOR_OBJECT_ID_SVIDEO,
2135
					    &hpd);
2152
					    &hpd);
2136
		break;
2153
		break;
-
 
2154
	case CT_SAM440EP:
-
 
2155
		DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
-
 
2156
			 rdev->mode_info.connector_table);
-
 
2157
		/* LVDS */
-
 
2158
		ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
-
 
2159
		hpd.hpd = RADEON_HPD_NONE;
-
 
2160
		radeon_add_legacy_encoder(dev,
-
 
2161
					  radeon_get_encoder_enum(dev,
-
 
2162
								ATOM_DEVICE_LCD1_SUPPORT,
-
 
2163
								0),
-
 
2164
					  ATOM_DEVICE_LCD1_SUPPORT);
-
 
2165
		radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
-
 
2166
					    DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
-
 
2167
					    CONNECTOR_OBJECT_ID_LVDS,
-
 
2168
					    &hpd);
-
 
2169
		/* DVI-I - secondary dac, int tmds */
-
 
2170
		ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
-
 
2171
		hpd.hpd = RADEON_HPD_1; /* ??? */
-
 
2172
		radeon_add_legacy_encoder(dev,
-
 
2173
					  radeon_get_encoder_enum(dev,
-
 
2174
								ATOM_DEVICE_DFP1_SUPPORT,
-
 
2175
								0),
-
 
2176
					  ATOM_DEVICE_DFP1_SUPPORT);
-
 
2177
		radeon_add_legacy_encoder(dev,
-
 
2178
					  radeon_get_encoder_enum(dev,
-
 
2179
								ATOM_DEVICE_CRT2_SUPPORT,
-
 
2180
								2),
-
 
2181
					  ATOM_DEVICE_CRT2_SUPPORT);
-
 
2182
		radeon_add_legacy_connector(dev, 1,
-
 
2183
					    ATOM_DEVICE_DFP1_SUPPORT |
-
 
2184
					    ATOM_DEVICE_CRT2_SUPPORT,
-
 
2185
					    DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
-
 
2186
					    CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
-
 
2187
					    &hpd);
-
 
2188
		/* VGA - primary dac */
-
 
2189
		ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
-
 
2190
		hpd.hpd = RADEON_HPD_NONE;
-
 
2191
		radeon_add_legacy_encoder(dev,
-
 
2192
					  radeon_get_encoder_enum(dev,
-
 
2193
								ATOM_DEVICE_CRT1_SUPPORT,
-
 
2194
								1),
-
 
2195
					  ATOM_DEVICE_CRT1_SUPPORT);
-
 
2196
		radeon_add_legacy_connector(dev, 2,
-
 
2197
					    ATOM_DEVICE_CRT1_SUPPORT,
-
 
2198
					    DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
-
 
2199
					    CONNECTOR_OBJECT_ID_VGA,
-
 
2200
					    &hpd);
-
 
2201
		/* TV - TV DAC */
-
 
2202
		ddc_i2c.valid = false;
-
 
2203
		hpd.hpd = RADEON_HPD_NONE;
-
 
2204
		radeon_add_legacy_encoder(dev,
-
 
2205
					  radeon_get_encoder_enum(dev,
-
 
2206
								ATOM_DEVICE_TV1_SUPPORT,
-
 
2207
								2),
-
 
2208
					  ATOM_DEVICE_TV1_SUPPORT);
-
 
2209
		radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
-
 
2210
					    DRM_MODE_CONNECTOR_SVIDEO,
-
 
2211
					    &ddc_i2c,
-
 
2212
					    CONNECTOR_OBJECT_ID_SVIDEO,
-
 
2213
					    &hpd);
-
 
2214
		break;
2137
	default:
2215
	default:
2138
		DRM_INFO("Connector table: %d (invalid)\n",
2216
		DRM_INFO("Connector table: %d (invalid)\n",
2139
			 rdev->mode_info.connector_table);
2217
			 rdev->mode_info.connector_table);
2140
		return false;
2218
		return false;
2141
	}
2219
	}
Line 2253... Line 2331...
2253
			tmp = RBIOS16(entry);
2331
			tmp = RBIOS16(entry);
Line 2254... Line 2332...
2254
 
2332
 
Line 2255... Line 2333...
2255
			connector = (tmp >> 12) & 0xf;
2333
			connector = (tmp >> 12) & 0xf;
-
 
2334
 
-
 
2335
			ddc_type = (tmp >> 8) & 0xf;
-
 
2336
			if (ddc_type == 5)
2256
 
2337
				ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
Line 2257... Line 2338...
2257
			ddc_type = (tmp >> 8) & 0xf;
2338
			else
2258
			ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2339
			ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2259
 
2340
 
Line 2561... Line 2642...
2561
 
2642
 
Line 2562... Line 2643...
2562
	rdev->pm.default_power_state_index = -1;
2643
	rdev->pm.default_power_state_index = -1;
2563
 
2644
 
2564
	/* allocate 2 power states */
2645
	/* allocate 2 power states */
-
 
2646
	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2565
	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2647
	if (rdev->pm.power_state) {
-
 
2648
		/* allocate 1 clock mode per state */
2566
	if (!rdev->pm.power_state) {
2649
		rdev->pm.power_state[0].clock_info =
2567
		rdev->pm.default_power_state_index = state_index;
-
 
2568
		rdev->pm.num_power_states = 0;
2650
			kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2569
 
2651
		rdev->pm.power_state[1].clock_info =
-
 
2652
			kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2570
		rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2653
		if (!rdev->pm.power_state[0].clock_info ||
2571
		rdev->pm.current_clock_mode_index = 0;
2654
		    !rdev->pm.power_state[1].clock_info)
-
 
2655
			goto pm_failed;
Line 2572... Line 2656...
2572
		return;
2656
	} else
2573
	}
2657
		goto pm_failed;
2574
 
2658
 
2575
	/* check for a thermal chip */
2659
	/* check for a thermal chip */
Line 2615... Line 2699...
2615
				info.addr = i2c_addr >> 1;
2699
				info.addr = i2c_addr >> 1;
2616
				strlcpy(info.type, name, sizeof(info.type));
2700
				strlcpy(info.type, name, sizeof(info.type));
2617
				i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2701
				i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2618
			}
2702
			}
2619
		}
2703
		}
-
 
2704
	} else {
-
 
2705
		/* boards with a thermal chip, but no overdrive table */
-
 
2706
 
-
 
2707
		/* Asus 9600xt has an f75375 on the monid bus */
-
 
2708
		if ((dev->pdev->device == 0x4152) &&
-
 
2709
		    (dev->pdev->subsystem_vendor == 0x1043) &&
-
 
2710
		    (dev->pdev->subsystem_device == 0xc002)) {
-
 
2711
			i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
-
 
2712
			rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
-
 
2713
			if (rdev->pm.i2c_bus) {
-
 
2714
				struct i2c_board_info info = { };
-
 
2715
				const char *name = "f75375";
-
 
2716
				info.addr = 0x28;
-
 
2717
				strlcpy(info.type, name, sizeof(info.type));
-
 
2718
				i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
-
 
2719
				DRM_INFO("Possible %s thermal controller at 0x%02x\n",
-
 
2720
					 name, info.addr);
-
 
2721
			}
-
 
2722
		}
2620
	}
2723
	}
Line 2621... Line 2724...
2621
 
2724
 
2622
	if (rdev->flags & RADEON_IS_MOBILITY) {
2725
	if (rdev->flags & RADEON_IS_MOBILITY) {
2623
		offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2726
		offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
Line 2714... Line 2817...
2714
	rdev->pm.default_power_state_index = state_index;
2817
	rdev->pm.default_power_state_index = state_index;
2715
	rdev->pm.num_power_states = state_index + 1;
2818
	rdev->pm.num_power_states = state_index + 1;
Line 2716... Line 2819...
2716
 
2819
 
2717
	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2820
	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
-
 
2821
	rdev->pm.current_clock_mode_index = 0;
-
 
2822
	return;
-
 
2823
 
-
 
2824
pm_failed:
-
 
2825
	rdev->pm.default_power_state_index = state_index;
-
 
2826
	rdev->pm.num_power_states = 0;
-
 
2827
 
-
 
2828
	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2718
	rdev->pm.current_clock_mode_index = 0;
2829
	rdev->pm.current_clock_mode_index = 0;
Line 2719... Line 2830...
2719
}
2830
}
2720
 
2831
 
2721
void radeon_external_tmds_setup(struct drm_encoder *encoder)
2832
void radeon_external_tmds_setup(struct drm_encoder *encoder)
Line 2813... Line 2924...
2813
						udelay(val);
2924
						udelay(val);
2814
						break;
2925
						break;
2815
					case 4:
2926
					case 4:
2816
						val = RBIOS16(index);
2927
						val = RBIOS16(index);
2817
						index += 2;
2928
						index += 2;
2818
						udelay(val * 1000);
2929
						mdelay(val);
2819
						break;
2930
						break;
2820
					case 6:
2931
					case 6:
2821
						slave_addr = id & 0xff;
2932
						slave_addr = id & 0xff;
2822
						slave_addr >>= 1; /* 7 bit addressing */
2933
						slave_addr >>= 1; /* 7 bit addressing */
2823
						index++;
2934
						index++;
Line 3012... Line 3123...
3012
				switch (addr) {
3123
				switch (addr) {
3013
				case 1:
3124
				case 1:
3014
					udelay(150);
3125
					udelay(150);
3015
					break;
3126
					break;
3016
				case 2:
3127
				case 2:
3017
					udelay(1000);
3128
					mdelay(1);
3018
					break;
3129
					break;
3019
				case 3:
3130
				case 3:
3020
					while (tmp--) {
3131
					while (tmp--) {
3021
						if (!
3132
						if (!
3022
						    (RREG32_PLL
3133
						    (RREG32_PLL
Line 3043... Line 3154...
3043
						    (RADEON_MCLK_CNTL);
3154
						    (RADEON_MCLK_CNTL);
3044
						mclk_cntl &= 0xffff0000;
3155
						mclk_cntl &= 0xffff0000;
3045
						/*mclk_cntl |= 0x00001111;*//* ??? */
3156
						/*mclk_cntl |= 0x00001111;*//* ??? */
3046
						WREG32_PLL(RADEON_MCLK_CNTL,
3157
						WREG32_PLL(RADEON_MCLK_CNTL,
3047
							   mclk_cntl);
3158
							   mclk_cntl);
3048
						udelay(10000);
3159
						mdelay(10);
3049
#endif
3160
#endif
3050
						WREG32_PLL
3161
						WREG32_PLL
3051
						    (RADEON_CLK_PWRMGT_CNTL,
3162
						    (RADEON_CLK_PWRMGT_CNTL,
3052
						     tmp &
3163
						     tmp &
3053
						     ~RADEON_CG_NO1_DEBUG_0);
3164
						     ~RADEON_CG_NO1_DEBUG_0);
3054
						udelay(10000);
3165
						mdelay(10);
3055
					}
3166
					}
3056
					break;
3167
					break;
3057
				default:
3168
				default:
3058
					break;
3169
					break;
3059
				}
3170
				}
Line 3206... Line 3317...
3206
 
3317
 
3207
	mem_size *= (1024 * 1024);	/* convert to bytes */
3318
	mem_size *= (1024 * 1024);	/* convert to bytes */
3208
	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3319
	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
Line 3209... Line -...
3209
}
-
 
3210
 
-
 
3211
void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
-
 
3212
{
-
 
3213
	uint16_t dyn_clk_info =
-
 
3214
	    combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
-
 
3215
 
-
 
3216
	if (dyn_clk_info)
-
 
3217
		combios_parse_pll_table(dev, dyn_clk_info);
-
 
3218
}
3320
}
3219
 
3321
 
3220
void radeon_combios_asic_init(struct drm_device *dev)
3322
void radeon_combios_asic_init(struct drm_device *dev)
3221
{
3323
{
Line 3277... Line 3379...
3277
	if (rdev->family == CHIP_RS480 &&
3379
	if (rdev->family == CHIP_RS480 &&
3278
	    rdev->pdev->subsystem_vendor == 0x103c &&
3380
	    rdev->pdev->subsystem_vendor == 0x103c &&
3279
	    rdev->pdev->subsystem_device == 0x30a4)
3381
	    rdev->pdev->subsystem_device == 0x30a4)
3280
		return;
3382
		return;
Line -... Line 3383...
-
 
3383
 
-
 
3384
	/* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
-
 
3385
	 * - it hangs on resume inside the dynclk 1 table.
-
 
3386
	 */
-
 
3387
	if (rdev->family == CHIP_RS480 &&
-
 
3388
	    rdev->pdev->subsystem_vendor == 0x103c &&
-
 
3389
	    rdev->pdev->subsystem_device == 0x30ae)
-
 
3390
		return;
3281
 
3391
 
3282
	/* DYN CLK 1 */
3392
	/* DYN CLK 1 */
3283
	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3393
	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3284
	if (table)
3394
	if (table)