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Rev 1430 Rev 1963
Line 89... Line 89...
89 
		mclk >>= 3;
 89 
		mclk >>= 3;
Line 90... Line 90...
90 
 
 90 
 
91 
	return mclk;
 91 
	return mclk;
Line -... Line 92...
- 
 
 92 
}
- 
 
 93 
 
- 
 
 94 
#ifdef CONFIG_OF
- 
 
 95 
/*
- 
 
 96 
 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
- 
 
 97 
 * tree. Hopefully, ATI OF driver is kind enough to fill these
- 
 
 98 
 */
- 
 
 99 
static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
- 
 
 100 
{
- 
 
 101 
	struct radeon_device *rdev = dev->dev_private;
- 
 
 102 
	struct device_node *dp = rdev->pdev->dev.of_node;
- 
 
 103 
	const u32 *val;
- 
 
 104 
	struct radeon_pll *p1pll = &rdev->clock.p1pll;
- 
 
 105 
	struct radeon_pll *p2pll = &rdev->clock.p2pll;
- 
 
 106 
	struct radeon_pll *spll = &rdev->clock.spll;
- 
 
 107 
	struct radeon_pll *mpll = &rdev->clock.mpll;
- 
 
 108 
 
- 
 
 109 
	if (dp == NULL)
- 
 
 110 
		return false;
- 
 
 111 
	val = of_get_property(dp, "ATY,RefCLK", NULL);
- 
 
 112 
	if (!val || !*val) {
- 
 
 113 
		printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
- 
 
 114 
		return false;
- 
 
 115 
	}
- 
 
 116 
	p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
- 
 
 117 
	p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
- 
 
 118 
	if (p1pll->reference_div < 2)
- 
 
 119 
		p1pll->reference_div = 12;
- 
 
 120 
	p2pll->reference_div = p1pll->reference_div;
- 
 
 121 
 
- 
 
 122 
	/* These aren't in the device-tree */
- 
 
 123 
	if (rdev->family >= CHIP_R420) {
- 
 
 124 
		p1pll->pll_in_min = 100;
- 
 
 125 
		p1pll->pll_in_max = 1350;
- 
 
 126 
		p1pll->pll_out_min = 20000;
- 
 
 127 
		p1pll->pll_out_max = 50000;
- 
 
 128 
		p2pll->pll_in_min = 100;
- 
 
 129 
		p2pll->pll_in_max = 1350;
- 
 
 130 
		p2pll->pll_out_min = 20000;
- 
 
 131 
		p2pll->pll_out_max = 50000;
- 
 
 132 
	} else {
- 
 
 133 
		p1pll->pll_in_min = 40;
- 
 
 134 
		p1pll->pll_in_max = 500;
- 
 
 135 
		p1pll->pll_out_min = 12500;
- 
 
 136 
		p1pll->pll_out_max = 35000;
- 
 
 137 
		p2pll->pll_in_min = 40;
- 
 
 138 
		p2pll->pll_in_max = 500;
- 
 
 139 
		p2pll->pll_out_min = 12500;
- 
 
 140 
		p2pll->pll_out_max = 35000;
- 
 
 141 
	}
- 
 
 142 
	/* not sure what the max should be in all cases */
- 
 
 143 
	rdev->clock.max_pixel_clock = 35000;
- 
 
 144 
 
- 
 
 145 
	spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
- 
 
 146 
	spll->reference_div = mpll->reference_div =
- 
 
 147 
		RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
- 
 
 148 
			    RADEON_M_SPLL_REF_DIV_MASK;
- 
 
 149 
 
- 
 
 150 
	val = of_get_property(dp, "ATY,SCLK", NULL);
- 
 
 151 
	if (val && *val)
- 
 
 152 
		rdev->clock.default_sclk = (*val) / 10;
- 
 
 153 
	else
- 
 
 154 
		rdev->clock.default_sclk =
- 
 
 155 
			radeon_legacy_get_engine_clock(rdev);
- 
 
 156 
 
- 
 
 157 
	val = of_get_property(dp, "ATY,MCLK", NULL);
- 
 
 158 
	if (val && *val)
- 
 
 159 
		rdev->clock.default_mclk = (*val) / 10;
- 
 
 160 
	else
- 
 
 161 
		rdev->clock.default_mclk =
- 
 
 162 
			radeon_legacy_get_memory_clock(rdev);
- 
 
 163 
 
- 
 
 164 
	DRM_INFO("Using device-tree clock info\n");
- 
 
 165 
 
- 
 
 166 
	return true;
- 
 
 167 
}
- 
 
 168 
#else
- 
 
 169 
static bool radeon_read_clocks_OF(struct drm_device *dev)
- 
 
 170 
{
- 
 
 171 
	return false;
- 
 
 172 
}
92 
}
 173 
#endif /* CONFIG_OF */
93 
 
 174 
 
94 
void radeon_get_clock_info(struct drm_device *dev)
 175 
void radeon_get_clock_info(struct drm_device *dev)
95 
{
 176 
{
96 
	struct radeon_device *rdev = dev->dev_private;
 177 
	struct radeon_device *rdev = dev->dev_private;
Line 103... Line 184...
103 
 
 184 
 
104 
	if (rdev->is_atom_bios)
 185 
	if (rdev->is_atom_bios)
105 
		ret = radeon_atom_get_clock_info(dev);
 186 
		ret = radeon_atom_get_clock_info(dev);
106 
	else
 187 
	else
- 
 
 188 
		ret = radeon_combios_get_clock_info(dev);
- 
 
 189 
	if (!ret)
Line 107... Line 190...
107 
		ret = radeon_combios_get_clock_info(dev);
 190 
		ret = radeon_read_clocks_OF(dev);
108 
 
 191 
 
109 
	if (ret) {
 192 
	if (ret) {
110 
		if (p1pll->reference_div < 2) {
 193 
		if (p1pll->reference_div < 2) {
Line 244... Line 327...
244 
	mpll->max_ref_div = 0xff;
 327 
	mpll->max_ref_div = 0xff;
245 
	mpll->min_feedback_div = 4;
 328 
	mpll->min_feedback_div = 4;
246 
	mpll->max_feedback_div = 0xff;
 329 
	mpll->max_feedback_div = 0xff;
247 
	mpll->best_vco = 0;
 330 
	mpll->best_vco = 0;
Line -... Line 331...
- 
 
 331 
 
- 
 
 332 
	if (!rdev->clock.default_sclk)
- 
 
 333 
		rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
- 
 
 334 
	if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
- 
 
 335 
		rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
- 
 
 336 
 
- 
 
 337 
	rdev->pm.current_sclk = rdev->clock.default_sclk;
- 
 
 338 
	rdev->pm.current_mclk = rdev->clock.default_mclk;
248 
 
 339 
 
Line 249... Line 340...
249 
}
 340 
}
250 
 
 341 
 
251 
/* 10 khz */
 342 
/* 10 khz */
Line 814... Line 905...
814 
			WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 905 
			WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
815 
		}
 906 
		}
816 
	}
 907 
	}
817 
}
 908 
}
Line 818... Line -...
818 
 
 - 
 
819 
static void radeon_apply_clock_quirks(struct radeon_device *rdev)
 - 
 
820 
{
 - 
 
821 
	uint32_t tmp;
 - 
 
822 
 
 - 
 
823 
	/* XXX make sure engine is idle */
 - 
 
824 
 
 - 
 
825 
	if (rdev->family < CHIP_RS600) {
 - 
 
826 
		tmp = RREG32_PLL(RADEON_SCLK_CNTL);
 - 
 
827 
		if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
 - 
 
828 
			tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
 - 
 
829 
		if ((rdev->family == CHIP_RV250)
 - 
 
830 
		    || (rdev->family == CHIP_RV280))
 - 
 
831 
			tmp |=
 - 
 
832 
			    RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
 - 
 
833 
		if ((rdev->family == CHIP_RV350)
 - 
 
834 
		    || (rdev->family == CHIP_RV380))
 - 
 
835 
			tmp |= R300_SCLK_FORCE_VAP;
 - 
 
836 
		if (rdev->family == CHIP_R420)
 - 
 
837 
			tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
 - 
 
838 
		WREG32_PLL(RADEON_SCLK_CNTL, tmp);
 - 
 
839 
	} else if (rdev->family < CHIP_R600) {
 - 
 
840 
		tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
 - 
 
841 
		tmp |= AVIVO_CP_FORCEON;
 - 
 
842 
		WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
 - 
 
843 
 
 - 
 
844 
		tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
 - 
 
845 
		tmp |= AVIVO_E2_FORCEON;
 - 
 
846 
		WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
 - 
 
847 
 
 - 
 
848 
		tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
 - 
 
849 
		tmp |= AVIVO_IDCT_FORCEON;
 - 
 
850 
		WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
 - 
 
851 
	}
 - 
 
852 
}
 - 
 
853 
 
 - 
 
854 
int radeon_static_clocks_init(struct drm_device *dev)
 - 
 
855 
{
 - 
 
856 
	struct radeon_device *rdev = dev->dev_private;
 - 
 
857 
 
 - 
 
858 
	/* XXX make sure engine is idle */
 - 
 
859 
 
 - 
 
860 
	if (radeon_dynclks != -1) {
 - 
 
861 
		if (radeon_dynclks) {
 - 
 
862 
			if (rdev->asic->set_clock_gating)
 - 
 
863 
			radeon_set_clock_gating(rdev, 1);
 - 
 
864 
		}
 - 
 
865 
	}
 - 
 
866 
	radeon_apply_clock_quirks(rdev);
 - 
 
867 
	return 0;
 -