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Rev 1268 Rev 1321
Line 42... Line 42...
42 
	fb_div <<= 1;
 42 
	fb_div <<= 1;
43 
	fb_div *= spll->reference_freq;
 43 
	fb_div *= spll->reference_freq;
Line 44... Line 44...
44 
 
 44 
 
45 
	ref_div =
 45 
	ref_div =
- 
 
 46 
	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
- 
 
 47 
 
- 
 
 48 
	if (ref_div == 0)
- 
 
 49 
		return 0;
46 
	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
 50 
 
Line 47... Line 51...
47 
	sclk = fb_div / ref_div;
 51 
	sclk = fb_div / ref_div;
48 
 
 52 
 
49 
	post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
 53 
	post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
Line 68... Line 72...
68 
	fb_div <<= 1;
 72 
	fb_div <<= 1;
69 
	fb_div *= mpll->reference_freq;
 73 
	fb_div *= mpll->reference_freq;
Line 70... Line 74...
70 
 
 74 
 
71 
	ref_div =
 75 
	ref_div =
- 
 
 76 
	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
- 
 
 77 
 
- 
 
 78 
	if (ref_div == 0)
- 
 
 79 
		return 0;
72 
	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
 80 
 
Line 73... Line 81...
73 
	mclk = fb_div / ref_div;
 81 
	mclk = fb_div / ref_div;
74 
 
 82 
 
75 
	post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
 83 
	post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
Line 96... Line 104...
96 
		ret = radeon_atom_get_clock_info(dev);
 104 
		ret = radeon_atom_get_clock_info(dev);
97 
	else
 105 
	else
98 
		ret = radeon_combios_get_clock_info(dev);
 106 
		ret = radeon_combios_get_clock_info(dev);
Line 99... Line 107...
99 
 
 107 
 
- 
 
 108 
	if (ret) {
- 
 
 109 
		if (p1pll->reference_div < 2) {
- 
 
 110 
			if (!ASIC_IS_AVIVO(rdev)) {
- 
 
 111 
				u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
- 
 
 112 
				if (ASIC_IS_R300(rdev))
- 
 
 113 
					p1pll->reference_div =
- 
 
 114 
						(tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
- 
 
 115 
				else
100 
	if (ret) {
 116 
					p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
101 
		if (p1pll->reference_div < 2)
 117 
		if (p1pll->reference_div < 2)
- 
 
 118 
			p1pll->reference_div = 12;
- 
 
 119 
			} else
- 
 
 120 
				p1pll->reference_div = 12;
102 
			p1pll->reference_div = 12;
 121 
		}
103 
		if (p2pll->reference_div < 2)
 122 
		if (p2pll->reference_div < 2)
104 
			p2pll->reference_div = 12;
 123 
			p2pll->reference_div = 12;
105 
		if (rdev->family < CHIP_RS600) {
 124 
		if (rdev->family < CHIP_RS600) {
106 
		if (spll->reference_div < 2)
 125 
		if (spll->reference_div < 2)