Rev 1179 | Rev 1268 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1179 | Rev 1221 | ||
|---|---|---|---|
| Line 409... | Line 409... | ||
| 409 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
409 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 410 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
410 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 411 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
411 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 412 | R300_PIXCLK_TVO_ALWAYS_ONb | |
412 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 413 | R300_P2G2CLK_ALWAYS_ONb | |
413 | R300_P2G2CLK_ALWAYS_ONb | |
| 414 | R300_P2G2CLK_ALWAYS_ONb); |
414 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
| 415 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
415 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 416 | } else if (rdev->family >= CHIP_RV350) { |
416 | } else if (rdev->family >= CHIP_RV350) { |
| 417 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
417 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 418 | tmp &= ~(R300_SCLK_FORCE_TCL | |
418 | tmp &= ~(R300_SCLK_FORCE_TCL | |
| 419 | R300_SCLK_FORCE_GA | |
419 | R300_SCLK_FORCE_GA | |
| Line 462... | Line 462... | ||
| 462 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
462 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 463 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
463 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 464 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
464 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 465 | R300_PIXCLK_TVO_ALWAYS_ONb | |
465 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 466 | R300_P2G2CLK_ALWAYS_ONb | |
466 | R300_P2G2CLK_ALWAYS_ONb | |
| 467 | R300_P2G2CLK_ALWAYS_ONb); |
467 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
| 468 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
468 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| Line 469... | Line 469... | ||
| 469 | 469 | ||
| 470 | tmp = RREG32_PLL(RADEON_MCLK_MISC); |
470 | tmp = RREG32_PLL(RADEON_MCLK_MISC); |
| 471 | tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
471 | tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
| Line 652... | Line 652... | ||
| 652 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
652 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 653 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
653 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 654 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
654 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 655 | R300_PIXCLK_TVO_ALWAYS_ONb | |
655 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 656 | R300_P2G2CLK_ALWAYS_ONb | |
656 | R300_P2G2CLK_ALWAYS_ONb | |
| 657 | R300_P2G2CLK_ALWAYS_ONb | |
657 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
| 658 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
658 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 659 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
659 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 660 | } else if (rdev->family >= CHIP_RV350) { |
660 | } else if (rdev->family >= CHIP_RV350) { |
| 661 | /* for RV350/M10, no delays are required. */ |
661 | /* for RV350/M10, no delays are required. */ |
| 662 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
662 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| Line 703... | Line 703... | ||
| 703 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
703 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| 704 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
704 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| 705 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
705 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
| 706 | R300_PIXCLK_TVO_ALWAYS_ONb | |
706 | R300_PIXCLK_TVO_ALWAYS_ONb | |
| 707 | R300_P2G2CLK_ALWAYS_ONb | |
707 | R300_P2G2CLK_ALWAYS_ONb | |
| 708 | R300_P2G2CLK_ALWAYS_ONb | |
708 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
| 709 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
709 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| 710 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
710 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 711 | } else { |
711 | } else { |
| 712 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
712 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| 713 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |
713 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |