WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_bios.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
 
#include 
#include 
/*
 * BIOS.
 */
 
/* If you boot an IGP board with a discrete card as the primary,
 * the IGP rom is not accessible via the rom bar as the IGP rom is
 * part of the system bios.  On boot, the system bios puts a
 * copy of the igp rom at the start of vram if a discrete card is
 * present.
 */
static bool igp_read_bios_from_vram(struct radeon_device *rdev)
{
	uint8_t __iomem *bios;
	resource_size_t vram_base;
	resource_size_t size = 256 * 1024; /* ??? */
 
	if (!(rdev->flags & RADEON_IS_IGP))
		if (!radeon_card_posted(rdev))
			return false;
 
	rdev->bios = NULL;
	vram_base = pci_resource_start(rdev->pdev, 0);
	bios = ioremap(vram_base, size);
	if (!bios) {
		return false;
	}
 
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
		iounmap(bios);
		return false;
	}
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (rdev->bios == NULL) {
		iounmap(bios);
		return false;
	}
	memcpy(rdev->bios, bios, size);
	iounmap(bios);
	return true;
}
 
static bool radeon_read_bios(struct radeon_device *rdev)
{
	uint8_t __iomem *bios, val1, val2;
	size_t size;
 
	rdev->bios = NULL;
	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
	bios = pci_map_rom(rdev->pdev, &size);
	if (!bios) {
		return false;
	}
 
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
//       pci_unmap_rom(rdev->pdev, bios);
		return false;
	}
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (rdev->bios == NULL) {
		return false;
	}
	memcpy(rdev->bios, bios, size);
	return true;
}
 
#ifdef CONFIG_ACPI
/* ATRM is used to get the BIOS on the discrete cards in
 * dual-gpu systems.
 */
/* retrieve the ROM in 4k blocks */
#define ATRM_BIOS_PAGE 4096
/**
 * radeon_atrm_call - fetch a chunk of the vbios
 *
 * @atrm_handle: acpi ATRM handle
 * @bios: vbios image pointer
 * @offset: offset of vbios image data to fetch
 * @len: length of vbios image data to fetch
 *
 * Executes ATRM to fetch a chunk of the discrete
 * vbios image on PX systems (all asics).
 * Returns the length of the buffer fetched.
 */
static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
			    int offset, int len)
{
	acpi_status status;
	union acpi_object atrm_arg_elements[2], *obj;
	struct acpi_object_list atrm_arg;
	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 
	atrm_arg.count = 2;
	atrm_arg.pointer = &atrm_arg_elements[0];
 
	atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
	atrm_arg_elements[0].integer.value = offset;
 
	atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
	atrm_arg_elements[1].integer.value = len;
 
	status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
	if (ACPI_FAILURE(status)) {
		printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
		return -ENODEV;
	}
 
	obj = (union acpi_object *)buffer.pointer;
	memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
	len = obj->buffer.length;
	kfree(buffer.pointer);
	return len;
}
 
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
{
	int ret;
	int size = 256 * 1024;
	int i;
	struct pci_dev *pdev = NULL;
	acpi_handle dhandle, atrm_handle;
	acpi_status status;
	bool found = false;
 
	/* ATRM is for the discrete card only */
	if (rdev->flags & RADEON_IS_IGP)
		return false;
 
	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
		dhandle = ACPI_HANDLE(&pdev->dev);
		if (!dhandle)
			continue;
 
		status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
		if (!ACPI_FAILURE(status)) {
			found = true;
			break;
		}
	}
 
	if (!found)
		return false;
 
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (!rdev->bios) {
		DRM_ERROR("Unable to allocate bios\n");
		return false;
	}
 
	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
		ret = radeon_atrm_call(atrm_handle,
				       rdev->bios,
				       (i * ATRM_BIOS_PAGE),
				       ATRM_BIOS_PAGE);
		if (ret < ATRM_BIOS_PAGE)
			break;
	}
 
	if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
		kfree(rdev->bios);
		return false;
	}
	return true;
}
#else
static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
{
	return false;
}
#endif
 
static bool ni_read_disabled_bios(struct radeon_device *rdev)
{
	u32 bus_cntl;
	u32 d1vga_control;
	u32 d2vga_control;
	u32 vga_render_control;
	u32 rom_cntl;
	bool r;
 
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
 
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	if (!ASIC_IS_NODCE(rdev)) {
		/* Disable VGA mode */
		WREG32(AVIVO_D1VGA_CONTROL,
		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
		WREG32(AVIVO_D2VGA_CONTROL,
		       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
		WREG32(AVIVO_VGA_RENDER_CONTROL,
		       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
	}
	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(R600_BUS_CNTL, bus_cntl);
	if (!ASIC_IS_NODCE(rdev)) {
		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
		WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	}
	WREG32(R600_ROM_CNTL, rom_cntl);
	return r;
}
 
static bool r700_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t rom_cntl;
	uint32_t cg_spll_func_cntl = 0;
	uint32_t cg_spll_status;
	bool r;
 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	if (rdev->family == CHIP_RV730) {
		cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 
		/* enable bypass mode */
		WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
						R600_SPLL_BYPASS_EN));
 
		/* wait for SPLL_CHG_STATUS to change to 1 */
		cg_spll_status = 0;
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 
		WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
	} else
		WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	if (rdev->family == CHIP_RV730) {
		WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 
		/* wait for SPLL_CHG_STATUS to change to 1 */
		cg_spll_status = 0;
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
	}
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(R600_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(R600_ROM_CNTL, rom_cntl);
	return r;
}
 
static bool r600_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t rom_cntl;
	uint32_t general_pwrmgt;
	uint32_t low_vid_lower_gpio_cntl;
	uint32_t medium_vid_lower_gpio_cntl;
	uint32_t high_vid_lower_gpio_cntl;
	uint32_t ctxsw_vid_lower_gpio_cntl;
	uint32_t lower_gpio_enable;
	bool r;
 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	WREG32(R600_ROM_CNTL,
	       ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
		(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
		R600_SCK_OVERWRITE));
 
	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
	       (low_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
	       (medium_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
	       (high_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
	       (ctxsw_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(R600_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(R600_ROM_CNTL, rom_cntl);
	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
	return r;
}
 
static bool avivo_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t seprom_cntl1;
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t gpiopad_a;
	uint32_t gpiopad_en;
	uint32_t gpiopad_mask;
	bool r;
 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(RV370_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 
	WREG32(RADEON_SEPROM_CNTL1,
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
	WREG32(RADEON_GPIOPAD_A, 0);
	WREG32(RADEON_GPIOPAD_EN, 0);
	WREG32(RADEON_GPIOPAD_MASK, 0);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
	/* enable the rom */
	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(RV370_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
	return r;
}
 
static bool legacy_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t seprom_cntl1;
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t crtc_gen_cntl;
	uint32_t crtc2_gen_cntl;
	uint32_t crtc_ext_cntl;
	uint32_t fp2_gen_cntl;
	bool r;
 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	if (rdev->flags & RADEON_IS_PCIE)
		bus_cntl = RREG32(RV370_BUS_CNTL);
	else
		bus_cntl = RREG32(RADEON_BUS_CNTL);
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
	crtc2_gen_cntl = 0;
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
	fp2_gen_cntl = 0;
 
	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
	}
 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
	}
 
	WREG32(RADEON_SEPROM_CNTL1,
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
	/* enable the rom */
	if (rdev->flags & RADEON_IS_PCIE)
		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
	else
		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
	/* Turn off mem requests and CRTC for both controllers */
	WREG32(RADEON_CRTC_GEN_CNTL,
	       ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
		(RADEON_CRTC_DISP_REQ_EN_B |
		 RADEON_CRTC_EXT_DISP_EN)));
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(RADEON_CRTC2_GEN_CNTL,
		       ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
			RADEON_CRTC2_DISP_REQ_EN_B));
	}
	/* Turn off CRTC */
	WREG32(RADEON_CRTC_EXT_CNTL,
	       ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
		(RADEON_CRTC_SYNC_TRISTAT |
		 RADEON_CRTC_DISPLAY_DIS)));
 
	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
	}
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	if (rdev->flags & RADEON_IS_PCIE)
		WREG32(RV370_BUS_CNTL, bus_cntl);
	else
		WREG32(RADEON_BUS_CNTL, bus_cntl);
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	}
	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
	}
	return r;
}
 
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
{
	if (rdev->flags & RADEON_IS_IGP)
		return igp_read_bios_from_vram(rdev);
	else if (rdev->family >= CHIP_BARTS)
		return ni_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_RV770)
		return r700_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_R600)
		return r600_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_RS600)
		return avivo_read_disabled_bios(rdev);
	else
		return legacy_read_disabled_bios(rdev);
}
 
#ifdef CONFIG_ACPI
static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
{
	bool ret = false;
	struct acpi_table_header *hdr;
	acpi_size tbl_size;
	UEFI_ACPI_VFCT *vfct;
	GOP_VBIOS_CONTENT *vbios;
	VFCT_IMAGE_HEADER *vhdr;
 
	if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
		return false;
	if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
		DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
		goto out_unmap;
	}
 
	vfct = (UEFI_ACPI_VFCT *)hdr;
	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
		DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
		goto out_unmap;
	}
 
	vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
	vhdr = &vbios->VbiosHeader;
	DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
			vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
			vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 
	if (vhdr->PCIBus != rdev->pdev->bus->number ||
	    vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
	    vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
	    vhdr->VendorID != rdev->pdev->vendor ||
	    vhdr->DeviceID != rdev->pdev->device) {
		DRM_INFO("ACPI VFCT table is not for this card\n");
		goto out_unmap;
	}
 
	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
		DRM_ERROR("ACPI VFCT image truncated\n");
		goto out_unmap;
	}
 
	rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
	ret = !!rdev->bios;
 
out_unmap:
	return ret;
}
#else
static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
{
	return false;
}
#endif
 
bool radeon_get_bios(struct radeon_device *rdev)
{
	bool r;
	uint16_t tmp;
 
	r = radeon_atrm_get_bios(rdev);
	if (r == false)
		r = radeon_acpi_vfct_bios(rdev);
	if (r == false)
		r = igp_read_bios_from_vram(rdev);
    if (r == false)
        r = radeon_read_bios(rdev);
	if (r == false) {
		r = radeon_read_disabled_bios(rdev);
	}
	if (r == false || rdev->bios == NULL) {
		DRM_ERROR("Unable to locate a BIOS ROM\n");
		rdev->bios = NULL;
		return false;
	}
	if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
		printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
		goto free_bios;
	}
 
	tmp = RBIOS16(0x18);
	if (RBIOS8(tmp + 0x14) != 0x0) {
		DRM_INFO("Not an x86 BIOS ROM, not using.\n");
		goto free_bios;
	}
 
	rdev->bios_header_start = RBIOS16(0x48);
	if (!rdev->bios_header_start) {
		goto free_bios;
	}
	tmp = rdev->bios_header_start + 4;
	if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
	    !memcmp(rdev->bios + tmp, "MOTA", 4)) {
		rdev->is_atom_bios = true;
	} else {
		rdev->is_atom_bios = false;
	}
 
	DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
	return true;
free_bios:
	kfree(rdev->bios);
	rdev->bios = NULL;
	return false;
}

Rev 6104	Rev 7146
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include "radeon_reg.h"	29	#include "radeon_reg.h"
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "atom.h"	31	#include "atom.h"
32		32
33	#include	33	#include
-		34	#include
34	/*	35	/*
35	* BIOS.	36	* BIOS.
36	*/	37	*/
37		38
38	/* If you boot an IGP board with a discrete card as the primary,	39	/* If you boot an IGP board with a discrete card as the primary,
39	* the IGP rom is not accessible via the rom bar as the IGP rom is	40	* the IGP rom is not accessible via the rom bar as the IGP rom is
40	* part of the system bios. On boot, the system bios puts a	41	* part of the system bios. On boot, the system bios puts a
41	* copy of the igp rom at the start of vram if a discrete card is	42	* copy of the igp rom at the start of vram if a discrete card is
42	* present.	43	* present.
43	*/	44	*/
44	static bool igp_read_bios_from_vram(struct radeon_device *rdev)	45	static bool igp_read_bios_from_vram(struct radeon_device *rdev)
45	{	46	{
46	uint8_t __iomem *bios;	47	uint8_t __iomem *bios;
47	resource_size_t vram_base;	48	resource_size_t vram_base;
48	resource_size_t size = 256 * 1024; /* ??? */	49	resource_size_t size = 256 * 1024; /* ??? */
49		50
50	if (!(rdev->flags & RADEON_IS_IGP))	51	if (!(rdev->flags & RADEON_IS_IGP))
51	if (!radeon_card_posted(rdev))	52	if (!radeon_card_posted(rdev))
52	return false;	53	return false;
53		54
54	rdev->bios = NULL;	55	rdev->bios = NULL;
55	vram_base = pci_resource_start(rdev->pdev, 0);	56	vram_base = pci_resource_start(rdev->pdev, 0);
56	bios = ioremap(vram_base, size);	57	bios = ioremap(vram_base, size);
57	if (!bios) {	58	if (!bios) {
58	return false;	59	return false;
59	}	60	}
60		61
61	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {	62	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {
62	iounmap(bios);	63	iounmap(bios);
63	return false;	64	return false;
64	}	65	}
65	rdev->bios = kmalloc(size, GFP_KERNEL);	66	rdev->bios = kmalloc(size, GFP_KERNEL);
66	if (rdev->bios == NULL) {	67	if (rdev->bios == NULL) {
67	iounmap(bios);	68	iounmap(bios);
68	return false;	69	return false;
69	}	70	}
70	memcpy(rdev->bios, bios, size);	71	memcpy(rdev->bios, bios, size);
71	iounmap(bios);	72	iounmap(bios);
72	return true;	73	return true;
73	}	74	}
74		75
75	static bool radeon_read_bios(struct radeon_device *rdev)	76	static bool radeon_read_bios(struct radeon_device *rdev)
76	{	77	{
77	uint8_t __iomem *bios, val1, val2;	78	uint8_t __iomem *bios, val1, val2;
78	size_t size;	79	size_t size;
79		80
80	rdev->bios = NULL;	81	rdev->bios = NULL;
81	/* XXX: some cards may return 0 for rom size? ddx has a workaround */	82	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
82	bios = pci_map_rom(rdev->pdev, &size);	83	bios = pci_map_rom(rdev->pdev, &size);
83	if (!bios) {	84	if (!bios) {
84	return false;	85	return false;
85	}	86	}
86		87
87	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {	88	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {
88	// pci_unmap_rom(rdev->pdev, bios);	89	// pci_unmap_rom(rdev->pdev, bios);
89	return false;	90	return false;
90	}	91	}
91	rdev->bios = kmalloc(size, GFP_KERNEL);	92	rdev->bios = kmalloc(size, GFP_KERNEL);
92	if (rdev->bios == NULL) {	93	if (rdev->bios == NULL) {
93	return false;	94	return false;
94	}	95	}
95	memcpy(rdev->bios, bios, size);	96	memcpy(rdev->bios, bios, size);
96	return true;	97	return true;
97	}	98	}
98		99
99	#ifdef CONFIG_ACPI	100	#ifdef CONFIG_ACPI
100	/* ATRM is used to get the BIOS on the discrete cards in	101	/* ATRM is used to get the BIOS on the discrete cards in
101	* dual-gpu systems.	102	* dual-gpu systems.
102	*/	103	*/
103	/* retrieve the ROM in 4k blocks */	104	/* retrieve the ROM in 4k blocks */
104	#define ATRM_BIOS_PAGE 4096	105	#define ATRM_BIOS_PAGE 4096
105	/**	106	/**
106	* radeon_atrm_call - fetch a chunk of the vbios	107	* radeon_atrm_call - fetch a chunk of the vbios
107	*	108	*
108	* @atrm_handle: acpi ATRM handle	109	* @atrm_handle: acpi ATRM handle
109	* @bios: vbios image pointer	110	* @bios: vbios image pointer
110	* @offset: offset of vbios image data to fetch	111	* @offset: offset of vbios image data to fetch
111	* @len: length of vbios image data to fetch	112	* @len: length of vbios image data to fetch
112	*	113	*
113	* Executes ATRM to fetch a chunk of the discrete	114	* Executes ATRM to fetch a chunk of the discrete
114	* vbios image on PX systems (all asics).	115	* vbios image on PX systems (all asics).
115	* Returns the length of the buffer fetched.	116	* Returns the length of the buffer fetched.
116	*/	117	*/
117	static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,	118	static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
118	int offset, int len)	119	int offset, int len)
119	{	120	{
120	acpi_status status;	121	acpi_status status;
121	union acpi_object atrm_arg_elements[2], *obj;	122	union acpi_object atrm_arg_elements[2], *obj;
122	struct acpi_object_list atrm_arg;	123	struct acpi_object_list atrm_arg;
123	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};	124	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
124		125
125	atrm_arg.count = 2;	126	atrm_arg.count = 2;
126	atrm_arg.pointer = &atrm_arg_elements[0];	127	atrm_arg.pointer = &atrm_arg_elements[0];
127		128
128	atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;	129	atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
129	atrm_arg_elements[0].integer.value = offset;	130	atrm_arg_elements[0].integer.value = offset;
130		131
131	atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;	132	atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
132	atrm_arg_elements[1].integer.value = len;	133	atrm_arg_elements[1].integer.value = len;
133		134
134	status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);	135	status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
135	if (ACPI_FAILURE(status)) {	136	if (ACPI_FAILURE(status)) {
136	printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));	137	printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
137	return -ENODEV;	138	return -ENODEV;
138	}	139	}
139		140
140	obj = (union acpi_object *)buffer.pointer;	141	obj = (union acpi_object *)buffer.pointer;
141	memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);	142	memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
142	len = obj->buffer.length;	143	len = obj->buffer.length;
143	kfree(buffer.pointer);	144	kfree(buffer.pointer);
144	return len;	145	return len;
145	}	146	}
146		147
147	static bool radeon_atrm_get_bios(struct radeon_device *rdev)	148	static bool radeon_atrm_get_bios(struct radeon_device *rdev)
148	{	149	{
149	int ret;	150	int ret;
150	int size = 256 * 1024;	151	int size = 256 * 1024;
151	int i;	152	int i;
152	struct pci_dev *pdev = NULL;	153	struct pci_dev *pdev = NULL;
153	acpi_handle dhandle, atrm_handle;	154	acpi_handle dhandle, atrm_handle;
154	acpi_status status;	155	acpi_status status;
155	bool found = false;	156	bool found = false;
156		157
157	/* ATRM is for the discrete card only */	158	/* ATRM is for the discrete card only */
158	if (rdev->flags & RADEON_IS_IGP)	159	if (rdev->flags & RADEON_IS_IGP)
159	return false;	160	return false;
160		161
161	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {	162	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
162	dhandle = ACPI_HANDLE(&pdev->dev);	163	dhandle = ACPI_HANDLE(&pdev->dev);
163	if (!dhandle)	164	if (!dhandle)
164	continue;	165	continue;
165		166
166	status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);	167	status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
167	if (!ACPI_FAILURE(status)) {	168	if (!ACPI_FAILURE(status)) {
168	found = true;	169	found = true;
169	break;	170	break;
170	}	171	}
171	}	172	}
172		173
173	if (!found)	174	if (!found)
174	return false;	175	return false;
175		176
176	rdev->bios = kmalloc(size, GFP_KERNEL);	177	rdev->bios = kmalloc(size, GFP_KERNEL);
177	if (!rdev->bios) {	178	if (!rdev->bios) {
178	DRM_ERROR("Unable to allocate bios\n");	179	DRM_ERROR("Unable to allocate bios\n");
179	return false;	180	return false;
180	}	181	}
181		182
182	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {	183	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
183	ret = radeon_atrm_call(atrm_handle,	184	ret = radeon_atrm_call(atrm_handle,
184	rdev->bios,	185	rdev->bios,
185	(i * ATRM_BIOS_PAGE),	186	(i * ATRM_BIOS_PAGE),
186	ATRM_BIOS_PAGE);	187	ATRM_BIOS_PAGE);
187	if (ret < ATRM_BIOS_PAGE)	188	if (ret < ATRM_BIOS_PAGE)
188	break;	189	break;
189	}	190	}
190		191
191	if (i == 0 \|\| rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {	192	if (i == 0 \|\| rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {
192	kfree(rdev->bios);	193	kfree(rdev->bios);
193	return false;	194	return false;
194	}	195	}
195	return true;	196	return true;
196	}	197	}
197	#else	198	#else
198	static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)	199	static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
199	{	200	{
200	return false;	201	return false;
201	}	202	}
202	#endif	203	#endif
203		204
204	static bool ni_read_disabled_bios(struct radeon_device *rdev)	205	static bool ni_read_disabled_bios(struct radeon_device *rdev)
205	{	206	{
206	u32 bus_cntl;	207	u32 bus_cntl;
207	u32 d1vga_control;	208	u32 d1vga_control;
208	u32 d2vga_control;	209	u32 d2vga_control;
209	u32 vga_render_control;	210	u32 vga_render_control;
210	u32 rom_cntl;	211	u32 rom_cntl;
211	bool r;	212	bool r;
212		213
213	bus_cntl = RREG32(R600_BUS_CNTL);	214	bus_cntl = RREG32(R600_BUS_CNTL);
214	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	215	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
215	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	216	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
216	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	217	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
217	rom_cntl = RREG32(R600_ROM_CNTL);	218	rom_cntl = RREG32(R600_ROM_CNTL);
218		219
219	/* enable the rom */	220	/* enable the rom */
220	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));	221	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
221	if (!ASIC_IS_NODCE(rdev)) {	222	if (!ASIC_IS_NODCE(rdev)) {
222	/* Disable VGA mode */	223	/* Disable VGA mode */
223	WREG32(AVIVO_D1VGA_CONTROL,	224	WREG32(AVIVO_D1VGA_CONTROL,
224	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	225	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
225	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	226	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
226	WREG32(AVIVO_D2VGA_CONTROL,	227	WREG32(AVIVO_D2VGA_CONTROL,
227	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	228	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
228	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	229	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
229	WREG32(AVIVO_VGA_RENDER_CONTROL,	230	WREG32(AVIVO_VGA_RENDER_CONTROL,
230	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	231	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
231	}	232	}
232	WREG32(R600_ROM_CNTL, rom_cntl \| R600_SCK_OVERWRITE);	233	WREG32(R600_ROM_CNTL, rom_cntl \| R600_SCK_OVERWRITE);
233		234
234	r = radeon_read_bios(rdev);	235	r = radeon_read_bios(rdev);
235		236
236	/* restore regs */	237	/* restore regs */
237	WREG32(R600_BUS_CNTL, bus_cntl);	238	WREG32(R600_BUS_CNTL, bus_cntl);
238	if (!ASIC_IS_NODCE(rdev)) {	239	if (!ASIC_IS_NODCE(rdev)) {
239	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	240	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
240	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	241	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
241	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	242	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
242	}	243	}
243	WREG32(R600_ROM_CNTL, rom_cntl);	244	WREG32(R600_ROM_CNTL, rom_cntl);
244	return r;	245	return r;
245	}	246	}
246		247
247	static bool r700_read_disabled_bios(struct radeon_device *rdev)	248	static bool r700_read_disabled_bios(struct radeon_device *rdev)
248	{	249	{
249	uint32_t viph_control;	250	uint32_t viph_control;
250	uint32_t bus_cntl;	251	uint32_t bus_cntl;
251	uint32_t d1vga_control;	252	uint32_t d1vga_control;
252	uint32_t d2vga_control;	253	uint32_t d2vga_control;
253	uint32_t vga_render_control;	254	uint32_t vga_render_control;
254	uint32_t rom_cntl;	255	uint32_t rom_cntl;
255	uint32_t cg_spll_func_cntl = 0;	256	uint32_t cg_spll_func_cntl = 0;
256	uint32_t cg_spll_status;	257	uint32_t cg_spll_status;
257	bool r;	258	bool r;
258		259
259	viph_control = RREG32(RADEON_VIPH_CONTROL);	260	viph_control = RREG32(RADEON_VIPH_CONTROL);
260	bus_cntl = RREG32(R600_BUS_CNTL);	261	bus_cntl = RREG32(R600_BUS_CNTL);
261	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	262	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
262	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	263	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
263	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	264	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
264	rom_cntl = RREG32(R600_ROM_CNTL);	265	rom_cntl = RREG32(R600_ROM_CNTL);
265		266
266	/* disable VIP */	267	/* disable VIP */
267	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	268	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
268	/* enable the rom */	269	/* enable the rom */
269	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));	270	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
270	/* Disable VGA mode */	271	/* Disable VGA mode */
271	WREG32(AVIVO_D1VGA_CONTROL,	272	WREG32(AVIVO_D1VGA_CONTROL,
272	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	273	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
273	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	274	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
274	WREG32(AVIVO_D2VGA_CONTROL,	275	WREG32(AVIVO_D2VGA_CONTROL,
275	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	276	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
276	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	277	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
277	WREG32(AVIVO_VGA_RENDER_CONTROL,	278	WREG32(AVIVO_VGA_RENDER_CONTROL,
278	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	279	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
279		280
280	if (rdev->family == CHIP_RV730) {	281	if (rdev->family == CHIP_RV730) {
281	cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);	282	cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
282		283
283	/* enable bypass mode */	284	/* enable bypass mode */
284	WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl \|	285	WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl \|
285	R600_SPLL_BYPASS_EN));	286	R600_SPLL_BYPASS_EN));
286		287
287	/* wait for SPLL_CHG_STATUS to change to 1 */	288	/* wait for SPLL_CHG_STATUS to change to 1 */
288	cg_spll_status = 0;	289	cg_spll_status = 0;
289	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))	290	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
290	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);	291	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
291		292
292	WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));	293	WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
293	} else	294	} else
294	WREG32(R600_ROM_CNTL, (rom_cntl \| R600_SCK_OVERWRITE));	295	WREG32(R600_ROM_CNTL, (rom_cntl \| R600_SCK_OVERWRITE));
295		296
296	r = radeon_read_bios(rdev);	297	r = radeon_read_bios(rdev);
297		298
298	/* restore regs */	299	/* restore regs */
299	if (rdev->family == CHIP_RV730) {	300	if (rdev->family == CHIP_RV730) {
300	WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);	301	WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
301		302
302	/* wait for SPLL_CHG_STATUS to change to 1 */	303	/* wait for SPLL_CHG_STATUS to change to 1 */
303	cg_spll_status = 0;	304	cg_spll_status = 0;
304	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))	305	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
305	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);	306	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
306	}	307	}
307	WREG32(RADEON_VIPH_CONTROL, viph_control);	308	WREG32(RADEON_VIPH_CONTROL, viph_control);
308	WREG32(R600_BUS_CNTL, bus_cntl);	309	WREG32(R600_BUS_CNTL, bus_cntl);
309	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	310	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
310	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	311	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
311	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	312	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
312	WREG32(R600_ROM_CNTL, rom_cntl);	313	WREG32(R600_ROM_CNTL, rom_cntl);
313	return r;	314	return r;
314	}	315	}
315		316
316	static bool r600_read_disabled_bios(struct radeon_device *rdev)	317	static bool r600_read_disabled_bios(struct radeon_device *rdev)
317	{	318	{
318	uint32_t viph_control;	319	uint32_t viph_control;
319	uint32_t bus_cntl;	320	uint32_t bus_cntl;
320	uint32_t d1vga_control;	321	uint32_t d1vga_control;
321	uint32_t d2vga_control;	322	uint32_t d2vga_control;
322	uint32_t vga_render_control;	323	uint32_t vga_render_control;
323	uint32_t rom_cntl;	324	uint32_t rom_cntl;
324	uint32_t general_pwrmgt;	325	uint32_t general_pwrmgt;
325	uint32_t low_vid_lower_gpio_cntl;	326	uint32_t low_vid_lower_gpio_cntl;
326	uint32_t medium_vid_lower_gpio_cntl;	327	uint32_t medium_vid_lower_gpio_cntl;
327	uint32_t high_vid_lower_gpio_cntl;	328	uint32_t high_vid_lower_gpio_cntl;
328	uint32_t ctxsw_vid_lower_gpio_cntl;	329	uint32_t ctxsw_vid_lower_gpio_cntl;
329	uint32_t lower_gpio_enable;	330	uint32_t lower_gpio_enable;
330	bool r;	331	bool r;
331		332
332	viph_control = RREG32(RADEON_VIPH_CONTROL);	333	viph_control = RREG32(RADEON_VIPH_CONTROL);
333	bus_cntl = RREG32(R600_BUS_CNTL);	334	bus_cntl = RREG32(R600_BUS_CNTL);
334	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	335	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
335	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	336	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
336	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	337	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
337	rom_cntl = RREG32(R600_ROM_CNTL);	338	rom_cntl = RREG32(R600_ROM_CNTL);
338	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);	339	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
339	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);	340	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
340	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);	341	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
341	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);	342	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
342	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);	343	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
343	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);	344	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
344		345
345	/* disable VIP */	346	/* disable VIP */
346	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	347	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
347	/* enable the rom */	348	/* enable the rom */
348	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));	349	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
349	/* Disable VGA mode */	350	/* Disable VGA mode */
350	WREG32(AVIVO_D1VGA_CONTROL,	351	WREG32(AVIVO_D1VGA_CONTROL,
351	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	352	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
352	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	353	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
353	WREG32(AVIVO_D2VGA_CONTROL,	354	WREG32(AVIVO_D2VGA_CONTROL,
354	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	355	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
355	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	356	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
356	WREG32(AVIVO_VGA_RENDER_CONTROL,	357	WREG32(AVIVO_VGA_RENDER_CONTROL,
357	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	358	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
358		359
359	WREG32(R600_ROM_CNTL,	360	WREG32(R600_ROM_CNTL,
360	((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) \|	361	((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) \|
361	(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) \|	362	(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) \|
362	R600_SCK_OVERWRITE));	363	R600_SCK_OVERWRITE));
363		364
364	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));	365	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
365	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,	366	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
366	(low_vid_lower_gpio_cntl & ~0x400));	367	(low_vid_lower_gpio_cntl & ~0x400));
367	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,	368	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
368	(medium_vid_lower_gpio_cntl & ~0x400));	369	(medium_vid_lower_gpio_cntl & ~0x400));
369	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,	370	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
370	(high_vid_lower_gpio_cntl & ~0x400));	371	(high_vid_lower_gpio_cntl & ~0x400));
371	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,	372	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
372	(ctxsw_vid_lower_gpio_cntl & ~0x400));	373	(ctxsw_vid_lower_gpio_cntl & ~0x400));
373	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable \| 0x400));	374	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable \| 0x400));
374		375
375	r = radeon_read_bios(rdev);	376	r = radeon_read_bios(rdev);
376		377
377	/* restore regs */	378	/* restore regs */
378	WREG32(RADEON_VIPH_CONTROL, viph_control);	379	WREG32(RADEON_VIPH_CONTROL, viph_control);
379	WREG32(R600_BUS_CNTL, bus_cntl);	380	WREG32(R600_BUS_CNTL, bus_cntl);
380	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	381	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
381	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	382	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
382	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	383	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
383	WREG32(R600_ROM_CNTL, rom_cntl);	384	WREG32(R600_ROM_CNTL, rom_cntl);
384	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);	385	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
385	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);	386	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
386	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);	387	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
387	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);	388	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
388	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);	389	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
389	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);	390	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
390	return r;	391	return r;
391	}	392	}
392		393
393	static bool avivo_read_disabled_bios(struct radeon_device *rdev)	394	static bool avivo_read_disabled_bios(struct radeon_device *rdev)
394	{	395	{
395	uint32_t seprom_cntl1;	396	uint32_t seprom_cntl1;
396	uint32_t viph_control;	397	uint32_t viph_control;
397	uint32_t bus_cntl;	398	uint32_t bus_cntl;
398	uint32_t d1vga_control;	399	uint32_t d1vga_control;
399	uint32_t d2vga_control;	400	uint32_t d2vga_control;
400	uint32_t vga_render_control;	401	uint32_t vga_render_control;
401	uint32_t gpiopad_a;	402	uint32_t gpiopad_a;
402	uint32_t gpiopad_en;	403	uint32_t gpiopad_en;
403	uint32_t gpiopad_mask;	404	uint32_t gpiopad_mask;
404	bool r;	405	bool r;
405		406
406	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);	407	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
407	viph_control = RREG32(RADEON_VIPH_CONTROL);	408	viph_control = RREG32(RADEON_VIPH_CONTROL);
408	bus_cntl = RREG32(RV370_BUS_CNTL);	409	bus_cntl = RREG32(RV370_BUS_CNTL);
409	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	410	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
410	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	411	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
411	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	412	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
412	gpiopad_a = RREG32(RADEON_GPIOPAD_A);	413	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
413	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);	414	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
414	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);	415	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
415		416
416	WREG32(RADEON_SEPROM_CNTL1,	417	WREG32(RADEON_SEPROM_CNTL1,
417	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|	418	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|
418	(0xc << RADEON_SCK_PRESCALE_SHIFT)));	419	(0xc << RADEON_SCK_PRESCALE_SHIFT)));
419	WREG32(RADEON_GPIOPAD_A, 0);	420	WREG32(RADEON_GPIOPAD_A, 0);
420	WREG32(RADEON_GPIOPAD_EN, 0);	421	WREG32(RADEON_GPIOPAD_EN, 0);
421	WREG32(RADEON_GPIOPAD_MASK, 0);	422	WREG32(RADEON_GPIOPAD_MASK, 0);
422		423
423	/* disable VIP */	424	/* disable VIP */
424	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	425	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
425		426
426	/* enable the rom */	427	/* enable the rom */
427	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));	428	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
428		429
429	/* Disable VGA mode */	430	/* Disable VGA mode */
430	WREG32(AVIVO_D1VGA_CONTROL,	431	WREG32(AVIVO_D1VGA_CONTROL,
431	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	432	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
432	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	433	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
433	WREG32(AVIVO_D2VGA_CONTROL,	434	WREG32(AVIVO_D2VGA_CONTROL,
434	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	435	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
435	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	436	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
436	WREG32(AVIVO_VGA_RENDER_CONTROL,	437	WREG32(AVIVO_VGA_RENDER_CONTROL,
437	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	438	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
438		439
439	r = radeon_read_bios(rdev);	440	r = radeon_read_bios(rdev);
440		441
441	/* restore regs */	442	/* restore regs */
442	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);	443	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
443	WREG32(RADEON_VIPH_CONTROL, viph_control);	444	WREG32(RADEON_VIPH_CONTROL, viph_control);
444	WREG32(RV370_BUS_CNTL, bus_cntl);	445	WREG32(RV370_BUS_CNTL, bus_cntl);
445	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	446	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
446	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	447	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
447	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	448	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
448	WREG32(RADEON_GPIOPAD_A, gpiopad_a);	449	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
449	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);	450	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
450	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);	451	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
451	return r;	452	return r;
452	}	453	}
453		454
454	static bool legacy_read_disabled_bios(struct radeon_device *rdev)	455	static bool legacy_read_disabled_bios(struct radeon_device *rdev)
455	{	456	{
456	uint32_t seprom_cntl1;	457	uint32_t seprom_cntl1;
457	uint32_t viph_control;	458	uint32_t viph_control;
458	uint32_t bus_cntl;	459	uint32_t bus_cntl;
459	uint32_t crtc_gen_cntl;	460	uint32_t crtc_gen_cntl;
460	uint32_t crtc2_gen_cntl;	461	uint32_t crtc2_gen_cntl;
461	uint32_t crtc_ext_cntl;	462	uint32_t crtc_ext_cntl;
462	uint32_t fp2_gen_cntl;	463	uint32_t fp2_gen_cntl;
463	bool r;	464	bool r;
464		465
465	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);	466	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
466	viph_control = RREG32(RADEON_VIPH_CONTROL);	467	viph_control = RREG32(RADEON_VIPH_CONTROL);
467	if (rdev->flags & RADEON_IS_PCIE)	468	if (rdev->flags & RADEON_IS_PCIE)
468	bus_cntl = RREG32(RV370_BUS_CNTL);	469	bus_cntl = RREG32(RV370_BUS_CNTL);
469	else	470	else
470	bus_cntl = RREG32(RADEON_BUS_CNTL);	471	bus_cntl = RREG32(RADEON_BUS_CNTL);
471	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);	472	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
472	crtc2_gen_cntl = 0;	473	crtc2_gen_cntl = 0;
473	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);	474	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
474	fp2_gen_cntl = 0;	475	fp2_gen_cntl = 0;
475		476
476	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {	477	if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
477	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);	478	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
478	}	479	}
479		480
480	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {	481	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
481	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);	482	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
482	}	483	}
483		484
484	WREG32(RADEON_SEPROM_CNTL1,	485	WREG32(RADEON_SEPROM_CNTL1,
485	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|	486	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|
486	(0xc << RADEON_SCK_PRESCALE_SHIFT)));	487	(0xc << RADEON_SCK_PRESCALE_SHIFT)));
487		488
488	/* disable VIP */	489	/* disable VIP */
489	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	490	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
490		491
491	/* enable the rom */	492	/* enable the rom */
492	if (rdev->flags & RADEON_IS_PCIE)	493	if (rdev->flags & RADEON_IS_PCIE)
493	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));	494	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
494	else	495	else
495	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));	496	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
496		497
497	/* Turn off mem requests and CRTC for both controllers */	498	/* Turn off mem requests and CRTC for both controllers */
498	WREG32(RADEON_CRTC_GEN_CNTL,	499	WREG32(RADEON_CRTC_GEN_CNTL,
499	((crtc_gen_cntl & ~RADEON_CRTC_EN) \|	500	((crtc_gen_cntl & ~RADEON_CRTC_EN) \|

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_bios.c – Rev 6104 → 7146