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Line 330... Line 330...
330 
	uint32_t gpiopad_mask;
 330 
	uint32_t gpiopad_mask;
331 
	bool r;
 331 
	bool r;
Line 332... Line 332...
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 332 
 
333 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 333 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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	viph_control = RREG32(RADEON_VIPH_CONTROL);
 334 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
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	bus_cntl = RREG32(RADEON_BUS_CNTL);
 335 
	bus_cntl = RREG32(RV370_BUS_CNTL);
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	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 336 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 337 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
338 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 338 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 339 
	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
Line 349... Line 349...
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 349 
 
350 
	/* disable VIP */
 350 
	/* disable VIP */
Line 351... Line 351...
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	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 351 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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 352 
 
Line 353... Line 353...
353 
	/* enable the rom */
 353 
	/* enable the rom */
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	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
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 355 
 
356 
	/* Disable VGA mode */
 356 
	/* Disable VGA mode */
Line 366... Line 366...
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	r = radeon_read_bios(rdev);
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	r = radeon_read_bios(rdev);
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367 
 
 367 
 
368 
	/* restore regs */
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	/* restore regs */
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	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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	WREG32(RADEON_VIPH_CONTROL, viph_control);
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	WREG32(RADEON_VIPH_CONTROL, viph_control);
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	WREG32(RADEON_BUS_CNTL, bus_cntl);
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	WREG32(RV370_BUS_CNTL, bus_cntl);
372 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 374 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
375 
	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 375 
	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
Line 389... Line 389...
389 
	uint32_t fp2_gen_cntl;
 389 
	uint32_t fp2_gen_cntl;
390 
	bool r;
 390 
	bool r;
Line 391... Line 391...
391 
 
 391 
 
392 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 392 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
- 
 
 393 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
- 
 
 394 
	if (rdev->flags & RADEON_IS_PCIE)
- 
 
 395 
		bus_cntl = RREG32(RV370_BUS_CNTL);
393 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
 396 
	else
394 
	bus_cntl = RREG32(RADEON_BUS_CNTL);
 397 
	bus_cntl = RREG32(RADEON_BUS_CNTL);
395 
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 398 
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
396 
	crtc2_gen_cntl = 0;
 399 
	crtc2_gen_cntl = 0;
397 
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 400 
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
Line 411... Line 414...
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 414 
 
412 
	/* disable VIP */
 415 
	/* disable VIP */
Line 413... Line 416...
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	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 416 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
- 
 
 417 
 
- 
 
 418 
	/* enable the rom */
- 
 
 419 
	if (rdev->flags & RADEON_IS_PCIE)
414 
 
 420 
		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
Line 415... Line 421...
415 
	/* enable the rom */
 421 
	else
416 
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 422 
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
417 
 
 423 
 
Line 438... Line 444...
438 
	r = radeon_read_bios(rdev);
 444 
	r = radeon_read_bios(rdev);
Line 439... Line 445...
439 
 
 445 
 
440 
	/* restore regs */
 446 
	/* restore regs */
441 
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 447 
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
- 
 
 448 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
- 
 
 449 
	if (rdev->flags & RADEON_IS_PCIE)
- 
 
 450 
		WREG32(RV370_BUS_CNTL, bus_cntl);
442 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
 451 
	else
443 
	WREG32(RADEON_BUS_CNTL, bus_cntl);
 452 
	WREG32(RADEON_BUS_CNTL, bus_cntl);
444 
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 453 
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
445 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 454 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
446 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 455 
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);