WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_bios.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
 
//#include 
#include 
/*
 * BIOS.
 */
 
/* If you boot an IGP board with a discrete card as the primary,
 * the IGP rom is not accessible via the rom bar as the IGP rom is
 * part of the system bios.  On boot, the system bios puts a
 * copy of the igp rom at the start of vram if a discrete card is
 * present.
 */
static bool igp_read_bios_from_vram(struct radeon_device *rdev)
{
	uint8_t __iomem *bios;
	resource_size_t vram_base;
	resource_size_t size = 256 * 1024; /* ??? */
 
	if (!(rdev->flags & RADEON_IS_IGP))
		if (!radeon_card_posted(rdev))
			return false;
 
	rdev->bios = NULL;
	vram_base = pci_resource_start(rdev->pdev, 0);
	bios = ioremap(vram_base, size);
	if (!bios) {
		return false;
	}
 
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
		iounmap(bios);
		return false;
	}
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (rdev->bios == NULL) {
		iounmap(bios);
		return false;
	}
	memcpy(rdev->bios, bios, size);
	iounmap(bios);
	return true;
}
 
static bool radeon_read_bios(struct radeon_device *rdev)
{
	uint8_t __iomem *bios;
    size_t    size;
 
	rdev->bios = NULL;
	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
	bios = pci_map_rom(rdev->pdev, &size);
	if (!bios) {
		return false;
	}
 
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
//       pci_unmap_rom(rdev->pdev, bios);
		return false;
	}
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (rdev->bios == NULL) {
//        pci_unmap_rom(rdev->pdev, bios);
		return false;
	}
	memcpy(rdev->bios, bios, size);
//    pci_unmap_rom(rdev->pdev, bios);
	return true;
}
 
/* ATRM is used to get the BIOS on the discrete cards in
 * dual-gpu systems.
 */
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
{
	int ret;
	int size = 64 * 1024;
	int i;
 
	if (!radeon_atrm_supported(rdev->pdev))
		return false;
 
	rdev->bios = kmalloc(size, GFP_KERNEL);
	if (!rdev->bios) {
		DRM_ERROR("Unable to allocate bios\n");
		return false;
	}
 
	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
		ret = radeon_atrm_get_bios_chunk(rdev->bios,
						 (i * ATRM_BIOS_PAGE),
						 ATRM_BIOS_PAGE);
		if (ret <= 0)
			break;
	}
 
	if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
		kfree(rdev->bios);
		return false;
	}
	return true;
}
 
static bool ni_read_disabled_bios(struct radeon_device *rdev)
{
	u32 bus_cntl;
	u32 d1vga_control;
	u32 d2vga_control;
	u32 vga_render_control;
	u32 rom_cntl;
	bool r;
 
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
 
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(R600_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(R600_ROM_CNTL, rom_cntl);
	return r;
}
 
static bool r700_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t rom_cntl;
	uint32_t cg_spll_func_cntl = 0;
	uint32_t cg_spll_status;
	bool r;
 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	if (rdev->family == CHIP_RV730) {
		cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 
		/* enable bypass mode */
		WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
						R600_SPLL_BYPASS_EN));
 
		/* wait for SPLL_CHG_STATUS to change to 1 */
		cg_spll_status = 0;
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 
		WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
	} else
		WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	if (rdev->family == CHIP_RV730) {
		WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 
		/* wait for SPLL_CHG_STATUS to change to 1 */
		cg_spll_status = 0;
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
	}
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(R600_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(R600_ROM_CNTL, rom_cntl);
	return r;
}
 
static bool r600_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t rom_cntl;
	uint32_t general_pwrmgt;
	uint32_t low_vid_lower_gpio_cntl;
	uint32_t medium_vid_lower_gpio_cntl;
	uint32_t high_vid_lower_gpio_cntl;
	uint32_t ctxsw_vid_lower_gpio_cntl;
	uint32_t lower_gpio_enable;
	bool r;
 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(R600_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	rom_cntl = RREG32(R600_ROM_CNTL);
	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
	/* enable the rom */
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	WREG32(R600_ROM_CNTL,
	       ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
		(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
		R600_SCK_OVERWRITE));
 
	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
	       (low_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
	       (medium_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
	       (high_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
	       (ctxsw_vid_lower_gpio_cntl & ~0x400));
	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(R600_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(R600_ROM_CNTL, rom_cntl);
	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
	return r;
}
 
static bool avivo_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t seprom_cntl1;
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t d1vga_control;
	uint32_t d2vga_control;
	uint32_t vga_render_control;
	uint32_t gpiopad_a;
	uint32_t gpiopad_en;
	uint32_t gpiopad_mask;
	bool r;
 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(RADEON_BUS_CNTL);
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 
	WREG32(RADEON_SEPROM_CNTL1,
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
	WREG32(RADEON_GPIOPAD_A, 0);
	WREG32(RADEON_GPIOPAD_EN, 0);
	WREG32(RADEON_GPIOPAD_MASK, 0);
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
	/* enable the rom */
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
	/* Disable VGA mode */
	WREG32(AVIVO_D1VGA_CONTROL,
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_D2VGA_CONTROL,
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
	WREG32(AVIVO_VGA_RENDER_CONTROL,
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(RADEON_BUS_CNTL, bus_cntl);
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
	return r;
}
 
static bool legacy_read_disabled_bios(struct radeon_device *rdev)
{
	uint32_t seprom_cntl1;
	uint32_t viph_control;
	uint32_t bus_cntl;
	uint32_t crtc_gen_cntl;
	uint32_t crtc2_gen_cntl;
	uint32_t crtc_ext_cntl;
	uint32_t fp2_gen_cntl;
	bool r;
 
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
	viph_control = RREG32(RADEON_VIPH_CONTROL);
	bus_cntl = RREG32(RADEON_BUS_CNTL);
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
	crtc2_gen_cntl = 0;
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
	fp2_gen_cntl = 0;
 
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
	}
 
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
	}
 
	WREG32(RADEON_SEPROM_CNTL1,
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
 
	/* disable VIP */
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 
	/* enable the rom */
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 
	/* Turn off mem requests and CRTC for both controllers */
	WREG32(RADEON_CRTC_GEN_CNTL,
	       ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
		(RADEON_CRTC_DISP_REQ_EN_B |
		 RADEON_CRTC_EXT_DISP_EN)));
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(RADEON_CRTC2_GEN_CNTL,
		       ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
			RADEON_CRTC2_DISP_REQ_EN_B));
	}
	/* Turn off CRTC */
	WREG32(RADEON_CRTC_EXT_CNTL,
	       ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
		(RADEON_CRTC_SYNC_TRISTAT |
		 RADEON_CRTC_DISPLAY_DIS)));
 
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
	}
 
	r = radeon_read_bios(rdev);
 
	/* restore regs */
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
	WREG32(RADEON_VIPH_CONTROL, viph_control);
	WREG32(RADEON_BUS_CNTL, bus_cntl);
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
	}
	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
	}
	return r;
}
 
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
{
	if (rdev->flags & RADEON_IS_IGP)
		return igp_read_bios_from_vram(rdev);
	else if (rdev->family >= CHIP_BARTS)
		return ni_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_RV770)
		return r700_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_R600)
		return r600_read_disabled_bios(rdev);
	else if (rdev->family >= CHIP_RS600)
		return avivo_read_disabled_bios(rdev);
	else
		return legacy_read_disabled_bios(rdev);
}
 
 
bool radeon_get_bios(struct radeon_device *rdev)
{
	bool r;
	uint16_t tmp;
 
	r = radeon_atrm_get_bios(rdev);
	if (r == false)
		r = igp_read_bios_from_vram(rdev);
		if (r == false)
			r = radeon_read_bios(rdev);
	if (r == false) {
		r = radeon_read_disabled_bios(rdev);
	}
	if (r == false || rdev->bios == NULL) {
		DRM_ERROR("Unable to locate a BIOS ROM\n");
		rdev->bios = NULL;
		return false;
	}
	if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
		printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
		goto free_bios;
	}
 
	tmp = RBIOS16(0x18);
	if (RBIOS8(tmp + 0x14) != 0x0) {
		DRM_INFO("Not an x86 BIOS ROM, not using.\n");
		goto free_bios;
	}
 
	rdev->bios_header_start = RBIOS16(0x48);
	if (!rdev->bios_header_start) {
		goto free_bios;
	}
	tmp = rdev->bios_header_start + 4;
	if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
	    !memcmp(rdev->bios + tmp, "MOTA", 4)) {
		rdev->is_atom_bios = true;
	} else {
		rdev->is_atom_bios = false;
	}
 
	DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
	return true;
free_bios:
	kfree(rdev->bios);
	rdev->bios = NULL;
	return false;
}

Rev 1430	Rev 1963
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include "drmP.h"	28	#include "drmP.h"
29	#include "radeon_reg.h"	29	#include "radeon_reg.h"
30	#include "radeon.h"	30	#include "radeon.h"
31	#include "atom.h"	31	#include "atom.h"
-		32
-		33	//#include
32		34	#include
33	/*	35	/*
34	* BIOS.	36	* BIOS.
35	*/	37	*/
36		38
37	/* If you boot an IGP board with a discrete card as the primary,	39	/* If you boot an IGP board with a discrete card as the primary,
38	* the IGP rom is not accessible via the rom bar as the IGP rom is	40	* the IGP rom is not accessible via the rom bar as the IGP rom is
39	* part of the system bios. On boot, the system bios puts a	41	* part of the system bios. On boot, the system bios puts a
40	* copy of the igp rom at the start of vram if a discrete card is	42	* copy of the igp rom at the start of vram if a discrete card is
41	* present.	43	* present.
42	*/	44	*/
43	static bool igp_read_bios_from_vram(struct radeon_device *rdev)	45	static bool igp_read_bios_from_vram(struct radeon_device *rdev)
44	{	46	{
45	uint8_t __iomem *bios;	47	uint8_t __iomem *bios;
46	resource_size_t vram_base;	48	resource_size_t vram_base;
47	resource_size_t size = 256 * 1024; /* ??? */	49	resource_size_t size = 256 * 1024; /* ??? */
-		50
-		51	if (!(rdev->flags & RADEON_IS_IGP))
-		52	if (!radeon_card_posted(rdev))
-		53	return false;
48		54
49	rdev->bios = NULL;	55	rdev->bios = NULL;
50	vram_base = drm_get_resource_start(rdev->ddev, 0);	56	vram_base = pci_resource_start(rdev->pdev, 0);
51	bios = ioremap(vram_base, size);	57	bios = ioremap(vram_base, size);
52	if (!bios) {	58	if (!bios) {
53	return false;	59	return false;
54	}	60	}
55		61
56	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {	62	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {
57	iounmap(bios);	63	iounmap(bios);
58	return false;	64	return false;
59	}	65	}
60	rdev->bios = kmalloc(size, GFP_KERNEL);	66	rdev->bios = kmalloc(size, GFP_KERNEL);
61	if (rdev->bios == NULL) {	67	if (rdev->bios == NULL) {
62	iounmap(bios);	68	iounmap(bios);
63	return false;	69	return false;
64	}	70	}
65	memcpy(rdev->bios, bios, size);	71	memcpy(rdev->bios, bios, size);
66	iounmap(bios);	72	iounmap(bios);
67	return true;	73	return true;
68	}	74	}
69		75
70	static bool radeon_read_bios(struct radeon_device *rdev)	76	static bool radeon_read_bios(struct radeon_device *rdev)
71	{	77	{
72	uint8_t __iomem *bios;	78	uint8_t __iomem *bios;
73	size_t size;	79	size_t size;
74		80
75	rdev->bios = NULL;	81	rdev->bios = NULL;
76	/* XXX: some cards may return 0 for rom size? ddx has a workaround */	82	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
77	bios = pci_map_rom(rdev->pdev, &size);	83	bios = pci_map_rom(rdev->pdev, &size);
78	if (!bios) {	84	if (!bios) {
79	return false;	85	return false;
80	}	86	}
81		87
82	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {	88	if (size == 0 \|\| bios[0] != 0x55 \|\| bios[1] != 0xaa) {
83	// pci_unmap_rom(rdev->pdev, bios);	89	// pci_unmap_rom(rdev->pdev, bios);
84	return false;	90	return false;
85	}	91	}
86	rdev->bios = kmalloc(size, GFP_KERNEL);	92	rdev->bios = kmalloc(size, GFP_KERNEL);
87	if (rdev->bios == NULL) {	93	if (rdev->bios == NULL) {
88	// pci_unmap_rom(rdev->pdev, bios);	94	// pci_unmap_rom(rdev->pdev, bios);
89	return false;	95	return false;
90	}	96	}
91	memcpy(rdev->bios, bios, size);	97	memcpy(rdev->bios, bios, size);
92	// pci_unmap_rom(rdev->pdev, bios);	98	// pci_unmap_rom(rdev->pdev, bios);
93	return true;	99	return true;
94	}	100	}
95		101
96	/* ATRM is used to get the BIOS on the discrete cards in	102	/* ATRM is used to get the BIOS on the discrete cards in
97	* dual-gpu systems.	103	* dual-gpu systems.
98	*/	104	*/
99	static bool radeon_atrm_get_bios(struct radeon_device *rdev)	105	static bool radeon_atrm_get_bios(struct radeon_device *rdev)
100	{	106	{
101	int ret;	107	int ret;
102	int size = 64 * 1024;	108	int size = 64 * 1024;
103	int i;	109	int i;
104		110
105	if (!radeon_atrm_supported(rdev->pdev))	111	if (!radeon_atrm_supported(rdev->pdev))
106	return false;	112	return false;
107		113
108	rdev->bios = kmalloc(size, GFP_KERNEL);	114	rdev->bios = kmalloc(size, GFP_KERNEL);
109	if (!rdev->bios) {	115	if (!rdev->bios) {
110	DRM_ERROR("Unable to allocate bios\n");	116	DRM_ERROR("Unable to allocate bios\n");
111	return false;	117	return false;
112	}	118	}
113		119
114	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {	120	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
115	ret = radeon_atrm_get_bios_chunk(rdev->bios,	121	ret = radeon_atrm_get_bios_chunk(rdev->bios,
116	(i * ATRM_BIOS_PAGE),	122	(i * ATRM_BIOS_PAGE),
117	ATRM_BIOS_PAGE);	123	ATRM_BIOS_PAGE);
118	if (ret <= 0)	124	if (ret <= 0)
119	break;	125	break;
120	}	126	}
121		127
122	if (i == 0 \|\| rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {	128	if (i == 0 \|\| rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {
123	kfree(rdev->bios);	129	kfree(rdev->bios);
124	return false;	130	return false;
125	}	131	}
126	return true;	132	return true;
127	}	133	}
-		134
-		135	static bool ni_read_disabled_bios(struct radeon_device *rdev)
-		136	{
-		137	u32 bus_cntl;
-		138	u32 d1vga_control;
-		139	u32 d2vga_control;
-		140	u32 vga_render_control;
-		141	u32 rom_cntl;
-		142	bool r;
-		143
-		144	bus_cntl = RREG32(R600_BUS_CNTL);
-		145	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
-		146	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
-		147	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
-		148	rom_cntl = RREG32(R600_ROM_CNTL);
-		149
-		150	/* enable the rom */
-		151	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
-		152	/* Disable VGA mode */
-		153	WREG32(AVIVO_D1VGA_CONTROL,
-		154	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
-		155	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
-		156	WREG32(AVIVO_D2VGA_CONTROL,
-		157	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
-		158	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
-		159	WREG32(AVIVO_VGA_RENDER_CONTROL,
-		160	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
-		161	WREG32(R600_ROM_CNTL, rom_cntl \| R600_SCK_OVERWRITE);
-		162
-		163	r = radeon_read_bios(rdev);
-		164
-		165	/* restore regs */
-		166	WREG32(R600_BUS_CNTL, bus_cntl);
-		167	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
-		168	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
-		169	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
-		170	WREG32(R600_ROM_CNTL, rom_cntl);
-		171	return r;
-		172	}
-		173
128	static bool r700_read_disabled_bios(struct radeon_device *rdev)	174	static bool r700_read_disabled_bios(struct radeon_device *rdev)
129	{	175	{
130	uint32_t viph_control;	176	uint32_t viph_control;
131	uint32_t bus_cntl;	177	uint32_t bus_cntl;
132	uint32_t d1vga_control;	178	uint32_t d1vga_control;
133	uint32_t d2vga_control;	179	uint32_t d2vga_control;
134	uint32_t vga_render_control;	180	uint32_t vga_render_control;
135	uint32_t rom_cntl;	181	uint32_t rom_cntl;
136	uint32_t cg_spll_func_cntl = 0;	182	uint32_t cg_spll_func_cntl = 0;
137	uint32_t cg_spll_status;	183	uint32_t cg_spll_status;
138	bool r;	184	bool r;
139		185
140	viph_control = RREG32(RADEON_VIPH_CONTROL);	186	viph_control = RREG32(RADEON_VIPH_CONTROL);
141	bus_cntl = RREG32(RADEON_BUS_CNTL);	187	bus_cntl = RREG32(R600_BUS_CNTL);
142	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	188	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
143	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	189	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
144	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	190	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
145	rom_cntl = RREG32(R600_ROM_CNTL);	191	rom_cntl = RREG32(R600_ROM_CNTL);
146		192
147	/* disable VIP */	193	/* disable VIP */
148	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	194	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
149	/* enable the rom */	195	/* enable the rom */
150	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));	196	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151	/* Disable VGA mode */	197	/* Disable VGA mode */
152	WREG32(AVIVO_D1VGA_CONTROL,	198	WREG32(AVIVO_D1VGA_CONTROL,
153	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	199	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
154	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	200	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
155	WREG32(AVIVO_D2VGA_CONTROL,	201	WREG32(AVIVO_D2VGA_CONTROL,
156	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	202	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
157	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	203	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
158	WREG32(AVIVO_VGA_RENDER_CONTROL,	204	WREG32(AVIVO_VGA_RENDER_CONTROL,
159	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	205	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
160		206
161	if (rdev->family == CHIP_RV730) {	207	if (rdev->family == CHIP_RV730) {
162	cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);	208	cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
163		209
164	/* enable bypass mode */	210	/* enable bypass mode */
165	WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl \|	211	WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl \|
166	R600_SPLL_BYPASS_EN));	212	R600_SPLL_BYPASS_EN));
167		213
168	/* wait for SPLL_CHG_STATUS to change to 1 */	214	/* wait for SPLL_CHG_STATUS to change to 1 */
169	cg_spll_status = 0;	215	cg_spll_status = 0;
170	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))	216	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
171	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);	217	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
172		218
173	WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));	219	WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
174	} else	220	} else
175	WREG32(R600_ROM_CNTL, (rom_cntl \| R600_SCK_OVERWRITE));	221	WREG32(R600_ROM_CNTL, (rom_cntl \| R600_SCK_OVERWRITE));
176		222
177	r = radeon_read_bios(rdev);	223	r = radeon_read_bios(rdev);
178		224
179	/* restore regs */	225	/* restore regs */
180	if (rdev->family == CHIP_RV730) {	226	if (rdev->family == CHIP_RV730) {
181	WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);	227	WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
182		228
183	/* wait for SPLL_CHG_STATUS to change to 1 */	229	/* wait for SPLL_CHG_STATUS to change to 1 */
184	cg_spll_status = 0;	230	cg_spll_status = 0;
185	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))	231	while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
186	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);	232	cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
187	}	233	}
188	WREG32(RADEON_VIPH_CONTROL, viph_control);	234	WREG32(RADEON_VIPH_CONTROL, viph_control);
189	WREG32(RADEON_BUS_CNTL, bus_cntl);	235	WREG32(R600_BUS_CNTL, bus_cntl);
190	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	236	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
191	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	237	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
192	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	238	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
193	WREG32(R600_ROM_CNTL, rom_cntl);	239	WREG32(R600_ROM_CNTL, rom_cntl);
194	return r;	240	return r;
195	}	241	}
196		242
197	static bool r600_read_disabled_bios(struct radeon_device *rdev)	243	static bool r600_read_disabled_bios(struct radeon_device *rdev)
198	{	244	{
199	uint32_t viph_control;	245	uint32_t viph_control;
200	uint32_t bus_cntl;	246	uint32_t bus_cntl;
201	uint32_t d1vga_control;	247	uint32_t d1vga_control;
202	uint32_t d2vga_control;	248	uint32_t d2vga_control;
203	uint32_t vga_render_control;	249	uint32_t vga_render_control;
204	uint32_t rom_cntl;	250	uint32_t rom_cntl;
205	uint32_t general_pwrmgt;	251	uint32_t general_pwrmgt;
206	uint32_t low_vid_lower_gpio_cntl;	252	uint32_t low_vid_lower_gpio_cntl;
207	uint32_t medium_vid_lower_gpio_cntl;	253	uint32_t medium_vid_lower_gpio_cntl;
208	uint32_t high_vid_lower_gpio_cntl;	254	uint32_t high_vid_lower_gpio_cntl;
209	uint32_t ctxsw_vid_lower_gpio_cntl;	255	uint32_t ctxsw_vid_lower_gpio_cntl;
210	uint32_t lower_gpio_enable;	256	uint32_t lower_gpio_enable;
211	bool r;	257	bool r;
212		258
213	viph_control = RREG32(RADEON_VIPH_CONTROL);	259	viph_control = RREG32(RADEON_VIPH_CONTROL);
214	bus_cntl = RREG32(RADEON_BUS_CNTL);	260	bus_cntl = RREG32(R600_BUS_CNTL);
215	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	261	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
216	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	262	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
217	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	263	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
218	rom_cntl = RREG32(R600_ROM_CNTL);	264	rom_cntl = RREG32(R600_ROM_CNTL);
219	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);	265	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
220	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);	266	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
221	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);	267	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
222	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);	268	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
223	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);	269	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
224	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);	270	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
225		271
226	/* disable VIP */	272	/* disable VIP */
227	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	273	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
228	/* enable the rom */	274	/* enable the rom */
229	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));	275	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
230	/* Disable VGA mode */	276	/* Disable VGA mode */
231	WREG32(AVIVO_D1VGA_CONTROL,	277	WREG32(AVIVO_D1VGA_CONTROL,
232	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	278	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
233	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	279	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
234	WREG32(AVIVO_D2VGA_CONTROL,	280	WREG32(AVIVO_D2VGA_CONTROL,
235	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	281	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
236	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	282	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
237	WREG32(AVIVO_VGA_RENDER_CONTROL,	283	WREG32(AVIVO_VGA_RENDER_CONTROL,
238	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	284	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
239		285
240	WREG32(R600_ROM_CNTL,	286	WREG32(R600_ROM_CNTL,
241	((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) \|	287	((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) \|
242	(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) \|	288	(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) \|
243	R600_SCK_OVERWRITE));	289	R600_SCK_OVERWRITE));
244		290
245	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));	291	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
246	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,	292	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
247	(low_vid_lower_gpio_cntl & ~0x400));	293	(low_vid_lower_gpio_cntl & ~0x400));
248	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,	294	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
249	(medium_vid_lower_gpio_cntl & ~0x400));	295	(medium_vid_lower_gpio_cntl & ~0x400));
250	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,	296	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
251	(high_vid_lower_gpio_cntl & ~0x400));	297	(high_vid_lower_gpio_cntl & ~0x400));
252	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,	298	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
253	(ctxsw_vid_lower_gpio_cntl & ~0x400));	299	(ctxsw_vid_lower_gpio_cntl & ~0x400));
254	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable \| 0x400));	300	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable \| 0x400));
255		301
256	r = radeon_read_bios(rdev);	302	r = radeon_read_bios(rdev);
257		303
258	/* restore regs */	304	/* restore regs */
259	WREG32(RADEON_VIPH_CONTROL, viph_control);	305	WREG32(RADEON_VIPH_CONTROL, viph_control);
260	WREG32(RADEON_BUS_CNTL, bus_cntl);	306	WREG32(R600_BUS_CNTL, bus_cntl);
261	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	307	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
262	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	308	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
263	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	309	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
264	WREG32(R600_ROM_CNTL, rom_cntl);	310	WREG32(R600_ROM_CNTL, rom_cntl);
265	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);	311	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
266	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);	312	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
267	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);	313	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
268	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);	314	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
269	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);	315	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
270	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);	316	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
271	return r;	317	return r;
272	}	318	}
273		319
274	static bool avivo_read_disabled_bios(struct radeon_device *rdev)	320	static bool avivo_read_disabled_bios(struct radeon_device *rdev)
275	{	321	{
276	uint32_t seprom_cntl1;	322	uint32_t seprom_cntl1;
277	uint32_t viph_control;	323	uint32_t viph_control;
278	uint32_t bus_cntl;	324	uint32_t bus_cntl;
279	uint32_t d1vga_control;	325	uint32_t d1vga_control;
280	uint32_t d2vga_control;	326	uint32_t d2vga_control;
281	uint32_t vga_render_control;	327	uint32_t vga_render_control;
282	uint32_t gpiopad_a;	328	uint32_t gpiopad_a;
283	uint32_t gpiopad_en;	329	uint32_t gpiopad_en;
284	uint32_t gpiopad_mask;	330	uint32_t gpiopad_mask;
285	bool r;	331	bool r;
286		332
287	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);	333	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
288	viph_control = RREG32(RADEON_VIPH_CONTROL);	334	viph_control = RREG32(RADEON_VIPH_CONTROL);
289	bus_cntl = RREG32(RADEON_BUS_CNTL);	335	bus_cntl = RREG32(RADEON_BUS_CNTL);
290	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);	336	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
291	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);	337	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
292	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);	338	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
293	gpiopad_a = RREG32(RADEON_GPIOPAD_A);	339	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
294	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);	340	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
295	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);	341	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
296		342
297	WREG32(RADEON_SEPROM_CNTL1,	343	WREG32(RADEON_SEPROM_CNTL1,
298	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|	344	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|
299	(0xc << RADEON_SCK_PRESCALE_SHIFT)));	345	(0xc << RADEON_SCK_PRESCALE_SHIFT)));
300	WREG32(RADEON_GPIOPAD_A, 0);	346	WREG32(RADEON_GPIOPAD_A, 0);
301	WREG32(RADEON_GPIOPAD_EN, 0);	347	WREG32(RADEON_GPIOPAD_EN, 0);
302	WREG32(RADEON_GPIOPAD_MASK, 0);	348	WREG32(RADEON_GPIOPAD_MASK, 0);
303		349
304	/* disable VIP */	350	/* disable VIP */
305	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	351	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
306		352
307	/* enable the rom */	353	/* enable the rom */
308	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));	354	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
309		355
310	/* Disable VGA mode */	356	/* Disable VGA mode */
311	WREG32(AVIVO_D1VGA_CONTROL,	357	WREG32(AVIVO_D1VGA_CONTROL,
312	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	358	(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
313	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	359	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
314	WREG32(AVIVO_D2VGA_CONTROL,	360	WREG32(AVIVO_D2VGA_CONTROL,
315	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|	361	(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE \|
316	AVIVO_DVGA_CONTROL_TIMING_SELECT)));	362	AVIVO_DVGA_CONTROL_TIMING_SELECT)));
317	WREG32(AVIVO_VGA_RENDER_CONTROL,	363	WREG32(AVIVO_VGA_RENDER_CONTROL,
318	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));	364	(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
319		365
320	r = radeon_read_bios(rdev);	366	r = radeon_read_bios(rdev);
321		367
322	/* restore regs */	368	/* restore regs */
323	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);	369	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
324	WREG32(RADEON_VIPH_CONTROL, viph_control);	370	WREG32(RADEON_VIPH_CONTROL, viph_control);
325	WREG32(RADEON_BUS_CNTL, bus_cntl);	371	WREG32(RADEON_BUS_CNTL, bus_cntl);
326	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);	372	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
327	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);	373	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
328	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);	374	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
329	WREG32(RADEON_GPIOPAD_A, gpiopad_a);	375	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
330	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);	376	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
331	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);	377	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
332	return r;	378	return r;
333	}	379	}
334		380
335	static bool legacy_read_disabled_bios(struct radeon_device *rdev)	381	static bool legacy_read_disabled_bios(struct radeon_device *rdev)
336	{	382	{
337	uint32_t seprom_cntl1;	383	uint32_t seprom_cntl1;
338	uint32_t viph_control;	384	uint32_t viph_control;
339	uint32_t bus_cntl;	385	uint32_t bus_cntl;
340	uint32_t crtc_gen_cntl;	386	uint32_t crtc_gen_cntl;
341	uint32_t crtc2_gen_cntl;	387	uint32_t crtc2_gen_cntl;
342	uint32_t crtc_ext_cntl;	388	uint32_t crtc_ext_cntl;
343	uint32_t fp2_gen_cntl;	389	uint32_t fp2_gen_cntl;
344	bool r;	390	bool r;
345		391
346	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);	392	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
347	viph_control = RREG32(RADEON_VIPH_CONTROL);	393	viph_control = RREG32(RADEON_VIPH_CONTROL);
348	bus_cntl = RREG32(RADEON_BUS_CNTL);	394	bus_cntl = RREG32(RADEON_BUS_CNTL);
349	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);	395	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
350	crtc2_gen_cntl = 0;	396	crtc2_gen_cntl = 0;
351	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);	397	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
352	fp2_gen_cntl = 0;	398	fp2_gen_cntl = 0;
353		399
354	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {	400	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
355	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);	401	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
356	}	402	}
357		403
358	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {	404	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
359	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);	405	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
360	}	406	}
361		407
362	WREG32(RADEON_SEPROM_CNTL1,	408	WREG32(RADEON_SEPROM_CNTL1,
363	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|	409	((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) \|
364	(0xc << RADEON_SCK_PRESCALE_SHIFT)));	410	(0xc << RADEON_SCK_PRESCALE_SHIFT)));
365		411
366	/* disable VIP */	412	/* disable VIP */
367	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));	413	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
368		414
369	/* enable the rom */	415	/* enable the rom */
370	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));	416	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
371		417
372	/* Turn off mem requests and CRTC for both controllers */	418	/* Turn off mem requests and CRTC for both controllers */
373	WREG32(RADEON_CRTC_GEN_CNTL,	419	WREG32(RADEON_CRTC_GEN_CNTL,
374	((crtc_gen_cntl & ~RADEON_CRTC_EN) \|	420	((crtc_gen_cntl & ~RADEON_CRTC_EN) \|
375	(RADEON_CRTC_DISP_REQ_EN_B \|	421	(RADEON_CRTC_DISP_REQ_EN_B \|
376	RADEON_CRTC_EXT_DISP_EN)));	422	RADEON_CRTC_EXT_DISP_EN)));
377	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {	423	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
378	WREG32(RADEON_CRTC2_GEN_CNTL,	424	WREG32(RADEON_CRTC2_GEN_CNTL,
379	((crtc2_gen_cntl & ~RADEON_CRTC2_EN) \|	425	((crtc2_gen_cntl & ~RADEON_CRTC2_EN) \|
380	RADEON_CRTC2_DISP_REQ_EN_B));	426	RADEON_CRTC2_DISP_REQ_EN_B));
381	}	427	}
382	/* Turn off CRTC */	428	/* Turn off CRTC */
383	WREG32(RADEON_CRTC_EXT_CNTL,	429	WREG32(RADEON_CRTC_EXT_CNTL,
384	((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) \|	430	((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) \|
385	(RADEON_CRTC_SYNC_TRISTAT \|	431	(RADEON_CRTC_SYNC_TRISTAT \|
386	RADEON_CRTC_DISPLAY_DIS)));	432	RADEON_CRTC_DISPLAY_DIS)));
387		433
388	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {	434	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
389	WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));	435	WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
390	}	436	}
391		437
392	r = radeon_read_bios(rdev);	438	r = radeon_read_bios(rdev);
393		439
394	/* restore regs */	440	/* restore regs */
395	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);	441	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
396	WREG32(RADEON_VIPH_CONTROL, viph_control);	442	WREG32(RADEON_VIPH_CONTROL, viph_control);
397	WREG32(RADEON_BUS_CNTL, bus_cntl);	443	WREG32(RADEON_BUS_CNTL, bus_cntl);
398	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);	444	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
399	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {	445	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
400	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);	446	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
401	}	447	}
402	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);	448	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
403	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {	449	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
404	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);	450	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
405	}	451	}
406	return r;	452	return r;
407	}	453	}
408		454
409	static bool radeon_read_disabled_bios(struct radeon_device *rdev)	455	static bool radeon_read_disabled_bios(struct radeon_device *rdev)
410	{	456	{
411	if (rdev->flags & RADEON_IS_IGP)	457	if (rdev->flags & RADEON_IS_IGP)
412	return igp_read_bios_from_vram(rdev);	458	return igp_read_bios_from_vram(rdev);
-		459	else if (rdev->family >= CHIP_BARTS)
-		460	return ni_read_disabled_bios(rdev);
413	else if (rdev->family >= CHIP_RV770)	461	else if (rdev->family >= CHIP_RV770)
414	return r700_read_disabled_bios(rdev);	462	return r700_read_disabled_bios(rdev);
415	else if (rdev->family >= CHIP_R600)	463	else if (rdev->family >= CHIP_R600)
416	return r600_read_disabled_bios(rdev);	464	return r600_read_disabled_bios(rdev);
417	else if (rdev->family >= CHIP_RS600)	465	else if (rdev->family >= CHIP_RS600)
418	return avivo_read_disabled_bios(rdev);	466	return avivo_read_disabled_bios(rdev);
419	else	467	else
420	return legacy_read_disabled_bios(rdev);	468	return legacy_read_disabled_bios(rdev);
421	}	469	}
422		470
423		471
424	bool radeon_get_bios(struct radeon_device *rdev)	472	bool radeon_get_bios(struct radeon_device *rdev)
425	{	473	{
426	bool r;	474	bool r;
427	uint16_t tmp;	475	uint16_t tmp;
428		476
429	r = radeon_atrm_get_bios(rdev);	477	r = radeon_atrm_get_bios(rdev);
430	if (r == false)	478	if (r == false)
431	r = igp_read_bios_from_vram(rdev);	479	r = igp_read_bios_from_vram(rdev);
432	if (r == false)	480	if (r == false)
433	r = radeon_read_bios(rdev);	481	r = radeon_read_bios(rdev);
434	if (r == false) {	482	if (r == false) {
435	r = radeon_read_disabled_bios(rdev);	483	r = radeon_read_disabled_bios(rdev);
436	}	484	}
437	if (r == false \|\| rdev->bios == NULL) {	485	if (r == false \|\| rdev->bios == NULL) {
438	DRM_ERROR("Unable to locate a BIOS ROM\n");	486	DRM_ERROR("Unable to locate a BIOS ROM\n");
439	rdev->bios = NULL;	487	rdev->bios = NULL;
440	return false;	488	return false;
441	}	489	}
442	if (rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {	490	if (rdev->bios[0] != 0x55 \|\| rdev->bios[1] != 0xaa) {
443	printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);	491	printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
444	goto free_bios;	492	goto free_bios;
445	}	493	}
446		494
447	tmp = RBIOS16(0x18);	495	tmp = RBIOS16(0x18);
448	if (RBIOS8(tmp + 0x14) != 0x0) {	496	if (RBIOS8(tmp + 0x14) != 0x0) {
449	DRM_INFO("Not an x86 BIOS ROM, not using.\n");	497	DRM_INFO("Not an x86 BIOS ROM, not using.\n");
450	goto free_bios;	498	goto free_bios;
451	}	499	}
452		500

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_bios.c – Rev 1430 → 1963