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Rev 1430 Rev 1963
Line 28... Line 28...
28 
#include "drmP.h"
 28 
#include "drmP.h"
29 
#include "radeon_reg.h"
 29 
#include "radeon_reg.h"
30 
#include "radeon.h"
 30 
#include "radeon.h"
31 
#include "atom.h"
 31 
#include "atom.h"
Line -... Line 32...
- 
 
 32 
 
- 
 
 33 
//#include
32 
 
 34 
#include
33 
/*
 35 
/*
34 
 * BIOS.
 36 
 * BIOS.
Line 35... Line 37...
35 
 */
 37 
 */
Line 44... Line 46...
44 
{
 46 
{
45 
	uint8_t __iomem *bios;
 47 
	uint8_t __iomem *bios;
46 
	resource_size_t vram_base;
 48 
	resource_size_t vram_base;
47 
	resource_size_t size = 256 * 1024; /* ??? */
 49 
	resource_size_t size = 256 * 1024; /* ??? */
Line -... Line 50...
- 
 
 50 
 
- 
 
 51 
	if (!(rdev->flags & RADEON_IS_IGP))
- 
 
 52 
		if (!radeon_card_posted(rdev))
- 
 
 53 
			return false;
48 
 
 54 
 
49 
	rdev->bios = NULL;
 55 
	rdev->bios = NULL;
50 
	vram_base = drm_get_resource_start(rdev->ddev, 0);
 56 
	vram_base = pci_resource_start(rdev->pdev, 0);
51 
	bios = ioremap(vram_base, size);
 57 
	bios = ioremap(vram_base, size);
52 
	if (!bios) {
 58 
	if (!bios) {
53 
		return false;
 59 
		return false;
Line 123... Line 129...
123 
		kfree(rdev->bios);
 129 
		kfree(rdev->bios);
124 
		return false;
 130 
		return false;
125 
	}
 131 
	}
126 
	return true;
 132 
	return true;
127 
}
 133 
}
- 
 
 134 
 
- 
 
 135 
static bool ni_read_disabled_bios(struct radeon_device *rdev)
- 
 
 136 
{
- 
 
 137 
	u32 bus_cntl;
- 
 
 138 
	u32 d1vga_control;
- 
 
 139 
	u32 d2vga_control;
- 
 
 140 
	u32 vga_render_control;
- 
 
 141 
	u32 rom_cntl;
- 
 
 142 
	bool r;
- 
 
 143 
 
- 
 
 144 
	bus_cntl = RREG32(R600_BUS_CNTL);
- 
 
 145 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
- 
 
 146 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
- 
 
 147 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
- 
 
 148 
	rom_cntl = RREG32(R600_ROM_CNTL);
- 
 
 149 
 
- 
 
 150 
	/* enable the rom */
- 
 
 151 
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
- 
 
 152 
	/* Disable VGA mode */
- 
 
 153 
	WREG32(AVIVO_D1VGA_CONTROL,
- 
 
 154 
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
- 
 
 155 
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- 
 
 156 
	WREG32(AVIVO_D2VGA_CONTROL,
- 
 
 157 
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
- 
 
 158 
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- 
 
 159 
	WREG32(AVIVO_VGA_RENDER_CONTROL,
- 
 
 160 
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
- 
 
 161 
	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
- 
 
 162 
 
- 
 
 163 
	r = radeon_read_bios(rdev);
- 
 
 164 
 
- 
 
 165 
	/* restore regs */
- 
 
 166 
	WREG32(R600_BUS_CNTL, bus_cntl);
- 
 
 167 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
- 
 
 168 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
- 
 
 169 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
- 
 
 170 
	WREG32(R600_ROM_CNTL, rom_cntl);
- 
 
 171 
	return r;
- 
 
 172 
}
- 
 
 173 
 
128 
static bool r700_read_disabled_bios(struct radeon_device *rdev)
 174 
static bool r700_read_disabled_bios(struct radeon_device *rdev)
129 
{
 175 
{
130 
	uint32_t viph_control;
 176 
	uint32_t viph_control;
131 
	uint32_t bus_cntl;
 177 
	uint32_t bus_cntl;
132 
	uint32_t d1vga_control;
 178 
	uint32_t d1vga_control;
Line 136... Line 182...
136 
	uint32_t cg_spll_func_cntl = 0;
 182 
	uint32_t cg_spll_func_cntl = 0;
137 
	uint32_t cg_spll_status;
 183 
	uint32_t cg_spll_status;
138 
	bool r;
 184 
	bool r;
Line 139... Line 185...
139 
 
 185 
 
140 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
 186 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
141 
	bus_cntl = RREG32(RADEON_BUS_CNTL);
 187 
	bus_cntl = RREG32(R600_BUS_CNTL);
142 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 188 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
143 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 189 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
144 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 190 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
Line 145... Line 191...
145 
	rom_cntl = RREG32(R600_ROM_CNTL);
 191 
	rom_cntl = RREG32(R600_ROM_CNTL);
146 
 
 192 
 
147 
	/* disable VIP */
 193 
	/* disable VIP */
148 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 194 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
149 
	/* enable the rom */
 195 
	/* enable the rom */
150 
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 196 
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151 
	/* Disable VGA mode */
 197 
	/* Disable VGA mode */
152 
	WREG32(AVIVO_D1VGA_CONTROL,
 198 
	WREG32(AVIVO_D1VGA_CONTROL,
153 
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 199 
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
Line 184... Line 230...
184 
		cg_spll_status = 0;
 230 
		cg_spll_status = 0;
185 
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 231 
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
186 
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 232 
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
187 
	}
 233 
	}
188 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
 234 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
189 
	WREG32(RADEON_BUS_CNTL, bus_cntl);
 235 
	WREG32(R600_BUS_CNTL, bus_cntl);
190 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 236 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
191 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 237 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
192 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 238 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
193 
	WREG32(R600_ROM_CNTL, rom_cntl);
 239 
	WREG32(R600_ROM_CNTL, rom_cntl);
194 
	return r;
 240 
	return r;
Line 209... Line 255...
209 
	uint32_t ctxsw_vid_lower_gpio_cntl;
 255 
	uint32_t ctxsw_vid_lower_gpio_cntl;
210 
	uint32_t lower_gpio_enable;
 256 
	uint32_t lower_gpio_enable;
211 
	bool r;
 257 
	bool r;
Line 212... Line 258...
212 
 
 258 
 
213 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
 259 
	viph_control = RREG32(RADEON_VIPH_CONTROL);
214 
	bus_cntl = RREG32(RADEON_BUS_CNTL);
 260 
	bus_cntl = RREG32(R600_BUS_CNTL);
215 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 261 
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
216 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 262 
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
217 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 263 
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
218 
	rom_cntl = RREG32(R600_ROM_CNTL);
 264 
	rom_cntl = RREG32(R600_ROM_CNTL);
Line 224... Line 270...
224 
	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 270 
	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
Line 225... Line 271...
225 
 
 271 
 
226 
	/* disable VIP */
 272 
	/* disable VIP */
227 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 273 
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
228 
	/* enable the rom */
 274 
	/* enable the rom */
229 
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 275 
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
230 
	/* Disable VGA mode */
 276 
	/* Disable VGA mode */
231 
	WREG32(AVIVO_D1VGA_CONTROL,
 277 
	WREG32(AVIVO_D1VGA_CONTROL,
232 
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 278 
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
233 
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 279 
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
Line 255... Line 301...
255 
 
 301 
 
Line 256... Line 302...
256 
	r = radeon_read_bios(rdev);
 302 
	r = radeon_read_bios(rdev);
257 
 
 303 
 
258 
	/* restore regs */
 304 
	/* restore regs */
259 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
 305 
	WREG32(RADEON_VIPH_CONTROL, viph_control);
260 
	WREG32(RADEON_BUS_CNTL, bus_cntl);
 306 
	WREG32(R600_BUS_CNTL, bus_cntl);
261 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 307 
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
262 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 308 
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
263 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 309 
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
Line 408... Line 454...
408 
 
 454 
 
409 
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 455 
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
410 
{
 456 
{
411 
	if (rdev->flags & RADEON_IS_IGP)
 457 
	if (rdev->flags & RADEON_IS_IGP)
- 
 
 458 
		return igp_read_bios_from_vram(rdev);
- 
 
 459 
	else if (rdev->family >= CHIP_BARTS)
412 
		return igp_read_bios_from_vram(rdev);
 460 
		return ni_read_disabled_bios(rdev);
413 
	else if (rdev->family >= CHIP_RV770)
 461 
	else if (rdev->family >= CHIP_RV770)
414 
		return r700_read_disabled_bios(rdev);
 462 
		return r700_read_disabled_bios(rdev);
415 
	else if (rdev->family >= CHIP_R600)
 463 
	else if (rdev->family >= CHIP_R600)
416 
		return r600_read_disabled_bios(rdev);
 464 
		return r600_read_disabled_bios(rdev);