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| Rev 1221 | Rev 1268 | ||
|---|---|---|---|
| Line 44... | Line 44... | ||
| 44 | radeon_add_atom_connector(struct drm_device *dev, |
44 | radeon_add_atom_connector(struct drm_device *dev, |
| 45 | uint32_t connector_id, |
45 | uint32_t connector_id, |
| 46 | uint32_t supported_device, |
46 | uint32_t supported_device, |
| 47 | int connector_type, |
47 | int connector_type, |
| 48 | struct radeon_i2c_bus_rec *i2c_bus, |
48 | struct radeon_i2c_bus_rec *i2c_bus, |
| 49 | bool linkb, uint32_t igp_lane_info); |
49 | bool linkb, uint32_t igp_lane_info, |
| - | 50 | uint16_t connector_object_id); |
|
| Line 50... | Line 51... | ||
| 50 | 51 | ||
| 51 | /* from radeon_legacy_encoder.c */ |
52 | /* from radeon_legacy_encoder.c */ |
| 52 | extern void |
53 | extern void |
| 53 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
54 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
| Line 191... | Line 192... | ||
| 191 | DRM_MODE_CONNECTOR_Unknown, |
192 | DRM_MODE_CONNECTOR_Unknown, |
| 192 | DRM_MODE_CONNECTOR_9PinDIN, |
193 | DRM_MODE_CONNECTOR_9PinDIN, |
| 193 | DRM_MODE_CONNECTOR_DisplayPort |
194 | DRM_MODE_CONNECTOR_DisplayPort |
| 194 | }; |
195 | }; |
| Line -... | Line 196... | ||
| - | 196 | ||
| - | 197 | const uint16_t supported_devices_connector_object_id_convert[] = { |
|
| - | 198 | CONNECTOR_OBJECT_ID_NONE, |
|
| - | 199 | CONNECTOR_OBJECT_ID_VGA, |
|
| - | 200 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ |
|
| - | 201 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ |
|
| - | 202 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ |
|
| - | 203 | CONNECTOR_OBJECT_ID_COMPOSITE, |
|
| - | 204 | CONNECTOR_OBJECT_ID_SVIDEO, |
|
| - | 205 | CONNECTOR_OBJECT_ID_LVDS, |
|
| - | 206 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
|
| - | 207 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
|
| - | 208 | CONNECTOR_OBJECT_ID_DISPLAYPORT, |
|
| - | 209 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, |
|
| - | 210 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, |
|
| - | 211 | CONNECTOR_OBJECT_ID_SVIDEO |
|
| - | 212 | }; |
|
| 195 | 213 | ||
| 196 | const int object_connector_convert[] = { |
214 | const int object_connector_convert[] = { |
| 197 | DRM_MODE_CONNECTOR_Unknown, |
215 | DRM_MODE_CONNECTOR_Unknown, |
| 198 | DRM_MODE_CONNECTOR_DVII, |
216 | DRM_MODE_CONNECTOR_DVII, |
| 199 | DRM_MODE_CONNECTOR_DVII, |
217 | DRM_MODE_CONNECTOR_DVII, |
| Line 227... | Line 245... | ||
| 227 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
245 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
| 228 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
246 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
| 229 | ATOM_OBJECT_HEADER *obj_header; |
247 | ATOM_OBJECT_HEADER *obj_header; |
| 230 | int i, j, path_size, device_support; |
248 | int i, j, path_size, device_support; |
| 231 | int connector_type; |
249 | int connector_type; |
| 232 | uint16_t igp_lane_info, conn_id; |
250 | uint16_t igp_lane_info, conn_id, connector_object_id; |
| 233 | bool linkb; |
251 | bool linkb; |
| 234 | struct radeon_i2c_bus_rec ddc_bus; |
252 | struct radeon_i2c_bus_rec ddc_bus; |
| Line 235... | Line 253... | ||
| 235 | 253 | ||
| Line 275... | Line 293... | ||
| 275 | /* TODO CV support */ |
293 | /* TODO CV support */ |
| 276 | if (le16_to_cpu(path->usDeviceTag) == |
294 | if (le16_to_cpu(path->usDeviceTag) == |
| 277 | ATOM_DEVICE_CV_SUPPORT) |
295 | ATOM_DEVICE_CV_SUPPORT) |
| 278 | continue; |
296 | continue; |
| Line -... | Line 297... | ||
| - | 297 | ||
| 279 | 298 | /* IGP chips */ |
|
| 280 | if ((rdev->family == CHIP_RS780) && |
299 | if ((rdev->flags & RADEON_IS_IGP) && |
| 281 | (con_obj_id == |
300 | (con_obj_id == |
| 282 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
301 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
| 283 | uint16_t igp_offset = 0; |
302 | uint16_t igp_offset = 0; |
| Line 309... | Line 328... | ||
| 309 | 328 | ||
| 310 | ct = (slot_config >> 16) & 0xff; |
329 | ct = (slot_config >> 16) & 0xff; |
| 311 | connector_type = |
330 | connector_type = |
| 312 | object_connector_convert |
331 | object_connector_convert |
| - | 332 | [ct]; |
|
| 313 | [ct]; |
333 | connector_object_id = ct; |
| 314 | igp_lane_info = |
334 | igp_lane_info = |
| 315 | slot_config & 0xffff; |
335 | slot_config & 0xffff; |
| 316 | } else |
336 | } else |
| 317 | continue; |
337 | continue; |
| 318 | } else |
338 | } else |
| 319 | continue; |
339 | continue; |
| 320 | } else { |
340 | } else { |
| 321 | igp_lane_info = 0; |
341 | igp_lane_info = 0; |
| 322 | connector_type = |
342 | connector_type = |
| - | 343 | object_connector_convert[con_obj_id]; |
|
| 323 | object_connector_convert[con_obj_id]; |
344 | connector_object_id = con_obj_id; |
| Line 324... | Line 345... | ||
| 324 | } |
345 | } |
| 325 | 346 | ||
| Line 423... | Line 444... | ||
| 423 | radeon_add_atom_connector(dev, |
444 | radeon_add_atom_connector(dev, |
| 424 | conn_id, |
445 | conn_id, |
| 425 | le16_to_cpu(path-> |
446 | le16_to_cpu(path-> |
| 426 | usDeviceTag), |
447 | usDeviceTag), |
| 427 | connector_type, &ddc_bus, |
448 | connector_type, &ddc_bus, |
| 428 | linkb, igp_lane_info); |
449 | linkb, igp_lane_info, |
| - | 450 | connector_object_id); |
|
| Line 429... | Line 451... | ||
| 429 | 451 | ||
| 430 | } |
452 | } |
| Line 431... | Line 453... | ||
| 431 | } |
453 | } |
| Line 432... | Line 454... | ||
| 432 | 454 | ||
| 433 | radeon_link_encoder_connector(dev); |
455 | radeon_link_encoder_connector(dev); |
| Line -... | Line 456... | ||
| - | 456 | ||
| - | 457 | return true; |
|
| - | 458 | } |
|
| - | 459 | ||
| - | 460 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
|
| - | 461 | int connector_type, |
|
| - | 462 | uint16_t devices) |
|
| - | 463 | { |
|
| - | 464 | struct radeon_device *rdev = dev->dev_private; |
|
| - | 465 | ||
| - | 466 | if (rdev->flags & RADEON_IS_IGP) { |
|
| - | 467 | return supported_devices_connector_object_id_convert |
|
| - | 468 | [connector_type]; |
|
| - | 469 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || |
|
| - | 470 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && |
|
| - | 471 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
|
| - | 472 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
|
| - | 473 | struct atom_context *ctx = mode_info->atom_context; |
|
| - | 474 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); |
|
| - | 475 | uint16_t size, data_offset; |
|
| - | 476 | uint8_t frev, crev; |
|
| - | 477 | ATOM_XTMDS_INFO *xtmds; |
|
| - | 478 | ||
| - | 479 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
|
| - | 480 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); |
|
| - | 481 | ||
| - | 482 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
|
| - | 483 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
|
| - | 484 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
|
| - | 485 | else |
|
| - | 486 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
|
| - | 487 | } else { |
|
| - | 488 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
|
| - | 489 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
|
| - | 490 | else |
|
| - | 491 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
|
| - | 492 | } |
|
| - | 493 | } else { |
|
| - | 494 | return supported_devices_connector_object_id_convert |
|
| 434 | 495 | [connector_type]; |
|
| 435 | return true; |
496 | } |
| 436 | } |
497 | } |
| 437 | 498 | ||
| 438 | struct bios_connector { |
499 | struct bios_connector { |
| Line 591... | Line 652... | ||
| 591 | } |
652 | } |
| 592 | } |
653 | } |
| Line 593... | Line 654... | ||
| 593 | 654 | ||
| 594 | /* add the connectors */ |
655 | /* add the connectors */ |
| 595 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
656 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| - | 657 | if (bios_connectors[i].valid) { |
|
| - | 658 | uint16_t connector_object_id = |
|
| - | 659 | atombios_get_connector_object_id(dev, |
|
| - | 660 | bios_connectors[i].connector_type, |
|
| 596 | if (bios_connectors[i].valid) |
661 | bios_connectors[i].devices); |
| 597 | radeon_add_atom_connector(dev, |
662 | radeon_add_atom_connector(dev, |
| 598 | bios_connectors[i].line_mux, |
663 | bios_connectors[i].line_mux, |
| 599 | bios_connectors[i].devices, |
664 | bios_connectors[i].devices, |
| 600 | bios_connectors[i]. |
665 | bios_connectors[i]. |
| 601 | connector_type, |
666 | connector_type, |
| 602 | &bios_connectors[i].ddc_bus, |
667 | &bios_connectors[i].ddc_bus, |
| - | 668 | false, 0, |
|
| - | 669 | connector_object_id); |
|
| 603 | false, 0); |
670 | } |
| Line 604... | Line 671... | ||
| 604 | } |
671 | } |
| Line 605... | Line 672... | ||
| 605 | 672 | ||
| Line 639... | Line 706... | ||
| 639 | /* pixel clocks */ |
706 | /* pixel clocks */ |
| 640 | p1pll->reference_freq = |
707 | p1pll->reference_freq = |
| 641 | le16_to_cpu(firmware_info->info.usReferenceClock); |
708 | le16_to_cpu(firmware_info->info.usReferenceClock); |
| 642 | p1pll->reference_div = 0; |
709 | p1pll->reference_div = 0; |
| Line -... | Line 710... | ||
| - | 710 | ||
| 643 | 711 | if (crev < 2) |
|
| 644 | p1pll->pll_out_min = |
712 | p1pll->pll_out_min = |
| - | 713 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
|
| - | 714 | else |
|
| - | 715 | p1pll->pll_out_min = |
|
| 645 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
716 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); |
| 646 | p1pll->pll_out_max = |
717 | p1pll->pll_out_max = |
| Line 647... | Line 718... | ||
| 647 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
718 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
| 648 | 719 | ||
| 649 | if (p1pll->pll_out_min == 0) { |
720 | if (p1pll->pll_out_min == 0) { |
| 650 | if (ASIC_IS_AVIVO(rdev)) |
721 | if (ASIC_IS_AVIVO(rdev)) |
| 651 | p1pll->pll_out_min = 64800; |
722 | p1pll->pll_out_min = 64800; |
| - | 723 | else |
|
| - | 724 | p1pll->pll_out_min = 20000; |
|
| - | 725 | } else if (p1pll->pll_out_min > 64800) { |
|
| - | 726 | /* Limiting the pll output range is a good thing generally as |
|
| - | 727 | * it limits the number of possible pll combinations for a given |
|
| - | 728 | * frequency presumably to the ones that work best on each card. |
|
| - | 729 | * However, certain duallink DVI monitors seem to like |
|
| - | 730 | * pll combinations that would be limited by this at least on |
|
| - | 731 | * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per |
|
| - | 732 | * family. |
|
| 652 | else |
733 | */ |
| Line 653... | Line 734... | ||
| 653 | p1pll->pll_out_min = 20000; |
734 | p1pll->pll_out_min = 64800; |
| 654 | } |
735 | } |
| 655 | 736 | ||
| Line 765... | Line 846... | ||
| 765 | return true; |
846 | return true; |
| 766 | } |
847 | } |
| 767 | return false; |
848 | return false; |
| 768 | } |
849 | } |
| Line -... | Line 850... | ||
| - | 850 | ||
| - | 851 | static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct |
|
| - | 852 | radeon_encoder |
|
| - | 853 | *encoder, |
|
| - | 854 | int id) |
|
| - | 855 | { |
|
| - | 856 | struct drm_device *dev = encoder->base.dev; |
|
| - | 857 | struct radeon_device *rdev = dev->dev_private; |
|
| - | 858 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
|
| - | 859 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); |
|
| - | 860 | uint16_t data_offset; |
|
| - | 861 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; |
|
| - | 862 | uint8_t frev, crev; |
|
| - | 863 | struct radeon_atom_ss *ss = NULL; |
|
| - | 864 | ||
| - | 865 | if (id > ATOM_MAX_SS_ENTRY) |
|
| - | 866 | return NULL; |
|
| - | 867 | ||
| - | 868 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
|
| - | 869 | &crev, &data_offset); |
|
| - | 870 | ||
| - | 871 | ss_info = |
|
| - | 872 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); |
|
| - | 873 | ||
| - | 874 | if (ss_info) { |
|
| - | 875 | ss = |
|
| - | 876 | kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL); |
|
| - | 877 | ||
| - | 878 | if (!ss) |
|
| - | 879 | return NULL; |
|
| - | 880 | ||
| - | 881 | ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage); |
|
| - | 882 | ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType; |
|
| - | 883 | ss->step = ss_info->asSS_Info[id].ucSS_Step; |
|
| - | 884 | ss->delay = ss_info->asSS_Info[id].ucSS_Delay; |
|
| - | 885 | ss->range = ss_info->asSS_Info[id].ucSS_Range; |
|
| - | 886 | ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div; |
|
| - | 887 | } |
|
| - | 888 | return ss; |
|
| - | 889 | } |
|
| 769 | 890 | ||
| 770 | union lvds_info { |
891 | union lvds_info { |
| 771 | struct _ATOM_LVDS_INFO info; |
892 | struct _ATOM_LVDS_INFO info; |
| 772 | struct _ATOM_LVDS_INFO_V12 info_12; |
893 | struct _ATOM_LVDS_INFO_V12 info_12; |
| Line 796... | Line 917... | ||
| 796 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
917 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| Line 797... | Line 918... | ||
| 797 | 918 | ||
| 798 | if (!lvds) |
919 | if (!lvds) |
| Line 799... | Line 920... | ||
| 799 | return NULL; |
920 | return NULL; |
| 800 | 921 | ||
| 801 | lvds->native_mode.dotclock = |
922 | lvds->native_mode.clock = |
| 802 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
923 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
| 803 | lvds->native_mode.panel_xres = |
924 | lvds->native_mode.hdisplay = |
| 804 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
925 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
| 805 | lvds->native_mode.panel_yres = |
926 | lvds->native_mode.vdisplay = |
| 806 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
927 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
| 807 | lvds->native_mode.hblank = |
928 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
| 808 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
929 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
| 809 | lvds->native_mode.hoverplus = |
930 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
| 810 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
931 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
| 811 | lvds->native_mode.hsync_width = |
932 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
| 812 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
933 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
| 813 | lvds->native_mode.vblank = |
934 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
| 814 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
935 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
| 815 | lvds->native_mode.voverplus = |
936 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
| 816 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
937 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
| 817 | lvds->native_mode.vsync_width = |
938 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
| 818 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
939 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
| 819 | lvds->panel_pwr_delay = |
940 | lvds->panel_pwr_delay = |
| - | 941 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
|
| - | 942 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; |
|
| - | 943 | /* set crtc values */ |
|
| - | 944 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
|
| Line 820... | Line 945... | ||
| 820 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
945 | |
| 821 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; |
946 | lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); |
| 822 | 947 | ||
| 823 | encoder->native_mode = lvds->native_mode; |
948 | encoder->native_mode = lvds->native_mode; |
| Line 855... | Line 980... | ||
| 855 | } |
980 | } |
| 856 | return p_dac; |
981 | return p_dac; |
| 857 | } |
982 | } |
| Line 858... | Line 983... | ||
| 858 | 983 | ||
| 859 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
- | |
| 860 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
984 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
| 861 | int32_t *pixel_clock) |
985 | struct drm_display_mode *mode) |
| 862 | { |
986 | { |
| 863 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
987 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 864 | ATOM_ANALOG_TV_INFO *tv_info; |
988 | ATOM_ANALOG_TV_INFO *tv_info; |
| 865 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
989 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
| 866 | ATOM_DTD_FORMAT *dtd_timings; |
990 | ATOM_DTD_FORMAT *dtd_timings; |
| 867 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
991 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
| 868 | u8 frev, crev; |
992 | u8 frev, crev; |
| Line 869... | Line 993... | ||
| 869 | uint16_t data_offset; |
993 | u16 data_offset, misc; |
| Line 870... | Line 994... | ||
| 870 | 994 | ||
| 871 | atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); |
995 | atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); |
| 872 | 996 | ||
| 873 | switch (crev) { |
997 | switch (crev) { |
| 874 | case 1: |
998 | case 1: |
| Line 875... | Line 999... | ||
| 875 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
999 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
| 876 | if (index > MAX_SUPPORTED_TV_TIMING) |
1000 | if (index > MAX_SUPPORTED_TV_TIMING) |
| 877 | return false; |
1001 | return false; |
| 878 | 1002 | ||
| - | 1003 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
|
| 879 | crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
1004 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
| 880 | crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
1005 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
| 881 | crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
1006 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + |
| 882 | crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
1007 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
| 883 | 1008 | ||
| 884 | crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
- | |
| 885 | crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
1009 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
| 886 | crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
1010 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
| - | 1011 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
|
| 887 | crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
1012 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + |
| - | 1013 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
|
| - | 1014 | ||
| - | 1015 | mode->flags = 0; |
|
| - | 1016 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); |
|
| - | 1017 | if (misc & ATOM_VSYNC_POLARITY) |
|
| - | 1018 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
|
| - | 1019 | if (misc & ATOM_HSYNC_POLARITY) |
|
| 888 | 1020 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
|
| 889 | crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; |
1021 | if (misc & ATOM_COMPOSITESYNC) |
| 890 | 1022 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
|
| - | 1023 | if (misc & ATOM_INTERLACE) |
|
| 891 | crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); |
1024 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| Line 892... | Line 1025... | ||
| 892 | crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); |
1025 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 893 | crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); |
1026 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
| 894 | crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); |
1027 | |
| 895 | *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
1028 | mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
| 896 | 1029 | ||
| 897 | if (index == 1) { |
1030 | if (index == 1) { |
| 898 | /* PAL timings appear to have wrong values for totals */ |
1031 | /* PAL timings appear to have wrong values for totals */ |
| 899 | crtc_timing->usH_Total -= 1; |
1032 | mode->crtc_htotal -= 1; |
| 900 | crtc_timing->usV_Total -= 1; |
1033 | mode->crtc_vtotal -= 1; |
| 901 | } |
1034 | } |
| Line 902... | Line 1035... | ||
| 902 | break; |
1035 | break; |
| 903 | case 2: |
1036 | case 2: |
| - | 1037 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
|
| 904 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
1038 | if (index > MAX_SUPPORTED_TV_TIMING_V1_2) |
| 905 | if (index > MAX_SUPPORTED_TV_TIMING_V1_2) |
1039 | return false; |
| - | 1040 | ||
| - | 1041 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
|
| 906 | return false; |
1042 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
| - | 1043 | le16_to_cpu(dtd_timings->usHBlanking_Time); |
|
| 907 | 1044 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); |
|
| - | 1045 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + |
|
| 908 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
1046 | le16_to_cpu(dtd_timings->usHSyncOffset); |
| 909 | crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); |
1047 | mode->crtc_hsync_end = mode->crtc_hsync_start + |
| - | 1048 | le16_to_cpu(dtd_timings->usHSyncWidth); |
|
| - | 1049 | ||
| 910 | crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); |
1050 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + |
| - | 1051 | le16_to_cpu(dtd_timings->usVBlanking_Time); |
|
| - | 1052 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); |
|
| - | 1053 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + |
|
| - | 1054 | le16_to_cpu(dtd_timings->usVSyncOffset); |
|
| - | 1055 | mode->crtc_vsync_end = mode->crtc_vsync_start + |
|
| - | 1056 | le16_to_cpu(dtd_timings->usVSyncWidth); |
|
| - | 1057 | ||
| - | 1058 | mode->flags = 0; |
|
| - | 1059 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); |
|
| - | 1060 | if (misc & ATOM_VSYNC_POLARITY) |
|
| - | 1061 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
|
| - | 1062 | if (misc & ATOM_HSYNC_POLARITY) |
|
| - | 1063 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
|
| Line 911... | Line -... | ||
| 911 | crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); |
- | |
| 912 | crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); |
1064 | if (misc & ATOM_COMPOSITESYNC) |
| 913 | crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); |
1065 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
| 914 | crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); |
1066 | if (misc & ATOM_INTERLACE) |
| 915 | crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); |
1067 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 916 | crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); |
1068 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| Line 979... | Line 1131... | ||
| 979 | args.ucEnable = enable; |
1131 | args.ucEnable = enable; |
| Line 980... | Line 1132... | ||
| 980 | 1132 | ||
| 981 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1133 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| Line -... | Line 1134... | ||
| - | 1134 | } |
|
| - | 1135 | ||
| - | 1136 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
|
| - | 1137 | { |
|
| - | 1138 | GET_ENGINE_CLOCK_PS_ALLOCATION args; |
|
| - | 1139 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); |
|
| - | 1140 | ||
| - | 1141 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
| - | 1142 | return args.ulReturnEngineClock; |
|
| - | 1143 | } |
|
| - | 1144 | ||
| - | 1145 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) |
|
| - | 1146 | { |
|
| - | 1147 | GET_MEMORY_CLOCK_PS_ALLOCATION args; |
|
| - | 1148 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); |
|
| - | 1149 | ||
| - | 1150 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
|
| - | 1151 | return args.ulReturnMemoryClock; |
|
| 982 | } |
1152 | } |
| 983 | 1153 | ||
| 984 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
1154 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
| 985 | uint32_t eng_clock) |
1155 | uint32_t eng_clock) |
| 986 | { |
1156 | { |