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| Rev 2997 | Rev 3192 | ||
|---|---|---|---|
| Line 261... | Line 261... | ||
| 261 | * rv515 |
261 | * rv515 |
| 262 | */ |
262 | */ |
| 263 | struct rv515_mc_save { |
263 | struct rv515_mc_save { |
| 264 | u32 vga_render_control; |
264 | u32 vga_render_control; |
| 265 | u32 vga_hdp_control; |
265 | u32 vga_hdp_control; |
| - | 266 | bool crtc_enabled[2]; |
|
| 266 | }; |
267 | }; |
| Line 267... | Line 268... | ||
| 267 | 268 | ||
| 268 | int rv515_init(struct radeon_device *rdev); |
269 | int rv515_init(struct radeon_device *rdev); |
| 269 | void rv515_fini(struct radeon_device *rdev); |
270 | void rv515_fini(struct radeon_device *rdev); |
| Line 301... | Line 302... | ||
| 301 | void r600_wb_fini(struct radeon_device *rdev); |
302 | void r600_wb_fini(struct radeon_device *rdev); |
| 302 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
303 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 303 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
304 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 304 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
305 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 305 | int r600_cs_parse(struct radeon_cs_parser *p); |
306 | int r600_cs_parse(struct radeon_cs_parser *p); |
| - | 307 | int r600_dma_cs_parse(struct radeon_cs_parser *p); |
|
| 306 | void r600_fence_ring_emit(struct radeon_device *rdev, |
308 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 307 | struct radeon_fence *fence); |
309 | struct radeon_fence *fence); |
| 308 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
310 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
| 309 | struct radeon_ring *cp, |
311 | struct radeon_ring *cp, |
| 310 | struct radeon_semaphore *semaphore, |
312 | struct radeon_semaphore *semaphore, |
| 311 | bool emit_wait); |
313 | bool emit_wait); |
| - | 314 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
|
| - | 315 | struct radeon_fence *fence); |
|
| - | 316 | void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
|
| - | 317 | struct radeon_ring *ring, |
|
| - | 318 | struct radeon_semaphore *semaphore, |
|
| - | 319 | bool emit_wait); |
|
| - | 320 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
|
| - | 321 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
|
| 312 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
322 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| 313 | int r600_asic_reset(struct radeon_device *rdev); |
323 | int r600_asic_reset(struct radeon_device *rdev); |
| 314 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
324 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 315 | uint32_t tiling_flags, uint32_t pitch, |
325 | uint32_t tiling_flags, uint32_t pitch, |
| 316 | uint32_t offset, uint32_t obj_size); |
326 | uint32_t offset, uint32_t obj_size); |
| 317 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
327 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| 318 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
328 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| - | 329 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
|
| 319 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
330 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 320 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
331 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| - | 332 | int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
|
| 321 | int r600_copy_blit(struct radeon_device *rdev, |
333 | int r600_copy_blit(struct radeon_device *rdev, |
| 322 | uint64_t src_offset, uint64_t dst_offset, |
334 | uint64_t src_offset, uint64_t dst_offset, |
| 323 | unsigned num_gpu_pages, struct radeon_fence **fence); |
335 | unsigned num_gpu_pages, struct radeon_fence **fence); |
| - | 336 | int r600_copy_dma(struct radeon_device *rdev, |
|
| - | 337 | uint64_t src_offset, uint64_t dst_offset, |
|
| - | 338 | unsigned num_gpu_pages, struct radeon_fence **fence); |
|
| 324 | void r600_hpd_init(struct radeon_device *rdev); |
339 | void r600_hpd_init(struct radeon_device *rdev); |
| 325 | void r600_hpd_fini(struct radeon_device *rdev); |
340 | void r600_hpd_fini(struct radeon_device *rdev); |
| 326 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
341 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 327 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
342 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
| 328 | enum radeon_hpd_id hpd); |
343 | enum radeon_hpd_id hpd); |
| Line 386... | Line 401... | ||
| 386 | void rv770_pm_misc(struct radeon_device *rdev); |
401 | void rv770_pm_misc(struct radeon_device *rdev); |
| 387 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
402 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 388 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
403 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
| 389 | void r700_cp_stop(struct radeon_device *rdev); |
404 | void r700_cp_stop(struct radeon_device *rdev); |
| 390 | void r700_cp_fini(struct radeon_device *rdev); |
405 | void r700_cp_fini(struct radeon_device *rdev); |
| - | 406 | int rv770_copy_dma(struct radeon_device *rdev, |
|
| - | 407 | uint64_t src_offset, uint64_t dst_offset, |
|
| - | 408 | unsigned num_gpu_pages, |
|
| - | 409 | struct radeon_fence **fence); |
|
| Line 391... | Line 410... | ||
| 391 | 410 | ||
| 392 | /* |
411 | /* |
| 393 | * evergreen |
412 | * evergreen |
| 394 | */ |
413 | */ |
| Line 414... | Line 433... | ||
| 414 | enum radeon_hpd_id hpd); |
433 | enum radeon_hpd_id hpd); |
| 415 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
434 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 416 | int evergreen_irq_set(struct radeon_device *rdev); |
435 | int evergreen_irq_set(struct radeon_device *rdev); |
| 417 | int evergreen_irq_process(struct radeon_device *rdev); |
436 | int evergreen_irq_process(struct radeon_device *rdev); |
| 418 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
437 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| - | 438 | extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); |
|
| 419 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
439 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 420 | extern void evergreen_pm_prepare(struct radeon_device *rdev); |
440 | extern void evergreen_pm_prepare(struct radeon_device *rdev); |
| 421 | extern void evergreen_pm_finish(struct radeon_device *rdev); |
441 | extern void evergreen_pm_finish(struct radeon_device *rdev); |
| 422 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
442 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 423 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
443 | extern void btc_pm_init_profile(struct radeon_device *rdev); |
| Line 426... | Line 446... | ||
| 426 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); |
446 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); |
| 427 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
447 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 428 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
448 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 429 | int evergreen_blit_init(struct radeon_device *rdev); |
449 | int evergreen_blit_init(struct radeon_device *rdev); |
| 430 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
450 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| - | 451 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, |
|
| - | 452 | struct radeon_fence *fence); |
|
| - | 453 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, |
|
| - | 454 | struct radeon_ib *ib); |
|
| - | 455 | int evergreen_copy_dma(struct radeon_device *rdev, |
|
| - | 456 | uint64_t src_offset, uint64_t dst_offset, |
|
| - | 457 | unsigned num_gpu_pages, |
|
| - | 458 | struct radeon_fence **fence); |
|
| Line 431... | Line 459... | ||
| 431 | 459 | ||
| 432 | /* |
460 | /* |
| 433 | * cayman |
461 | * cayman |
| 434 | */ |
462 | */ |
| Line 447... | Line 475... | ||
| 447 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
475 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); |
| 448 | void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
476 | void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, |
| 449 | uint64_t addr, unsigned count, |
477 | uint64_t addr, unsigned count, |
| 450 | uint32_t incr, uint32_t flags); |
478 | uint32_t incr, uint32_t flags); |
| 451 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
479 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| - | 480 | int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
|
| - | 481 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
|
| - | 482 | struct radeon_ib *ib); |
|
| - | 483 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
|
| - | 484 | void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
|
| Line 452... | Line 485... | ||
| 452 | 485 | ||
| 453 | /* DCE6 - SI */ |
486 | /* DCE6 - SI */ |
| Line 454... | Line 487... | ||
| 454 | void dce6_bandwidth_update(struct radeon_device *rdev); |
487 | void dce6_bandwidth_update(struct radeon_device *rdev); |
| Line 474... | Line 507... | ||
| 474 | uint64_t addr, unsigned count, |
507 | uint64_t addr, unsigned count, |
| 475 | uint32_t incr, uint32_t flags); |
508 | uint32_t incr, uint32_t flags); |
| 476 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
509 | void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 477 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
510 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 478 | uint64_t si_get_gpu_clock(struct radeon_device *rdev); |
511 | uint64_t si_get_gpu_clock(struct radeon_device *rdev); |
| - | 512 | int si_copy_dma(struct radeon_device *rdev, |
|
| - | 513 | uint64_t src_offset, uint64_t dst_offset, |
|
| - | 514 | unsigned num_gpu_pages, |
|
| - | 515 | struct radeon_fence **fence); |
|
| - | 516 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
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| Line 479... | Line 517... | ||
| 479 | 517 | ||