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Rev 1413 Rev 1430
Line 41... Line 41...
41 
uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
 41 
uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42 
void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
 42 
void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43 
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 43 
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Line 44... Line 44...
44 
 
 44 
 
45 
/*
 45 
/*
46 
 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
 46 
 * r100,rv100,rs100,rv200,rs200
47 
 */
 47 
 */
48 
extern int r100_init(struct radeon_device *rdev);
 48 
extern int r100_init(struct radeon_device *rdev);
49 
extern void r100_fini(struct radeon_device *rdev);
 49 
extern void r100_fini(struct radeon_device *rdev);
50 
extern int r100_suspend(struct radeon_device *rdev);
 50 
extern int r100_suspend(struct radeon_device *rdev);
Line 106... Line 106...
106 
//	.copy = &r100_copy_blit,
 106 
//	.copy = &r100_copy_blit,
107 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 107 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
108 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 108 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
109 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 109 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
110 
	.set_memory_clock = NULL,
 110 
	.set_memory_clock = NULL,
- 
 
 111 
	.get_pcie_lanes = NULL,
- 
 
 112 
	.set_pcie_lanes = NULL,
- 
 
 113 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
- 
 
 114 
	.set_surface_reg = r100_set_surface_reg,
- 
 
 115 
	.clear_surface_reg = r100_clear_surface_reg,
- 
 
 116 
	.bandwidth_update = &r100_bandwidth_update,
- 
 
 117 
	.hpd_init = &r100_hpd_init,
- 
 
 118 
	.hpd_fini = &r100_hpd_fini,
- 
 
 119 
	.hpd_sense = &r100_hpd_sense,
- 
 
 120 
	.hpd_set_polarity = &r100_hpd_set_polarity,
- 
 
 121 
	.ioctl_wait_idle = NULL,
- 
 
 122 
};
- 
 
 123 
 
- 
 
 124 
/*
- 
 
 125 
 * r200,rv250,rs300,rv280
- 
 
 126 
 */
- 
 
 127 
extern int r200_copy_dma(struct radeon_device *rdev,
- 
 
 128 
			uint64_t src_offset,
- 
 
 129 
			uint64_t dst_offset,
- 
 
 130 
			unsigned num_pages,
- 
 
 131 
			struct radeon_fence *fence);
- 
 
 132 
static struct radeon_asic r200_asic = {
- 
 
 133 
	.init = &r100_init,
- 
 
 134 
//	.fini = &r100_fini,
- 
 
 135 
//	.suspend = &r100_suspend,
- 
 
 136 
//	.resume = &r100_resume,
- 
 
 137 
//	.vga_set_state = &r100_vga_set_state,
- 
 
 138 
	.gpu_reset = &r100_gpu_reset,
- 
 
 139 
	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
- 
 
 140 
	.gart_set_page = &r100_pci_gart_set_page,
- 
 
 141 
	.cp_commit = &r100_cp_commit,
- 
 
 142 
	.ring_start = &r100_ring_start,
- 
 
 143 
    .ring_test = &r100_ring_test,
- 
 
 144 
//	.ring_ib_execute = &r100_ring_ib_execute,
- 
 
 145 
//	.irq_set = &r100_irq_set,
- 
 
 146 
//	.irq_process = &r100_irq_process,
- 
 
 147 
//	.get_vblank_counter = &r100_get_vblank_counter,
- 
 
 148 
	.fence_ring_emit = &r100_fence_ring_emit,
- 
 
 149 
//	.cs_parse = &r100_cs_parse,
- 
 
 150 
//	.copy_blit = &r100_copy_blit,
- 
 
 151 
//	.copy_dma = NULL,
- 
 
 152 
//	.copy = &r100_copy_blit,
- 
 
 153 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
- 
 
 154 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
- 
 
 155 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
- 
 
 156 
	.set_memory_clock = NULL,
111 
	.set_pcie_lanes = NULL,
 157 
	.set_pcie_lanes = NULL,
112 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 158 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
113 
	.set_surface_reg = r100_set_surface_reg,
 159 
	.set_surface_reg = r100_set_surface_reg,
114 
	.clear_surface_reg = r100_clear_surface_reg,
 160 
	.clear_surface_reg = r100_clear_surface_reg,
115 
	.bandwidth_update = &r100_bandwidth_update,
 161 
	.bandwidth_update = &r100_bandwidth_update,
Line 136... Line 182...
136 
extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 182 
extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
137 
extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 183 
extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
138 
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 184 
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
139 
extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 185 
extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
140 
extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 186 
extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
141 
extern int r300_copy_dma(struct radeon_device *rdev,
 187 
extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
142 
		  uint64_t src_offset,
 - 
 
143 
		  uint64_t dst_offset,
 - 
 
144 
		  unsigned num_pages,
 - 
 
145 
		  struct radeon_fence *fence);
 - 
 
- 
 
 188 
 
146 
static struct radeon_asic r300_asic = {
 189 
static struct radeon_asic r300_asic = {
147 
	.init = &r300_init,
 190 
	.init = &r300_init,
148 
//	.fini = &r300_fini,
 191 
//	.fini = &r300_fini,
149 
//	.suspend = &r300_suspend,
 192 
//	.suspend = &r300_suspend,
150 
//	.resume = &r300_resume,
 193 
//	.resume = &r300_resume,
Line 166... Line 209...
166 
//	.copy = &r100_copy_blit,
 209 
//	.copy = &r100_copy_blit,
167 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 210 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
168 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 211 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
169 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 212 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
170 
	.set_memory_clock = NULL,
 213 
	.set_memory_clock = NULL,
- 
 
 214 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
- 
 
 215 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
- 
 
 216 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
- 
 
 217 
	.set_surface_reg = r100_set_surface_reg,
- 
 
 218 
	.clear_surface_reg = r100_clear_surface_reg,
- 
 
 219 
	.bandwidth_update = &r100_bandwidth_update,
- 
 
 220 
	.hpd_init = &r100_hpd_init,
- 
 
 221 
	.hpd_fini = &r100_hpd_fini,
- 
 
 222 
	.hpd_sense = &r100_hpd_sense,
- 
 
 223 
	.hpd_set_polarity = &r100_hpd_set_polarity,
- 
 
 224 
	.ioctl_wait_idle = NULL,
- 
 
 225 
};
- 
 
 226 
 
- 
 
 227 
 
- 
 
 228 
static struct radeon_asic r300_asic_pcie = {
- 
 
 229 
	.init = &r300_init,
- 
 
 230 
//	.fini = &r300_fini,
- 
 
 231 
//	.suspend = &r300_suspend,
- 
 
 232 
//	.resume = &r300_resume,
- 
 
 233 
//	.vga_set_state = &r100_vga_set_state,
- 
 
 234 
	.gpu_reset = &r300_gpu_reset,
- 
 
 235 
	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
- 
 
 236 
	.gart_set_page = &rv370_pcie_gart_set_page,
- 
 
 237 
	.cp_commit = &r100_cp_commit,
- 
 
 238 
	.ring_start = &r300_ring_start,
- 
 
 239 
    .ring_test = &r100_ring_test,
- 
 
 240 
//	.ring_ib_execute = &r100_ring_ib_execute,
- 
 
 241 
//	.irq_set = &r100_irq_set,
- 
 
 242 
//	.irq_process = &r100_irq_process,
- 
 
 243 
//	.get_vblank_counter = &r100_get_vblank_counter,
- 
 
 244 
	.fence_ring_emit = &r300_fence_ring_emit,
- 
 
 245 
//	.cs_parse = &r300_cs_parse,
- 
 
 246 
//	.copy_blit = &r100_copy_blit,
- 
 
 247 
//	.copy_dma = &r300_copy_dma,
- 
 
 248 
//	.copy = &r100_copy_blit,
- 
 
 249 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
- 
 
 250 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
- 
 
 251 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
- 
 
 252 
	.set_memory_clock = NULL,
171 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 253 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
172 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 254 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
173 
	.set_surface_reg = r100_set_surface_reg,
 255 
	.set_surface_reg = r100_set_surface_reg,
174 
	.clear_surface_reg = r100_clear_surface_reg,
 256 
	.clear_surface_reg = r100_clear_surface_reg,
175 
	.bandwidth_update = &r100_bandwidth_update,
 257 
	.bandwidth_update = &r100_bandwidth_update,
Line 210... Line 292...
210 
//	.copy = &r100_copy_blit,
 292 
//	.copy = &r100_copy_blit,
211 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 293 
	.get_engine_clock = &radeon_atom_get_engine_clock,
212 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 294 
	.set_engine_clock = &radeon_atom_set_engine_clock,
213 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 295 
	.get_memory_clock = &radeon_atom_get_memory_clock,
214 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 296 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 297 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
215 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 298 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
216 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 299 
	.set_clock_gating = &radeon_atom_set_clock_gating,
217 
	.set_surface_reg = r100_set_surface_reg,
 300 
	.set_surface_reg = r100_set_surface_reg,
218 
	.clear_surface_reg = r100_clear_surface_reg,
 301 
	.clear_surface_reg = r100_clear_surface_reg,
219 
	.bandwidth_update = &r100_bandwidth_update,
 302 
	.bandwidth_update = &r100_bandwidth_update,
Line 259... Line 342...
259 
//	.copy = &r100_copy_blit,
 342 
//	.copy = &r100_copy_blit,
260 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
 343 
	.get_engine_clock = &radeon_legacy_get_engine_clock,
261 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
 344 
	.set_engine_clock = &radeon_legacy_set_engine_clock,
262 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
 345 
	.get_memory_clock = &radeon_legacy_get_memory_clock,
263 
	.set_memory_clock = NULL,
 346 
	.set_memory_clock = NULL,
- 
 
 347 
	.get_pcie_lanes = NULL,
264 
	.set_pcie_lanes = NULL,
 348 
	.set_pcie_lanes = NULL,
265 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
 349 
	.set_clock_gating = &radeon_legacy_set_clock_gating,
266 
	.set_surface_reg = r100_set_surface_reg,
 350 
	.set_surface_reg = r100_set_surface_reg,
267 
	.clear_surface_reg = r100_clear_surface_reg,
 351 
	.clear_surface_reg = r100_clear_surface_reg,
268 
	.bandwidth_update = &r100_bandwidth_update,
 352 
	.bandwidth_update = &r100_bandwidth_update,
Line 318... Line 402...
318 
//   .copy = &r100_copy_blit,
 402 
//   .copy = &r100_copy_blit,
319 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 403 
	.get_engine_clock = &radeon_atom_get_engine_clock,
320 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 404 
	.set_engine_clock = &radeon_atom_set_engine_clock,
321 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 405 
	.get_memory_clock = &radeon_atom_get_memory_clock,
322 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 406 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 407 
	.get_pcie_lanes = NULL,
323 
	.set_pcie_lanes = NULL,
 408 
	.set_pcie_lanes = NULL,
324 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 409 
	.set_clock_gating = &radeon_atom_set_clock_gating,
- 
 
 410 
	.set_surface_reg = r100_set_surface_reg,
- 
 
 411 
	.clear_surface_reg = r100_clear_surface_reg,
325 
	.bandwidth_update = &rs600_bandwidth_update,
 412 
	.bandwidth_update = &rs600_bandwidth_update,
326 
	.hpd_init = &rs600_hpd_init,
 413 
	.hpd_init = &rs600_hpd_init,
327 
	.hpd_fini = &rs600_hpd_fini,
 414 
	.hpd_fini = &rs600_hpd_fini,
328 
	.hpd_sense = &rs600_hpd_sense,
 415 
	.hpd_sense = &rs600_hpd_sense,
329 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
 416 
	.hpd_set_polarity = &rs600_hpd_set_polarity,
Line 364... Line 451...
364 
//	.copy = &r300_copy_dma,
 451 
//	.copy = &r300_copy_dma,
365 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 452 
	.get_engine_clock = &radeon_atom_get_engine_clock,
366 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 453 
	.set_engine_clock = &radeon_atom_set_engine_clock,
367 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 454 
	.get_memory_clock = &radeon_atom_get_memory_clock,
368 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 455 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 456 
	.get_pcie_lanes = NULL,
369 
	.set_pcie_lanes = NULL,
 457 
	.set_pcie_lanes = NULL,
370 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 458 
	.set_clock_gating = &radeon_atom_set_clock_gating,
371 
	.set_surface_reg = r100_set_surface_reg,
 459 
	.set_surface_reg = r100_set_surface_reg,
372 
	.clear_surface_reg = r100_clear_surface_reg,
 460 
	.clear_surface_reg = r100_clear_surface_reg,
373 
	.bandwidth_update = &rs690_bandwidth_update,
 461 
	.bandwidth_update = &rs690_bandwidth_update,
Line 416... Line 504...
416 
//	.copy = &r100_copy_blit,
 504 
//	.copy = &r100_copy_blit,
417 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 505 
	.get_engine_clock = &radeon_atom_get_engine_clock,
418 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 506 
	.set_engine_clock = &radeon_atom_set_engine_clock,
419 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 507 
	.get_memory_clock = &radeon_atom_get_memory_clock,
420 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 508 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 509 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
421 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 510 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
422 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 511 
	.set_clock_gating = &radeon_atom_set_clock_gating,
423 
	.set_surface_reg = r100_set_surface_reg,
 512 
	.set_surface_reg = r100_set_surface_reg,
424 
	.clear_surface_reg = r100_clear_surface_reg,
 513 
	.clear_surface_reg = r100_clear_surface_reg,
425 
	.bandwidth_update = &rv515_bandwidth_update,
 514 
	.bandwidth_update = &rv515_bandwidth_update,
Line 459... Line 548...
459 
//	.copy = &r100_copy_blit,
 548 
//	.copy = &r100_copy_blit,
460 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 549 
	.get_engine_clock = &radeon_atom_get_engine_clock,
461 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 550 
	.set_engine_clock = &radeon_atom_set_engine_clock,
462 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 551 
	.get_memory_clock = &radeon_atom_get_memory_clock,
463 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 552 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 553 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
464 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
 554 
	.set_pcie_lanes = &rv370_set_pcie_lanes,
465 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 555 
	.set_clock_gating = &radeon_atom_set_clock_gating,
466 
	.set_surface_reg = r100_set_surface_reg,
 556 
	.set_surface_reg = r100_set_surface_reg,
467 
	.clear_surface_reg = r100_clear_surface_reg,
 557 
	.clear_surface_reg = r100_clear_surface_reg,
468 
	.bandwidth_update = &rv515_bandwidth_update,
 558 
	.bandwidth_update = &rv515_bandwidth_update,
Line 535... Line 625...
535 
//	.copy = &r600_copy_blit,
 625 
//	.copy = &r600_copy_blit,
536 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 626 
	.get_engine_clock = &radeon_atom_get_engine_clock,
537 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 627 
	.set_engine_clock = &radeon_atom_set_engine_clock,
538 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 628 
	.get_memory_clock = &radeon_atom_get_memory_clock,
539 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 629 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 630 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
540 
	.set_pcie_lanes = NULL,
 631 
	.set_pcie_lanes = NULL,
541 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 632 
	.set_clock_gating = NULL,
542 
	.set_surface_reg = r600_set_surface_reg,
 633 
	.set_surface_reg = r600_set_surface_reg,
543 
	.clear_surface_reg = r600_clear_surface_reg,
 634 
	.clear_surface_reg = r600_clear_surface_reg,
544 
	.bandwidth_update = &rv515_bandwidth_update,
 635 
	.bandwidth_update = &rv515_bandwidth_update,
545 
	.hpd_init = &r600_hpd_init,
 636 
	.hpd_init = &r600_hpd_init,
546 
	.hpd_fini = &r600_hpd_fini,
 637 
	.hpd_fini = &r600_hpd_fini,
Line 579... Line 670...
579 
//	.copy = &r600_copy_blit,
 670 
//	.copy = &r600_copy_blit,
580 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 671 
	.get_engine_clock = &radeon_atom_get_engine_clock,
581 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 672 
	.set_engine_clock = &radeon_atom_set_engine_clock,
582 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 673 
	.get_memory_clock = &radeon_atom_get_memory_clock,
583 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 674 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 675 
	.get_pcie_lanes = &rv370_get_pcie_lanes,
584 
	.set_pcie_lanes = NULL,
 676 
	.set_pcie_lanes = NULL,
585 
	.set_clock_gating = &radeon_atom_set_clock_gating,
 677 
	.set_clock_gating = &radeon_atom_set_clock_gating,
586 
	.set_surface_reg = r600_set_surface_reg,
 678 
	.set_surface_reg = r600_set_surface_reg,
587 
	.clear_surface_reg = r600_clear_surface_reg,
 679 
	.clear_surface_reg = r600_clear_surface_reg,
588 
	.bandwidth_update = &rv515_bandwidth_update,
 680 
	.bandwidth_update = &rv515_bandwidth_update,
589 
	.hpd_init = &r600_hpd_init,
 681 
	.hpd_init = &r600_hpd_init,
590 
	.hpd_fini = &r600_hpd_fini,
 682 
	.hpd_fini = &r600_hpd_fini,
591 
	.hpd_sense = &r600_hpd_sense,
 683 
	.hpd_sense = &r600_hpd_sense,
592 
	.hpd_set_polarity = &r600_hpd_set_polarity,
 684 
	.hpd_set_polarity = &r600_hpd_set_polarity,
- 
 
 685 
};
- 
 
 686 
 
- 
 
 687 
/*
- 
 
 688 
 * evergreen
- 
 
 689 
 */
- 
 
 690 
int evergreen_init(struct radeon_device *rdev);
- 
 
 691 
void evergreen_fini(struct radeon_device *rdev);
- 
 
 692 
int evergreen_suspend(struct radeon_device *rdev);
- 
 
 693 
int evergreen_resume(struct radeon_device *rdev);
- 
 
 694 
int evergreen_gpu_reset(struct radeon_device *rdev);
- 
 
 695 
void evergreen_bandwidth_update(struct radeon_device *rdev);
- 
 
 696 
void evergreen_hpd_init(struct radeon_device *rdev);
- 
 
 697 
void evergreen_hpd_fini(struct radeon_device *rdev);
- 
 
 698 
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
- 
 
 699 
void evergreen_hpd_set_polarity(struct radeon_device *rdev,
- 
 
 700 
				enum radeon_hpd_id hpd);
- 
 
 701 
 
- 
 
 702 
static struct radeon_asic evergreen_asic = {
- 
 
 703 
	.init = &evergreen_init,
- 
 
 704 
//	.fini = &evergreen_fini,
- 
 
 705 
//	.suspend = &evergreen_suspend,
- 
 
 706 
//	.resume = &evergreen_resume,
- 
 
 707 
	.cp_commit = NULL,
- 
 
 708 
	.gpu_reset = &evergreen_gpu_reset,
- 
 
 709 
	.vga_set_state = &r600_vga_set_state,
- 
 
 710 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
593 
//	.ioctl_wait_idle = r600_ioctl_wait_idle,
 711 
	.gart_set_page = &rs600_gart_set_page,
- 
 
 712 
	.ring_test = NULL,
- 
 
 713 
//	.ring_ib_execute = &r600_ring_ib_execute,
- 
 
 714 
//	.irq_set = &r600_irq_set,
- 
 
 715 
//	.irq_process = &r600_irq_process,
- 
 
 716 
	.fence_ring_emit = &r600_fence_ring_emit,
- 
 
 717 
//	.cs_parse = &r600_cs_parse,
- 
 
 718 
//	.copy_blit = &r600_copy_blit,
- 
 
 719 
//	.copy_dma = &r600_copy_blit,
- 
 
 720 
//	.copy = &r600_copy_blit,
- 
 
 721 
	.get_engine_clock = &radeon_atom_get_engine_clock,
- 
 
 722 
	.set_engine_clock = &radeon_atom_set_engine_clock,
- 
 
 723 
	.get_memory_clock = &radeon_atom_get_memory_clock,
- 
 
 724 
	.set_memory_clock = &radeon_atom_set_memory_clock,
- 
 
 725 
	.set_pcie_lanes = NULL,
- 
 
 726 
	.set_clock_gating = NULL,
- 
 
 727 
	.set_surface_reg = r600_set_surface_reg,
- 
 
 728 
	.clear_surface_reg = r600_clear_surface_reg,
- 
 
 729 
	.bandwidth_update = &evergreen_bandwidth_update,
- 
 
 730 
	.hpd_init = &evergreen_hpd_init,
- 
 
 731 
	.hpd_fini = &evergreen_hpd_fini,
- 
 
 732 
	.hpd_sense = &evergreen_hpd_sense,
- 
 
 733 
	.hpd_set_polarity = &evergreen_hpd_set_polarity,
594 
};
 734 
};
Line 595... Line 735...
595 
 
 735