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| Rev 1412 | Rev 1413 | ||
|---|---|---|---|
| Line 97... | Line 97... | ||
| 97 | .ring_test = &r100_ring_test, |
97 | .ring_test = &r100_ring_test, |
| 98 | // .ring_ib_execute = &r100_ring_ib_execute, |
98 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 99 | // .irq_set = &r100_irq_set, |
99 | // .irq_set = &r100_irq_set, |
| 100 | // .irq_process = &r100_irq_process, |
100 | // .irq_process = &r100_irq_process, |
| 101 | // .get_vblank_counter = &r100_get_vblank_counter, |
101 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 102 | // .fence_ring_emit = &r100_fence_ring_emit, |
102 | .fence_ring_emit = &r100_fence_ring_emit, |
| 103 | // .cs_parse = &r100_cs_parse, |
103 | // .cs_parse = &r100_cs_parse, |
| 104 | // .copy_blit = &r100_copy_blit, |
104 | // .copy_blit = &r100_copy_blit, |
| 105 | // .copy_dma = NULL, |
105 | // .copy_dma = NULL, |
| 106 | // .copy = &r100_copy_blit, |
106 | // .copy = &r100_copy_blit, |
| 107 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
107 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| Line 157... | Line 157... | ||
| 157 | .ring_test = &r100_ring_test, |
157 | .ring_test = &r100_ring_test, |
| 158 | // .ring_ib_execute = &r100_ring_ib_execute, |
158 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 159 | // .irq_set = &r100_irq_set, |
159 | // .irq_set = &r100_irq_set, |
| 160 | // .irq_process = &r100_irq_process, |
160 | // .irq_process = &r100_irq_process, |
| 161 | // .get_vblank_counter = &r100_get_vblank_counter, |
161 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 162 | // .fence_ring_emit = &r300_fence_ring_emit, |
162 | .fence_ring_emit = &r300_fence_ring_emit, |
| 163 | // .cs_parse = &r300_cs_parse, |
163 | // .cs_parse = &r300_cs_parse, |
| 164 | // .copy_blit = &r100_copy_blit, |
164 | // .copy_blit = &r100_copy_blit, |
| 165 | // .copy_dma = &r300_copy_dma, |
165 | // .copy_dma = &r300_copy_dma, |
| 166 | // .copy = &r100_copy_blit, |
166 | // .copy = &r100_copy_blit, |
| 167 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
167 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| Line 201... | Line 201... | ||
| 201 | .ring_test = &r100_ring_test, |
201 | .ring_test = &r100_ring_test, |
| 202 | // .ring_ib_execute = &r100_ring_ib_execute, |
202 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 203 | // .irq_set = &r100_irq_set, |
203 | // .irq_set = &r100_irq_set, |
| 204 | // .irq_process = &r100_irq_process, |
204 | // .irq_process = &r100_irq_process, |
| 205 | // .get_vblank_counter = &r100_get_vblank_counter, |
205 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 206 | // .fence_ring_emit = &r300_fence_ring_emit, |
206 | .fence_ring_emit = &r300_fence_ring_emit, |
| 207 | // .cs_parse = &r300_cs_parse, |
207 | // .cs_parse = &r300_cs_parse, |
| 208 | // .copy_blit = &r100_copy_blit, |
208 | // .copy_blit = &r100_copy_blit, |
| 209 | // .copy_dma = &r300_copy_dma, |
209 | // .copy_dma = &r300_copy_dma, |
| 210 | // .copy = &r100_copy_blit, |
210 | // .copy = &r100_copy_blit, |
| 211 | .get_engine_clock = &radeon_atom_get_engine_clock, |
211 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 250... | Line 250... | ||
| 250 | .ring_test = &r100_ring_test, |
250 | .ring_test = &r100_ring_test, |
| 251 | // .ring_ib_execute = &r100_ring_ib_execute, |
251 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 252 | // .irq_set = &r100_irq_set, |
252 | // .irq_set = &r100_irq_set, |
| 253 | // .irq_process = &r100_irq_process, |
253 | // .irq_process = &r100_irq_process, |
| 254 | // .get_vblank_counter = &r100_get_vblank_counter, |
254 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 255 | // .fence_ring_emit = &r300_fence_ring_emit, |
255 | .fence_ring_emit = &r300_fence_ring_emit, |
| 256 | // .cs_parse = &r300_cs_parse, |
256 | // .cs_parse = &r300_cs_parse, |
| 257 | // .copy_blit = &r100_copy_blit, |
257 | // .copy_blit = &r100_copy_blit, |
| 258 | // .copy_dma = &r300_copy_dma, |
258 | // .copy_dma = &r300_copy_dma, |
| 259 | // .copy = &r100_copy_blit, |
259 | // .copy = &r100_copy_blit, |
| 260 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
260 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| Line 309... | Line 309... | ||
| 309 | .ring_test = &r100_ring_test, |
309 | .ring_test = &r100_ring_test, |
| 310 | // .ring_ib_execute = &r100_ring_ib_execute, |
310 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 311 | // .irq_set = &rs600_irq_set, |
311 | // .irq_set = &rs600_irq_set, |
| 312 | // .irq_process = &rs600_irq_process, |
312 | // .irq_process = &rs600_irq_process, |
| 313 | // .get_vblank_counter = &rs600_get_vblank_counter, |
313 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 314 | // .fence_ring_emit = &r300_fence_ring_emit, |
314 | .fence_ring_emit = &r300_fence_ring_emit, |
| 315 | // .cs_parse = &r300_cs_parse, |
315 | // .cs_parse = &r300_cs_parse, |
| 316 | // .copy_blit = &r100_copy_blit, |
316 | // .copy_blit = &r100_copy_blit, |
| 317 | // .copy_dma = &r300_copy_dma, |
317 | // .copy_dma = &r300_copy_dma, |
| 318 | // .copy = &r100_copy_blit, |
318 | // .copy = &r100_copy_blit, |
| 319 | .get_engine_clock = &radeon_atom_get_engine_clock, |
319 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 355... | Line 355... | ||
| 355 | .ring_test = &r100_ring_test, |
355 | .ring_test = &r100_ring_test, |
| 356 | // .ring_ib_execute = &r100_ring_ib_execute, |
356 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 357 | // .irq_set = &rs600_irq_set, |
357 | // .irq_set = &rs600_irq_set, |
| 358 | // .irq_process = &rs600_irq_process, |
358 | // .irq_process = &rs600_irq_process, |
| 359 | // .get_vblank_counter = &rs600_get_vblank_counter, |
359 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 360 | // .fence_ring_emit = &r300_fence_ring_emit, |
360 | .fence_ring_emit = &r300_fence_ring_emit, |
| 361 | // .cs_parse = &r300_cs_parse, |
361 | // .cs_parse = &r300_cs_parse, |
| 362 | // .copy_blit = &r100_copy_blit, |
362 | // .copy_blit = &r100_copy_blit, |
| 363 | // .copy_dma = &r300_copy_dma, |
363 | // .copy_dma = &r300_copy_dma, |
| 364 | // .copy = &r300_copy_dma, |
364 | // .copy = &r300_copy_dma, |
| 365 | .get_engine_clock = &radeon_atom_get_engine_clock, |
365 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 407... | Line 407... | ||
| 407 | .ring_test = &r100_ring_test, |
407 | .ring_test = &r100_ring_test, |
| 408 | // .ring_ib_execute = &r100_ring_ib_execute, |
408 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 409 | // .irq_set = &rs600_irq_set, |
409 | // .irq_set = &rs600_irq_set, |
| 410 | // .irq_process = &rs600_irq_process, |
410 | // .irq_process = &rs600_irq_process, |
| 411 | // .get_vblank_counter = &rs600_get_vblank_counter, |
411 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 412 | // .fence_ring_emit = &r300_fence_ring_emit, |
412 | .fence_ring_emit = &r300_fence_ring_emit, |
| 413 | // .cs_parse = &r300_cs_parse, |
413 | // .cs_parse = &r300_cs_parse, |
| 414 | // .copy_blit = &r100_copy_blit, |
414 | // .copy_blit = &r100_copy_blit, |
| 415 | // .copy_dma = &r300_copy_dma, |
415 | // .copy_dma = &r300_copy_dma, |
| 416 | // .copy = &r100_copy_blit, |
416 | // .copy = &r100_copy_blit, |
| 417 | .get_engine_clock = &radeon_atom_get_engine_clock, |
417 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 450... | Line 450... | ||
| 450 | .ring_test = &r100_ring_test, |
450 | .ring_test = &r100_ring_test, |
| 451 | // .ring_ib_execute = &r100_ring_ib_execute, |
451 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 452 | // .irq_set = &rs600_irq_set, |
452 | // .irq_set = &rs600_irq_set, |
| 453 | // .irq_process = &rs600_irq_process, |
453 | // .irq_process = &rs600_irq_process, |
| 454 | // .get_vblank_counter = &rs600_get_vblank_counter, |
454 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 455 | // .fence_ring_emit = &r300_fence_ring_emit, |
455 | .fence_ring_emit = &r300_fence_ring_emit, |
| 456 | // .cs_parse = &r300_cs_parse, |
456 | // .cs_parse = &r300_cs_parse, |
| 457 | // .copy_blit = &r100_copy_blit, |
457 | // .copy_blit = &r100_copy_blit, |
| 458 | // .copy_dma = &r300_copy_dma, |
458 | // .copy_dma = &r300_copy_dma, |
| 459 | // .copy = &r100_copy_blit, |
459 | // .copy = &r100_copy_blit, |
| 460 | .get_engine_clock = &radeon_atom_get_engine_clock, |
460 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 517... | Line 517... | ||
| 517 | static struct radeon_asic r600_asic = { |
517 | static struct radeon_asic r600_asic = { |
| 518 | .init = &r600_init, |
518 | .init = &r600_init, |
| 519 | // .fini = &r600_fini, |
519 | // .fini = &r600_fini, |
| 520 | // .suspend = &r600_suspend, |
520 | // .suspend = &r600_suspend, |
| 521 | // .resume = &r600_resume, |
521 | // .resume = &r600_resume, |
| 522 | // .cp_commit = &r600_cp_commit, |
522 | .cp_commit = &r600_cp_commit, |
| 523 | .vga_set_state = &r600_vga_set_state, |
523 | .vga_set_state = &r600_vga_set_state, |
| 524 | .gpu_reset = &r600_gpu_reset, |
524 | .gpu_reset = &r600_gpu_reset, |
| 525 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
525 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 526 | .gart_set_page = &rs600_gart_set_page, |
526 | .gart_set_page = &rs600_gart_set_page, |
| 527 | // .ring_test = &r600_ring_test, |
527 | .ring_test = &r600_ring_test, |
| 528 | // .ring_ib_execute = &r600_ring_ib_execute, |
528 | // .ring_ib_execute = &r600_ring_ib_execute, |
| 529 | // .irq_set = &r600_irq_set, |
529 | // .irq_set = &r600_irq_set, |
| 530 | // .irq_process = &r600_irq_process, |
530 | // .irq_process = &r600_irq_process, |
| 531 | // .fence_ring_emit = &r600_fence_ring_emit, |
531 | .fence_ring_emit = &r600_fence_ring_emit, |
| 532 | // .cs_parse = &r600_cs_parse, |
532 | // .cs_parse = &r600_cs_parse, |
| 533 | // .copy_blit = &r600_copy_blit, |
533 | // .copy_blit = &r600_copy_blit, |
| 534 | // .copy_dma = &r600_copy_blit, |
534 | // .copy_dma = &r600_copy_blit, |
| 535 | // .copy = &r600_copy_blit, |
535 | // .copy = &r600_copy_blit, |
| 536 | .get_engine_clock = &radeon_atom_get_engine_clock, |
536 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| Line 561... | Line 561... | ||
| 561 | static struct radeon_asic rv770_asic = { |
561 | static struct radeon_asic rv770_asic = { |
| 562 | .init = &rv770_init, |
562 | .init = &rv770_init, |
| 563 | // .fini = &rv770_fini, |
563 | // .fini = &rv770_fini, |
| 564 | // .suspend = &rv770_suspend, |
564 | // .suspend = &rv770_suspend, |
| 565 | // .resume = &rv770_resume, |
565 | // .resume = &rv770_resume, |
| 566 | // .cp_commit = &r600_cp_commit, |
566 | .cp_commit = &r600_cp_commit, |
| 567 | .gpu_reset = &rv770_gpu_reset, |
567 | .gpu_reset = &rv770_gpu_reset, |
| 568 | .vga_set_state = &r600_vga_set_state, |
568 | .vga_set_state = &r600_vga_set_state, |
| 569 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
569 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 570 | .gart_set_page = &rs600_gart_set_page, |
570 | .gart_set_page = &rs600_gart_set_page, |
| 571 | // .ring_test = &r600_ring_test, |
571 | .ring_test = &r600_ring_test, |
| 572 | // .ring_ib_execute = &r600_ring_ib_execute, |
572 | // .ring_ib_execute = &r600_ring_ib_execute, |
| 573 | // .irq_set = &r600_irq_set, |
573 | // .irq_set = &r600_irq_set, |
| 574 | // .irq_process = &r600_irq_process, |
574 | // .irq_process = &r600_irq_process, |
| 575 | // .fence_ring_emit = &r600_fence_ring_emit, |
575 | .fence_ring_emit = &r600_fence_ring_emit, |
| 576 | // .cs_parse = &r600_cs_parse, |
576 | // .cs_parse = &r600_cs_parse, |
| 577 | // .copy_blit = &r600_copy_blit, |
577 | // .copy_blit = &r600_copy_blit, |
| 578 | // .copy_dma = &r600_copy_blit, |
578 | // .copy_dma = &r600_copy_blit, |
| 579 | // .copy = &r600_copy_blit, |
579 | // .copy = &r600_copy_blit, |
| 580 | .get_engine_clock = &radeon_atom_get_engine_clock, |
580 | .get_engine_clock = &radeon_atom_get_engine_clock, |