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| Rev 1404 | Rev 1412 | ||
|---|---|---|---|
| Line 91... | Line 91... | ||
| 91 | // .vga_set_state = &r100_vga_set_state, |
91 | // .vga_set_state = &r100_vga_set_state, |
| 92 | .gpu_reset = &r100_gpu_reset, |
92 | .gpu_reset = &r100_gpu_reset, |
| 93 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
93 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 94 | .gart_set_page = &r100_pci_gart_set_page, |
94 | .gart_set_page = &r100_pci_gart_set_page, |
| 95 | .cp_commit = &r100_cp_commit, |
95 | .cp_commit = &r100_cp_commit, |
| 96 | // .ring_start = &r100_ring_start, |
96 | .ring_start = &r100_ring_start, |
| 97 | // .ring_test = &r100_ring_test, |
97 | .ring_test = &r100_ring_test, |
| 98 | // .ring_ib_execute = &r100_ring_ib_execute, |
98 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 99 | // .irq_set = &r100_irq_set, |
99 | // .irq_set = &r100_irq_set, |
| 100 | // .irq_process = &r100_irq_process, |
100 | // .irq_process = &r100_irq_process, |
| 101 | // .get_vblank_counter = &r100_get_vblank_counter, |
101 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 102 | // .fence_ring_emit = &r100_fence_ring_emit, |
102 | // .fence_ring_emit = &r100_fence_ring_emit, |
| Line 150... | Line 150... | ||
| 150 | // .resume = &r300_resume, |
150 | // .resume = &r300_resume, |
| 151 | // .vga_set_state = &r100_vga_set_state, |
151 | // .vga_set_state = &r100_vga_set_state, |
| 152 | .gpu_reset = &r300_gpu_reset, |
152 | .gpu_reset = &r300_gpu_reset, |
| 153 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
153 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 154 | .gart_set_page = &r100_pci_gart_set_page, |
154 | .gart_set_page = &r100_pci_gart_set_page, |
| 155 | // .cp_commit = &r100_cp_commit, |
155 | .cp_commit = &r100_cp_commit, |
| 156 | // .ring_start = &r300_ring_start, |
156 | .ring_start = &r300_ring_start, |
| 157 | // .ring_test = &r100_ring_test, |
157 | .ring_test = &r100_ring_test, |
| 158 | // .ring_ib_execute = &r100_ring_ib_execute, |
158 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 159 | // .irq_set = &r100_irq_set, |
159 | // .irq_set = &r100_irq_set, |
| 160 | // .irq_process = &r100_irq_process, |
160 | // .irq_process = &r100_irq_process, |
| 161 | // .get_vblank_counter = &r100_get_vblank_counter, |
161 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 162 | // .fence_ring_emit = &r300_fence_ring_emit, |
162 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 194... | Line 194... | ||
| 194 | // .resume = &r420_resume, |
194 | // .resume = &r420_resume, |
| 195 | // .vga_set_state = &r100_vga_set_state, |
195 | // .vga_set_state = &r100_vga_set_state, |
| 196 | .gpu_reset = &r300_gpu_reset, |
196 | .gpu_reset = &r300_gpu_reset, |
| 197 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
197 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 198 | .gart_set_page = &rv370_pcie_gart_set_page, |
198 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 199 | // .cp_commit = &r100_cp_commit, |
199 | .cp_commit = &r100_cp_commit, |
| 200 | // .ring_start = &r300_ring_start, |
200 | .ring_start = &r300_ring_start, |
| 201 | // .ring_test = &r100_ring_test, |
201 | .ring_test = &r100_ring_test, |
| 202 | // .ring_ib_execute = &r100_ring_ib_execute, |
202 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 203 | // .irq_set = &r100_irq_set, |
203 | // .irq_set = &r100_irq_set, |
| 204 | // .irq_process = &r100_irq_process, |
204 | // .irq_process = &r100_irq_process, |
| 205 | // .get_vblank_counter = &r100_get_vblank_counter, |
205 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 206 | // .fence_ring_emit = &r300_fence_ring_emit, |
206 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 243... | Line 243... | ||
| 243 | // .resume = &rs400_resume, |
243 | // .resume = &rs400_resume, |
| 244 | // .vga_set_state = &r100_vga_set_state, |
244 | // .vga_set_state = &r100_vga_set_state, |
| 245 | .gpu_reset = &r300_gpu_reset, |
245 | .gpu_reset = &r300_gpu_reset, |
| 246 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
246 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 247 | .gart_set_page = &rs400_gart_set_page, |
247 | .gart_set_page = &rs400_gart_set_page, |
| 248 | // .cp_commit = &r100_cp_commit, |
248 | .cp_commit = &r100_cp_commit, |
| 249 | // .ring_start = &r300_ring_start, |
249 | .ring_start = &r300_ring_start, |
| 250 | // .ring_test = &r100_ring_test, |
250 | .ring_test = &r100_ring_test, |
| 251 | // .ring_ib_execute = &r100_ring_ib_execute, |
251 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 252 | // .irq_set = &r100_irq_set, |
252 | // .irq_set = &r100_irq_set, |
| 253 | // .irq_process = &r100_irq_process, |
253 | // .irq_process = &r100_irq_process, |
| 254 | // .get_vblank_counter = &r100_get_vblank_counter, |
254 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 255 | // .fence_ring_emit = &r300_fence_ring_emit, |
255 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 302... | Line 302... | ||
| 302 | // .resume = &rs600_resume, |
302 | // .resume = &rs600_resume, |
| 303 | // .vga_set_state = &r100_vga_set_state, |
303 | // .vga_set_state = &r100_vga_set_state, |
| 304 | .gpu_reset = &r300_gpu_reset, |
304 | .gpu_reset = &r300_gpu_reset, |
| 305 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
305 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
| 306 | .gart_set_page = &rs600_gart_set_page, |
306 | .gart_set_page = &rs600_gart_set_page, |
| 307 | // .cp_commit = &r100_cp_commit, |
307 | .cp_commit = &r100_cp_commit, |
| 308 | // .ring_start = &r300_ring_start, |
308 | .ring_start = &r300_ring_start, |
| 309 | // .ring_test = &r100_ring_test, |
309 | .ring_test = &r100_ring_test, |
| 310 | // .ring_ib_execute = &r100_ring_ib_execute, |
310 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 311 | // .irq_set = &rs600_irq_set, |
311 | // .irq_set = &rs600_irq_set, |
| 312 | // .irq_process = &rs600_irq_process, |
312 | // .irq_process = &rs600_irq_process, |
| 313 | // .get_vblank_counter = &rs600_get_vblank_counter, |
313 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 314 | // .fence_ring_emit = &r300_fence_ring_emit, |
314 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 348... | Line 348... | ||
| 348 | // .resume = &rs690_resume, |
348 | // .resume = &rs690_resume, |
| 349 | // .vga_set_state = &r100_vga_set_state, |
349 | // .vga_set_state = &r100_vga_set_state, |
| 350 | .gpu_reset = &r300_gpu_reset, |
350 | .gpu_reset = &r300_gpu_reset, |
| 351 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
351 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 352 | .gart_set_page = &rs400_gart_set_page, |
352 | .gart_set_page = &rs400_gart_set_page, |
| 353 | // .cp_commit = &r100_cp_commit, |
353 | .cp_commit = &r100_cp_commit, |
| 354 | // .ring_start = &r300_ring_start, |
354 | .ring_start = &r300_ring_start, |
| 355 | // .ring_test = &r100_ring_test, |
355 | .ring_test = &r100_ring_test, |
| 356 | // .ring_ib_execute = &r100_ring_ib_execute, |
356 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 357 | // .irq_set = &rs600_irq_set, |
357 | // .irq_set = &rs600_irq_set, |
| 358 | // .irq_process = &rs600_irq_process, |
358 | // .irq_process = &rs600_irq_process, |
| 359 | // .get_vblank_counter = &rs600_get_vblank_counter, |
359 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 360 | // .fence_ring_emit = &r300_fence_ring_emit, |
360 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 400... | Line 400... | ||
| 400 | // .resume = &rv515_resume, |
400 | // .resume = &rv515_resume, |
| 401 | // .vga_set_state = &r100_vga_set_state, |
401 | // .vga_set_state = &r100_vga_set_state, |
| 402 | .gpu_reset = &rv515_gpu_reset, |
402 | .gpu_reset = &rv515_gpu_reset, |
| 403 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
403 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 404 | .gart_set_page = &rv370_pcie_gart_set_page, |
404 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 405 | // .cp_commit = &r100_cp_commit, |
405 | .cp_commit = &r100_cp_commit, |
| 406 | // .ring_start = &rv515_ring_start, |
406 | .ring_start = &rv515_ring_start, |
| 407 | // .ring_test = &r100_ring_test, |
407 | .ring_test = &r100_ring_test, |
| 408 | // .ring_ib_execute = &r100_ring_ib_execute, |
408 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 409 | // .irq_set = &rs600_irq_set, |
409 | // .irq_set = &rs600_irq_set, |
| 410 | // .irq_process = &rs600_irq_process, |
410 | // .irq_process = &rs600_irq_process, |
| 411 | // .get_vblank_counter = &rs600_get_vblank_counter, |
411 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 412 | // .fence_ring_emit = &r300_fence_ring_emit, |
412 | // .fence_ring_emit = &r300_fence_ring_emit, |
| Line 443... | Line 443... | ||
| 443 | // .resume = &r520_resume, |
443 | // .resume = &r520_resume, |
| 444 | // .vga_set_state = &r100_vga_set_state, |
444 | // .vga_set_state = &r100_vga_set_state, |
| 445 | .gpu_reset = &rv515_gpu_reset, |
445 | .gpu_reset = &rv515_gpu_reset, |
| 446 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
446 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 447 | .gart_set_page = &rv370_pcie_gart_set_page, |
447 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 448 | // .cp_commit = &r100_cp_commit, |
448 | .cp_commit = &r100_cp_commit, |
| 449 | // .ring_start = &rv515_ring_start, |
449 | .ring_start = &rv515_ring_start, |
| 450 | // .ring_test = &r100_ring_test, |
450 | .ring_test = &r100_ring_test, |
| 451 | // .ring_ib_execute = &r100_ring_ib_execute, |
451 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 452 | // .irq_set = &rs600_irq_set, |
452 | // .irq_set = &rs600_irq_set, |
| 453 | // .irq_process = &rs600_irq_process, |
453 | // .irq_process = &rs600_irq_process, |
| 454 | // .get_vblank_counter = &rs600_get_vblank_counter, |
454 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 455 | // .fence_ring_emit = &r300_fence_ring_emit, |
455 | // .fence_ring_emit = &r300_fence_ring_emit, |