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| Rev 1179 | Rev 1221 | ||
|---|---|---|---|
| Line 39... | Line 39... | ||
| 39 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
39 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| Line 40... | Line 40... | ||
| 40 | 40 | ||
| 41 | /* |
41 | /* |
| 42 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
42 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| 43 | */ |
43 | */ |
| 44 | int r100_init(struct radeon_device *rdev); |
44 | extern int r100_init(struct radeon_device *rdev); |
| - | 45 | extern void r100_fini(struct radeon_device *rdev); |
|
| - | 46 | extern int r100_suspend(struct radeon_device *rdev); |
|
| 45 | int r200_init(struct radeon_device *rdev); |
47 | extern int r100_resume(struct radeon_device *rdev); |
| 46 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
48 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| 47 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
- | |
| 48 | void r100_errata(struct radeon_device *rdev); |
- | |
| 49 | void r100_vram_info(struct radeon_device *rdev); |
49 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 50 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
50 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| 51 | int r100_gpu_reset(struct radeon_device *rdev); |
- | |
| 52 | int r100_mc_init(struct radeon_device *rdev); |
- | |
| 53 | void r100_mc_fini(struct radeon_device *rdev); |
51 | int r100_gpu_reset(struct radeon_device *rdev); |
| 54 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
- | |
| 55 | int r100_wb_init(struct radeon_device *rdev); |
- | |
| 56 | void r100_wb_fini(struct radeon_device *rdev); |
- | |
| 57 | int r100_pci_gart_init(struct radeon_device *rdev); |
- | |
| 58 | void r100_pci_gart_fini(struct radeon_device *rdev); |
- | |
| 59 | int r100_pci_gart_enable(struct radeon_device *rdev); |
- | |
| 60 | void r100_pci_gart_disable(struct radeon_device *rdev); |
52 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 61 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
53 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 62 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
- | |
| 63 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
- | |
| 64 | void r100_cp_fini(struct radeon_device *rdev); |
- | |
| 65 | void r100_cp_disable(struct radeon_device *rdev); |
54 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 66 | void r100_cp_commit(struct radeon_device *rdev); |
55 | void r100_cp_commit(struct radeon_device *rdev); |
| 67 | void r100_ring_start(struct radeon_device *rdev); |
56 | void r100_ring_start(struct radeon_device *rdev); |
| 68 | int r100_irq_set(struct radeon_device *rdev); |
57 | int r100_irq_set(struct radeon_device *rdev); |
| 69 | int r100_irq_process(struct radeon_device *rdev); |
58 | int r100_irq_process(struct radeon_device *rdev); |
| Line 81... | Line 70... | ||
| 81 | uint32_t tiling_flags, uint32_t pitch, |
70 | uint32_t tiling_flags, uint32_t pitch, |
| 82 | uint32_t offset, uint32_t obj_size); |
71 | uint32_t offset, uint32_t obj_size); |
| 83 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
72 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| 84 | void r100_bandwidth_update(struct radeon_device *rdev); |
73 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 85 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
74 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 86 | int r100_ib_test(struct radeon_device *rdev); |
- | |
| 87 | int r100_ring_test(struct radeon_device *rdev); |
75 | int r100_ring_test(struct radeon_device *rdev); |
| Line 88... | Line 76... | ||
| 88 | 76 | ||
| 89 | static struct radeon_asic r100_asic = { |
77 | static struct radeon_asic r100_asic = { |
| - | 78 | .init = &r100_init, |
|
| - | 79 | // .fini = &r100_fini, |
|
| 90 | .init = &r100_init, |
80 | // .suspend = &r100_suspend, |
| 91 | .errata = &r100_errata, |
81 | // .resume = &r100_resume, |
| 92 | .vram_info = &r100_vram_info, |
82 | // .vga_set_state = &r100_vga_set_state, |
| 93 | .gpu_reset = &r100_gpu_reset, |
- | |
| 94 | .mc_init = &r100_mc_init, |
- | |
| 95 | .mc_fini = &r100_mc_fini, |
- | |
| 96 | // .wb_init = &r100_wb_init, |
- | |
| 97 | // .wb_fini = &r100_wb_fini, |
- | |
| 98 | .gart_enable = &r100_pci_gart_enable, |
- | |
| 99 | .gart_disable = &r100_pci_gart_disable, |
83 | .gpu_reset = &r100_gpu_reset, |
| 100 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
84 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 101 | .gart_set_page = &r100_pci_gart_set_page, |
85 | .gart_set_page = &r100_pci_gart_set_page, |
| 102 | .cp_init = &r100_cp_init, |
86 | .cp_commit = &r100_cp_commit, |
| 103 | // .cp_fini = &r100_cp_fini, |
87 | // .ring_start = &r100_ring_start, |
| 104 | // .cp_disable = &r100_cp_disable, |
88 | // .ring_test = &r100_ring_test, |
| 105 | .ring_start = &r100_ring_start, |
89 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 106 | // .irq_set = &r100_irq_set, |
90 | // .irq_set = &r100_irq_set, |
| - | 91 | // .irq_process = &r100_irq_process, |
|
| 107 | // .irq_process = &r100_irq_process, |
92 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 108 | // .fence_ring_emit = &r100_fence_ring_emit, |
93 | // .fence_ring_emit = &r100_fence_ring_emit, |
| 109 | // .cs_parse = &r100_cs_parse, |
94 | // .cs_parse = &r100_cs_parse, |
| 110 | // .copy_blit = &r100_copy_blit, |
95 | // .copy_blit = &r100_copy_blit, |
| 111 | // .copy_dma = NULL, |
96 | // .copy_dma = NULL, |
| 112 | // .copy = &r100_copy_blit, |
97 | // .copy = &r100_copy_blit, |
| 113 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
98 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 114 | // .set_memory_clock = NULL, |
99 | .set_memory_clock = NULL, |
| 115 | // .set_pcie_lanes = NULL, |
100 | .set_pcie_lanes = NULL, |
| 116 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
101 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 117 | .set_surface_reg = r100_set_surface_reg, |
102 | .set_surface_reg = r100_set_surface_reg, |
| 118 | .clear_surface_reg = r100_clear_surface_reg, |
103 | .clear_surface_reg = r100_clear_surface_reg, |
| 119 | .bandwidth_update = &r100_bandwidth_update, |
104 | .bandwidth_update = &r100_bandwidth_update, |
| Line 120... | Line 105... | ||
| 120 | }; |
105 | }; |
| 121 | 106 | ||
| 122 | 107 | ||
| 123 | /* |
108 | /* |
| 124 | * r300,r350,rv350,rv380 |
109 | * r300,r350,rv350,rv380 |
| 125 | */ |
110 | */ |
| 126 | int r300_init(struct radeon_device *rdev); |
111 | extern int r300_init(struct radeon_device *rdev); |
| 127 | void r300_errata(struct radeon_device *rdev); |
112 | extern void r300_fini(struct radeon_device *rdev); |
| 128 | void r300_vram_info(struct radeon_device *rdev); |
- | |
| 129 | int r300_gpu_reset(struct radeon_device *rdev); |
113 | extern int r300_suspend(struct radeon_device *rdev); |
| 130 | int r300_mc_init(struct radeon_device *rdev); |
114 | extern int r300_resume(struct radeon_device *rdev); |
| 131 | void r300_mc_fini(struct radeon_device *rdev); |
115 | extern int r300_gpu_reset(struct radeon_device *rdev); |
| 132 | void r300_ring_start(struct radeon_device *rdev); |
116 | extern void r300_ring_start(struct radeon_device *rdev); |
| 133 | void r300_fence_ring_emit(struct radeon_device *rdev, |
- | |
| 134 | struct radeon_fence *fence); |
- | |
| 135 | int r300_cs_parse(struct radeon_cs_parser *p); |
- | |
| 136 | int rv370_pcie_gart_init(struct radeon_device *rdev); |
- | |
| 137 | void rv370_pcie_gart_fini(struct radeon_device *rdev); |
117 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 138 | int rv370_pcie_gart_enable(struct radeon_device *rdev); |
118 | struct radeon_fence *fence); |
| 139 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
119 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
| 140 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
120 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 141 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
121 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 142 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
122 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| 143 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
123 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 144 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
124 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 145 | int r300_copy_dma(struct radeon_device *rdev, |
125 | extern int r300_copy_dma(struct radeon_device *rdev, |
| 146 | uint64_t src_offset, |
126 | uint64_t src_offset, |
| 147 | uint64_t dst_offset, |
- | |
| 148 | unsigned num_pages, |
127 | uint64_t dst_offset, |
| 149 | struct radeon_fence *fence); |
128 | unsigned num_pages, |
| 150 | 129 | struct radeon_fence *fence); |
|
| 151 | static struct radeon_asic r300_asic = { |
130 | static struct radeon_asic r300_asic = { |
| - | 131 | .init = &r300_init, |
|
| 152 | .init = &r300_init, |
132 | // .fini = &r300_fini, |
| 153 | .errata = &r300_errata, |
133 | // .suspend = &r300_suspend, |
| 154 | .vram_info = &r300_vram_info, |
- | |
| 155 | .vga_set_state = &r100_vga_set_state, |
- | |
| 156 | .gpu_reset = &r300_gpu_reset, |
- | |
| 157 | .mc_init = &r300_mc_init, |
- | |
| 158 | .mc_fini = &r300_mc_fini, |
- | |
| 159 | // .wb_init = &r100_wb_init, |
- | |
| 160 | // .wb_fini = &r100_wb_fini, |
134 | // .resume = &r300_resume, |
| 161 | .gart_enable = &r100_pci_gart_enable, |
135 | // .vga_set_state = &r100_vga_set_state, |
| 162 | .gart_disable = &r100_pci_gart_disable, |
136 | .gpu_reset = &r300_gpu_reset, |
| 163 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
137 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 164 | .gart_set_page = &r100_pci_gart_set_page, |
138 | .gart_set_page = &r100_pci_gart_set_page, |
| 165 | .cp_init = &r100_cp_init, |
139 | // .cp_commit = &r100_cp_commit, |
| 166 | // .cp_fini = &r100_cp_fini, |
140 | // .ring_start = &r300_ring_start, |
| 167 | // .cp_disable = &r100_cp_disable, |
141 | // .ring_test = &r100_ring_test, |
| - | 142 | // .ring_ib_execute = &r100_ring_ib_execute, |
|
| 168 | .ring_start = &r300_ring_start, |
143 | // .irq_set = &r100_irq_set, |
| 169 | // .irq_set = &r100_irq_set, |
144 | // .irq_process = &r100_irq_process, |
| 170 | // .irq_process = &r100_irq_process, |
145 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 171 | // .fence_ring_emit = &r300_fence_ring_emit, |
146 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 172 | // .cs_parse = &r300_cs_parse, |
147 | // .cs_parse = &r300_cs_parse, |
| 173 | // .copy_blit = &r100_copy_blit, |
148 | // .copy_blit = &r100_copy_blit, |
| 174 | // .copy_dma = &r300_copy_dma, |
149 | // .copy_dma = &r300_copy_dma, |
| 175 | // .copy = &r100_copy_blit, |
150 | // .copy = &r100_copy_blit, |
| 176 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
151 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 177 | // .set_memory_clock = NULL, |
152 | .set_memory_clock = NULL, |
| 178 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
153 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 179 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
154 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 180 | .set_surface_reg = r100_set_surface_reg, |
155 | .set_surface_reg = r100_set_surface_reg, |
| Line 189... | Line 164... | ||
| 189 | extern void r420_fini(struct radeon_device *rdev); |
164 | extern void r420_fini(struct radeon_device *rdev); |
| 190 | extern int r420_suspend(struct radeon_device *rdev); |
165 | extern int r420_suspend(struct radeon_device *rdev); |
| 191 | extern int r420_resume(struct radeon_device *rdev); |
166 | extern int r420_resume(struct radeon_device *rdev); |
| 192 | static struct radeon_asic r420_asic = { |
167 | static struct radeon_asic r420_asic = { |
| 193 | .init = &r420_init, |
168 | .init = &r420_init, |
| 194 | .fini = &r420_fini, |
169 | // .fini = &r420_fini, |
| 195 | .suspend = &r420_suspend, |
170 | // .suspend = &r420_suspend, |
| 196 | .resume = &r420_resume, |
171 | // .resume = &r420_resume, |
| 197 | .errata = NULL, |
- | |
| 198 | .vram_info = NULL, |
- | |
| 199 | .vga_set_state = &r100_vga_set_state, |
172 | // .vga_set_state = &r100_vga_set_state, |
| 200 | .gpu_reset = &r300_gpu_reset, |
173 | .gpu_reset = &r300_gpu_reset, |
| 201 | .mc_init = NULL, |
- | |
| 202 | .mc_fini = NULL, |
- | |
| 203 | .wb_init = NULL, |
- | |
| 204 | .wb_fini = NULL, |
- | |
| 205 | .gart_enable = NULL, |
- | |
| 206 | .gart_disable = NULL, |
- | |
| 207 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
174 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 208 | .gart_set_page = &rv370_pcie_gart_set_page, |
175 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 209 | .cp_init = NULL, |
176 | // .cp_commit = &r100_cp_commit, |
| 210 | .cp_fini = NULL, |
177 | // .ring_start = &r300_ring_start, |
| 211 | .cp_disable = NULL, |
178 | // .ring_test = &r100_ring_test, |
| 212 | .ring_start = &r300_ring_start, |
179 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 213 | // .irq_set = &r100_irq_set, |
180 | // .irq_set = &r100_irq_set, |
| 214 | // .irq_process = &r100_irq_process, |
181 | // .irq_process = &r100_irq_process, |
| - | 182 | // .get_vblank_counter = &r100_get_vblank_counter, |
|
| 215 | // .fence_ring_emit = &r300_fence_ring_emit, |
183 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 216 | // .cs_parse = &r300_cs_parse, |
184 | // .cs_parse = &r300_cs_parse, |
| 217 | // .copy_blit = &r100_copy_blit, |
185 | // .copy_blit = &r100_copy_blit, |
| 218 | // .copy_dma = &r300_copy_dma, |
186 | // .copy_dma = &r300_copy_dma, |
| 219 | // .copy = &r100_copy_blit, |
187 | // .copy = &r100_copy_blit, |
| 220 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
188 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 221 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
189 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 222 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
190 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 223 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
191 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 224 | .set_surface_reg = r100_set_surface_reg, |
192 | .set_surface_reg = r100_set_surface_reg, |
| 225 | .clear_surface_reg = r100_clear_surface_reg, |
193 | .clear_surface_reg = r100_clear_surface_reg, |
| 226 | .bandwidth_update = &r100_bandwidth_update, |
194 | .bandwidth_update = &r100_bandwidth_update, |
| 227 | }; |
195 | }; |
| Line 228... | Line 196... | ||
| 228 | 196 | ||
| 229 | 197 | ||
| 230 | /* |
198 | /* |
| 231 | * rs400,rs480 |
- | |
| 232 | */ |
- | |
| 233 | void rs400_errata(struct radeon_device *rdev); |
199 | * rs400,rs480 |
| 234 | void rs400_vram_info(struct radeon_device *rdev); |
200 | */ |
| 235 | int rs400_mc_init(struct radeon_device *rdev); |
201 | extern int rs400_init(struct radeon_device *rdev); |
| 236 | void rs400_mc_fini(struct radeon_device *rdev); |
- | |
| 237 | int rs400_gart_init(struct radeon_device *rdev); |
202 | extern void rs400_fini(struct radeon_device *rdev); |
| 238 | void rs400_gart_fini(struct radeon_device *rdev); |
- | |
| 239 | int rs400_gart_enable(struct radeon_device *rdev); |
203 | extern int rs400_suspend(struct radeon_device *rdev); |
| 240 | void rs400_gart_disable(struct radeon_device *rdev); |
204 | extern int rs400_resume(struct radeon_device *rdev); |
| 241 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
205 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 242 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
206 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 243 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
207 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 244 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
208 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 245 | static struct radeon_asic rs400_asic = { |
209 | static struct radeon_asic rs400_asic = { |
| 246 | .init = &r300_init, |
210 | .init = &rs400_init, |
| - | 211 | // .fini = &rs400_fini, |
|
| 247 | .errata = &rs400_errata, |
212 | // .suspend = &rs400_suspend, |
| 248 | .vram_info = &rs400_vram_info, |
213 | // .resume = &rs400_resume, |
| 249 | .vga_set_state = &r100_vga_set_state, |
- | |
| 250 | .gpu_reset = &r300_gpu_reset, |
- | |
| 251 | .mc_init = &rs400_mc_init, |
- | |
| 252 | .mc_fini = &rs400_mc_fini, |
- | |
| 253 | // .wb_init = &r100_wb_init, |
- | |
| 254 | // .wb_fini = &r100_wb_fini, |
- | |
| 255 | .gart_init = &rs400_gart_init, |
- | |
| 256 | .gart_fini = &rs400_gart_fini, |
- | |
| 257 | .gart_enable = &rs400_gart_enable, |
214 | // .vga_set_state = &r100_vga_set_state, |
| 258 | .gart_disable = &rs400_gart_disable, |
215 | .gpu_reset = &r300_gpu_reset, |
| 259 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
216 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 260 | .gart_set_page = &rs400_gart_set_page, |
217 | .gart_set_page = &rs400_gart_set_page, |
| 261 | .cp_init = &r100_cp_init, |
218 | // .cp_commit = &r100_cp_commit, |
| 262 | // .cp_fini = &r100_cp_fini, |
- | |
| 263 | // .cp_disable = &r100_cp_disable, |
219 | // .ring_start = &r300_ring_start, |
| 264 | .cp_commit = &r100_cp_commit, |
220 | // .ring_test = &r100_ring_test, |
| 265 | .ring_start = &r300_ring_start, |
221 | // .ring_ib_execute = &r100_ring_ib_execute, |
| - | 222 | // .irq_set = &r100_irq_set, |
|
| 266 | // .irq_set = &r100_irq_set, |
223 | // .irq_process = &r100_irq_process, |
| 267 | // .irq_process = &r100_irq_process, |
224 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 268 | // .fence_ring_emit = &r300_fence_ring_emit, |
225 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 269 | // .cs_parse = &r300_cs_parse, |
226 | // .cs_parse = &r300_cs_parse, |
| 270 | // .copy_blit = &r100_copy_blit, |
227 | // .copy_blit = &r100_copy_blit, |
| 271 | // .copy_dma = &r300_copy_dma, |
228 | // .copy_dma = &r300_copy_dma, |
| 272 | // .copy = &r100_copy_blit, |
229 | // .copy = &r100_copy_blit, |
| 273 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
230 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 274 | // .set_memory_clock = NULL, |
231 | .set_memory_clock = NULL, |
| 275 | // .set_pcie_lanes = NULL, |
232 | .set_pcie_lanes = NULL, |
| 276 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
233 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 277 | .set_surface_reg = r100_set_surface_reg, |
234 | .set_surface_reg = r100_set_surface_reg, |
| 278 | .clear_surface_reg = r100_clear_surface_reg, |
235 | .clear_surface_reg = r100_clear_surface_reg, |
| Line 279... | Line 236... | ||
| 279 | .bandwidth_update = &r100_bandwidth_update, |
236 | .bandwidth_update = &r100_bandwidth_update, |
| 280 | }; |
237 | }; |
| 281 | 238 | ||
| 282 | 239 | ||
| 283 | /* |
240 | /* |
| 284 | * rs600. |
- | |
| 285 | */ |
241 | * rs600. |
| 286 | int rs600_init(struct radeon_device *rdev); |
242 | */ |
| 287 | void rs600_errata(struct radeon_device *rdev); |
243 | extern int rs600_init(struct radeon_device *rdev); |
| 288 | void rs600_vram_info(struct radeon_device *rdev); |
244 | extern void rs600_fini(struct radeon_device *rdev); |
| 289 | int rs600_mc_init(struct radeon_device *rdev); |
245 | extern int rs600_suspend(struct radeon_device *rdev); |
| 290 | void rs600_mc_fini(struct radeon_device *rdev); |
- | |
| 291 | int rs600_irq_set(struct radeon_device *rdev); |
- | |
| 292 | int rs600_irq_process(struct radeon_device *rdev); |
- | |
| 293 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
- | |
| 294 | int rs600_gart_init(struct radeon_device *rdev); |
246 | extern int rs600_resume(struct radeon_device *rdev); |
| 295 | void rs600_gart_fini(struct radeon_device *rdev); |
247 | int rs600_irq_set(struct radeon_device *rdev); |
| 296 | int rs600_gart_enable(struct radeon_device *rdev); |
248 | int rs600_irq_process(struct radeon_device *rdev); |
| 297 | void rs600_gart_disable(struct radeon_device *rdev); |
249 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 298 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
250 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 299 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
251 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 300 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
252 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 301 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
253 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 302 | void rs600_bandwidth_update(struct radeon_device *rdev); |
254 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| - | 255 | static struct radeon_asic rs600_asic = { |
|
| 303 | static struct radeon_asic rs600_asic = { |
256 | .init = &rs600_init, |
| 304 | .init = &rs600_init, |
257 | // .fini = &rs600_fini, |
| 305 | .errata = &rs600_errata, |
- | |
| 306 | .vram_info = &rs600_vram_info, |
- | |
| 307 | .vga_set_state = &r100_vga_set_state, |
- | |
| 308 | .gpu_reset = &r300_gpu_reset, |
- | |
| 309 | .mc_init = &rs600_mc_init, |
- | |
| 310 | .mc_fini = &rs600_mc_fini, |
- | |
| 311 | // .wb_init = &r100_wb_init, |
- | |
| 312 | // .wb_fini = &r100_wb_fini, |
- | |
| 313 | .gart_init = &rs600_gart_init, |
258 | // .suspend = &rs600_suspend, |
| 314 | .gart_fini = &rs600_gart_fini, |
259 | // .resume = &rs600_resume, |
| 315 | .gart_enable = &rs600_gart_enable, |
260 | // .vga_set_state = &r100_vga_set_state, |
| 316 | .gart_disable = &rs600_gart_disable, |
261 | .gpu_reset = &r300_gpu_reset, |
| 317 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
262 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
| 318 | .gart_set_page = &rs600_gart_set_page, |
- | |
| 319 | .cp_init = &r100_cp_init, |
263 | .gart_set_page = &rs600_gart_set_page, |
| 320 | // .cp_fini = &r100_cp_fini, |
264 | // .cp_commit = &r100_cp_commit, |
| 321 | // .cp_disable = &r100_cp_disable, |
265 | // .ring_start = &r300_ring_start, |
| - | 266 | // .ring_test = &r100_ring_test, |
|
| 322 | .cp_commit = &r100_cp_commit, |
267 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 323 | .ring_start = &r300_ring_start, |
268 | // .irq_set = &rs600_irq_set, |
| 324 | // .irq_set = &rs600_irq_set, |
269 | // .irq_process = &rs600_irq_process, |
| 325 | // .irq_process = &r100_irq_process, |
270 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 326 | // .fence_ring_emit = &r300_fence_ring_emit, |
271 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 327 | // .cs_parse = &r300_cs_parse, |
272 | // .cs_parse = &r300_cs_parse, |
| 328 | // .copy_blit = &r100_copy_blit, |
273 | // .copy_blit = &r100_copy_blit, |
| 329 | // .copy_dma = &r300_copy_dma, |
274 | // .copy_dma = &r300_copy_dma, |
| 330 | // .copy = &r100_copy_blit, |
275 | // .copy = &r100_copy_blit, |
| 331 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
276 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 332 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
277 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 333... | Line 278... | ||
| 333 | // .set_pcie_lanes = NULL, |
278 | .set_pcie_lanes = NULL, |
| 334 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
279 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 335 | .bandwidth_update = &rs600_bandwidth_update, |
280 | .bandwidth_update = &rs600_bandwidth_update, |
| 336 | }; |
281 | }; |
| 337 | 282 | ||
| 338 | 283 | ||
| 339 | /* |
284 | /* |
| 340 | * rs690,rs740 |
285 | * rs690,rs740 |
| 341 | */ |
286 | */ |
| 342 | void rs690_errata(struct radeon_device *rdev); |
287 | int rs690_init(struct radeon_device *rdev); |
| 343 | void rs690_vram_info(struct radeon_device *rdev); |
288 | void rs690_fini(struct radeon_device *rdev); |
| 344 | int rs690_mc_init(struct radeon_device *rdev); |
289 | int rs690_resume(struct radeon_device *rdev); |
| 345 | void rs690_mc_fini(struct radeon_device *rdev); |
290 | int rs690_suspend(struct radeon_device *rdev); |
| 346 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
291 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| - | 292 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
|
| 347 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
293 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 348 | void rs690_bandwidth_update(struct radeon_device *rdev); |
294 | static struct radeon_asic rs690_asic = { |
| 349 | static struct radeon_asic rs690_asic = { |
- | |
| 350 | .init = &rs600_init, |
- | |
| 351 | .errata = &rs690_errata, |
- | |
| 352 | .vram_info = &rs690_vram_info, |
- | |
| 353 | .vga_set_state = &r100_vga_set_state, |
- | |
| 354 | .gpu_reset = &r300_gpu_reset, |
- | |
| 355 | .mc_init = &rs690_mc_init, |
- | |
| 356 | .mc_fini = &rs690_mc_fini, |
- | |
| 357 | // .wb_init = &r100_wb_init, |
295 | .init = &rs690_init, |
| 358 | // .wb_fini = &r100_wb_fini, |
296 | // .fini = &rs690_fini, |
| 359 | .gart_init = &rs400_gart_init, |
297 | // .suspend = &rs690_suspend, |
| 360 | .gart_fini = &rs400_gart_fini, |
298 | // .resume = &rs690_resume, |
| 361 | .gart_enable = &rs400_gart_enable, |
299 | // .vga_set_state = &r100_vga_set_state, |
| 362 | .gart_disable = &rs400_gart_disable, |
- | |
| 363 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
300 | .gpu_reset = &r300_gpu_reset, |
| 364 | .gart_set_page = &rs400_gart_set_page, |
301 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 365 | .cp_init = &r100_cp_init, |
302 | .gart_set_page = &rs400_gart_set_page, |
| - | 303 | // .cp_commit = &r100_cp_commit, |
|
| 366 | // .cp_fini = &r100_cp_fini, |
304 | // .ring_start = &r300_ring_start, |
| 367 | // .cp_disable = &r100_cp_disable, |
305 | // .ring_test = &r100_ring_test, |
| 368 | .cp_commit = &r100_cp_commit, |
306 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 369 | .ring_start = &r300_ring_start, |
307 | // .irq_set = &rs600_irq_set, |
| 370 | // .irq_set = &rs600_irq_set, |
308 | // .irq_process = &rs600_irq_process, |
| 371 | // .irq_process = &r100_irq_process, |
309 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 372 | // .fence_ring_emit = &r300_fence_ring_emit, |
310 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 373 | // .cs_parse = &r300_cs_parse, |
311 | // .cs_parse = &r300_cs_parse, |
| 374 | // .copy_blit = &r100_copy_blit, |
312 | // .copy_blit = &r100_copy_blit, |
| 375 | // .copy_dma = &r300_copy_dma, |
313 | // .copy_dma = &r300_copy_dma, |
| 376 | // .copy = &r300_copy_dma, |
314 | // .copy = &r300_copy_dma, |
| 377 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
315 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 378 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
316 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 379... | Line 317... | ||
| 379 | // .set_pcie_lanes = NULL, |
317 | .set_pcie_lanes = NULL, |
| 380 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
318 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 381 | .set_surface_reg = r100_set_surface_reg, |
319 | .set_surface_reg = r100_set_surface_reg, |
| 382 | .clear_surface_reg = r100_clear_surface_reg, |
320 | .clear_surface_reg = r100_clear_surface_reg, |
| 383 | .bandwidth_update = &rs690_bandwidth_update, |
321 | .bandwidth_update = &rs690_bandwidth_update, |
| 384 | }; |
- | |
| 385 | 322 | }; |
|
| 386 | - | ||
| 387 | /* |
- | |
| 388 | * rv515 |
323 | |
| 389 | */ |
324 | |
| 390 | int rv515_init(struct radeon_device *rdev); |
325 | /* |
| 391 | void rv515_errata(struct radeon_device *rdev); |
326 | * rv515 |
| 392 | void rv515_vram_info(struct radeon_device *rdev); |
327 | */ |
| 393 | int rv515_gpu_reset(struct radeon_device *rdev); |
328 | int rv515_init(struct radeon_device *rdev); |
| - | 329 | void rv515_fini(struct radeon_device *rdev); |
|
| - | 330 | int rv515_gpu_reset(struct radeon_device *rdev); |
|
| 394 | int rv515_mc_init(struct radeon_device *rdev); |
331 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 395 | void rv515_mc_fini(struct radeon_device *rdev); |
332 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 396 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
333 | void rv515_ring_start(struct radeon_device *rdev); |
| 397 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
334 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| - | 335 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
|
| 398 | void rv515_ring_start(struct radeon_device *rdev); |
336 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| 399 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
337 | int rv515_resume(struct radeon_device *rdev); |
| 400 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
- | |
| 401 | void rv515_bandwidth_update(struct radeon_device *rdev); |
- | |
| 402 | static struct radeon_asic rv515_asic = { |
- | |
| 403 | .init = &rv515_init, |
- | |
| 404 | .errata = &rv515_errata, |
- | |
| 405 | .vram_info = &rv515_vram_info, |
- | |
| 406 | .vga_set_state = &r100_vga_set_state, |
- | |
| 407 | .gpu_reset = &rv515_gpu_reset, |
- | |
| 408 | .mc_init = &rv515_mc_init, |
338 | int rv515_suspend(struct radeon_device *rdev); |
| 409 | .mc_fini = &rv515_mc_fini, |
339 | static struct radeon_asic rv515_asic = { |
| 410 | // .wb_init = &r100_wb_init, |
340 | .init = &rv515_init, |
| 411 | // .wb_fini = &r100_wb_fini, |
341 | // .fini = &rv515_fini, |
| 412 | .gart_init = &rv370_pcie_gart_init, |
342 | // .suspend = &rv515_suspend, |
| 413 | .gart_fini = &rv370_pcie_gart_fini, |
- | |
| 414 | .gart_enable = &rv370_pcie_gart_enable, |
343 | // .resume = &rv515_resume, |
| 415 | .gart_disable = &rv370_pcie_gart_disable, |
344 | // .vga_set_state = &r100_vga_set_state, |
| 416 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
345 | .gpu_reset = &rv515_gpu_reset, |
| - | 346 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
|
| 417 | .gart_set_page = &rv370_pcie_gart_set_page, |
347 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 418 | .cp_init = &r100_cp_init, |
348 | // .cp_commit = &r100_cp_commit, |
| 419 | // .cp_fini = &r100_cp_fini, |
349 | // .ring_start = &rv515_ring_start, |
| 420 | // .cp_disable = &r100_cp_disable, |
350 | // .ring_test = &r100_ring_test, |
| 421 | .cp_commit = &r100_cp_commit, |
351 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 422 | .ring_start = &rv515_ring_start, |
352 | // .irq_set = &rs600_irq_set, |
| 423 | // .irq_set = &r100_irq_set, |
353 | // .irq_process = &rs600_irq_process, |
| 424 | // .irq_process = &r100_irq_process, |
354 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 425 | // .fence_ring_emit = &r300_fence_ring_emit, |
355 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 426 | // .cs_parse = &r300_cs_parse, |
356 | // .cs_parse = &r300_cs_parse, |
| 427 | // .copy_blit = &r100_copy_blit, |
357 | // .copy_blit = &r100_copy_blit, |
| 428 | // .copy_dma = &r300_copy_dma, |
358 | // .copy_dma = &r300_copy_dma, |
| 429 | // .copy = &r100_copy_blit, |
359 | // .copy = &r100_copy_blit, |
| Line 430... | Line 360... | ||
| 430 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
360 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 431 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
361 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 432 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
362 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 433 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
- | |
| 434 | .set_surface_reg = r100_set_surface_reg, |
- | |
| 435 | .clear_surface_reg = r100_clear_surface_reg, |
363 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 436 | .bandwidth_update = &rv515_bandwidth_update, |
364 | .set_surface_reg = r100_set_surface_reg, |
| 437 | }; |
- | |
| 438 | 365 | .clear_surface_reg = r100_clear_surface_reg, |
|
| 439 | 366 | .bandwidth_update = &rv515_bandwidth_update, |
|
| - | 367 | }; |
|
| 440 | /* |
368 | |
| 441 | * r520,rv530,rv560,rv570,r580 |
369 | |
| 442 | */ |
370 | /* |
| 443 | void r520_errata(struct radeon_device *rdev); |
371 | * r520,rv530,rv560,rv570,r580 |
| 444 | void r520_vram_info(struct radeon_device *rdev); |
- | |
| 445 | int r520_mc_init(struct radeon_device *rdev); |
- | |
| 446 | void r520_mc_fini(struct radeon_device *rdev); |
- | |
| 447 | void r520_bandwidth_update(struct radeon_device *rdev); |
- | |
| 448 | static struct radeon_asic r520_asic = { |
- | |
| 449 | .init = &rv515_init, |
- | |
| 450 | .errata = &r520_errata, |
- | |
| 451 | .vram_info = &r520_vram_info, |
- | |
| 452 | .vga_set_state = &r100_vga_set_state, |
372 | */ |
| 453 | .gpu_reset = &rv515_gpu_reset, |
373 | int r520_init(struct radeon_device *rdev); |
| 454 | .mc_init = &r520_mc_init, |
374 | int r520_resume(struct radeon_device *rdev); |
| 455 | .mc_fini = &r520_mc_fini, |
- | |
| 456 | // .wb_init = &r100_wb_init, |
375 | static struct radeon_asic r520_asic = { |
| 457 | // .wb_fini = &r100_wb_fini, |
376 | .init = &r520_init, |
| 458 | .gart_init = &rv370_pcie_gart_init, |
377 | // .fini = &rv515_fini, |
| 459 | .gart_fini = &rv370_pcie_gart_fini, |
378 | // .suspend = &rv515_suspend, |
| 460 | .gart_enable = &rv370_pcie_gart_enable, |
379 | // .resume = &r520_resume, |
| - | 380 | // .vga_set_state = &r100_vga_set_state, |
|
| 461 | .gart_disable = &rv370_pcie_gart_disable, |
381 | .gpu_reset = &rv515_gpu_reset, |
| 462 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
382 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 463 | .gart_set_page = &rv370_pcie_gart_set_page, |
383 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 464 | .cp_init = &r100_cp_init, |
384 | // .cp_commit = &r100_cp_commit, |
| 465 | // .cp_fini = &r100_cp_fini, |
385 | // .ring_start = &rv515_ring_start, |
| 466 | // .cp_disable = &r100_cp_disable, |
386 | // .ring_test = &r100_ring_test, |
| 467 | .cp_commit = &r100_cp_commit, |
387 | // .ring_ib_execute = &r100_ring_ib_execute, |
| 468 | .ring_start = &rv515_ring_start, |
388 | // .irq_set = &rs600_irq_set, |
| 469 | // .irq_set = &r100_irq_set, |
389 | // .irq_process = &rs600_irq_process, |
| 470 | // .irq_process = &r100_irq_process, |
390 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 471 | // .fence_ring_emit = &r300_fence_ring_emit, |
391 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 472 | // .cs_parse = &r300_cs_parse, |
392 | // .cs_parse = &r300_cs_parse, |
| 473 | // .copy_blit = &r100_copy_blit, |
393 | // .copy_blit = &r100_copy_blit, |
| Line 474... | Line 394... | ||
| 474 | // .copy_dma = &r300_copy_dma, |
394 | // .copy_dma = &r300_copy_dma, |
| 475 | // .copy = &r100_copy_blit, |
395 | // .copy = &r100_copy_blit, |
| 476 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
396 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 477 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
397 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 478 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
398 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 479 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
399 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 480 | .set_surface_reg = r100_set_surface_reg, |
400 | .set_surface_reg = r100_set_surface_reg, |