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| Rev 1117 | Rev 1119 | ||
|---|---|---|---|
| Line 399... | Line 399... | ||
| 399 | static struct radeon_asic r520_asic = { |
399 | static struct radeon_asic r520_asic = { |
| 400 | .init = &rv515_init, |
400 | .init = &rv515_init, |
| 401 | .errata = &r520_errata, |
401 | .errata = &r520_errata, |
| 402 | .vram_info = &r520_vram_info, |
402 | .vram_info = &r520_vram_info, |
| 403 | .gpu_reset = &rv515_gpu_reset, |
403 | .gpu_reset = &rv515_gpu_reset, |
| 404 | // .mc_init = &r520_mc_init, |
404 | .mc_init = &r520_mc_init, |
| 405 | // .mc_fini = &r520_mc_fini, |
405 | .mc_fini = &r520_mc_fini, |
| 406 | // .wb_init = &r100_wb_init, |
406 | // .wb_init = &r100_wb_init, |
| 407 | // .wb_fini = &r100_wb_fini, |
407 | // .wb_fini = &r100_wb_fini, |
| 408 | // .gart_enable = &r300_gart_enable, |
408 | .gart_enable = &r300_gart_enable, |
| 409 | // .gart_disable = &rv370_pcie_gart_disable, |
409 | .gart_disable = &rv370_pcie_gart_disable, |
| 410 | // .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
410 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 411 | // .gart_set_page = &rv370_pcie_gart_set_page, |
411 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 412 | // .cp_init = &r100_cp_init, |
412 | .cp_init = &r100_cp_init, |
| 413 | // .cp_fini = &r100_cp_fini, |
413 | // .cp_fini = &r100_cp_fini, |
| 414 | // .cp_disable = &r100_cp_disable, |
414 | // .cp_disable = &r100_cp_disable, |
| 415 | // .ring_start = &rv515_ring_start, |
415 | .ring_start = &rv515_ring_start, |
| 416 | // .irq_set = &r100_irq_set, |
416 | // .irq_set = &r100_irq_set, |
| 417 | // .irq_process = &r100_irq_process, |
417 | // .irq_process = &r100_irq_process, |
| 418 | // .fence_ring_emit = &r300_fence_ring_emit, |
418 | // .fence_ring_emit = &r300_fence_ring_emit, |
| 419 | // .cs_parse = &r300_cs_parse, |
419 | // .cs_parse = &r300_cs_parse, |
| 420 | // .copy_blit = &r100_copy_blit, |
420 | // .copy_blit = &r100_copy_blit, |