WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_asic.c



 
//#include 
#include 
#include 
#include 
 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"

		rdev->pciep_rreg = &r600_pciep_rreg;
		rdev->pciep_wreg = &r600_pciep_wreg;
	}
}

 
static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
						    u32 reg, u32 *val)
{
	return -EINVAL;

}
 
/* helper to disable agp */
/**

			rdev->family == CHIP_RV410 ||
			rdev->family == CHIP_R423) {
		DRM_INFO("Forcing AGP to PCIE mode\n");
		rdev->flags |= RADEON_IS_PCIE;
		rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
		rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
		rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
	} else {
		DRM_INFO("Forcing AGP to PCI mode\n");
		rdev->flags |= RADEON_IS_PCI;
		rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
		rdev->asic->gart.set_page = &r100_pci_gart_set_page;
	}
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
}

	.set_wptr = &r100_gfx_set_wptr,
};

 
static struct radeon_asic r100_asic = {
	.init = &r100_init,
	.fini = &r100_fini,
//	.suspend = &r100_suspend,
//	.resume = &r100_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r100_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r100_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r100_pci_gart_tlb_flush,
		.get_page_entry = &r100_pci_gart_get_page_entry,
		.set_page = &r100_pci_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring

	},
};

 
static struct radeon_asic r200_asic = {
	.init = &r100_init,
	.fini = &r100_fini,
//	.suspend = &r100_suspend,
//	.resume = &r100_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r100_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r100_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r100_pci_gart_tlb_flush,
		.get_page_entry = &r100_pci_gart_get_page_entry,
		.set_page = &r100_pci_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring

	.get_rptr = &r100_gfx_get_rptr,
	.get_wptr = &r100_gfx_get_wptr,
	.set_wptr = &r100_gfx_set_wptr,
};

 
static struct radeon_asic_ring rv515_gfx_ring = {
	.ib_execute = &r100_ring_ib_execute,
	.emit_fence = &r300_fence_ring_emit,
	.emit_semaphore = &r100_semaphore_ring_emit,
	.cs_parse = &r300_cs_parse,
	.ring_start = &rv515_ring_start,
	.ring_test = &r100_ring_test,
	.ib_test = &r100_ib_test,
	.is_lockup = &r100_gpu_is_lockup,
	.get_rptr = &r100_gfx_get_rptr,
	.get_wptr = &r100_gfx_get_wptr,
	.set_wptr = &r100_gfx_set_wptr,
};
 
static struct radeon_asic r300_asic = {
	.init = &r300_init,
	.fini = &r300_fini,
//	.suspend = &r300_suspend,
//	.resume = &r300_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r300_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r300_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r100_pci_gart_tlb_flush,
		.get_page_entry = &r100_pci_gart_get_page_entry,
		.set_page = &r100_pci_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

	},
};

 
static struct radeon_asic r300_asic_pcie = {
	.init = &r300_init,
	.fini = &r300_fini,
//	.suspend = &r300_suspend,
//	.resume = &r300_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r300_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r300_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rv370_pcie_gart_tlb_flush,
		.get_page_entry = &rv370_pcie_gart_get_page_entry,
		.set_page = &rv370_pcie_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

	},
};

 
static struct radeon_asic r420_asic = {
	.init = &r420_init,
	.fini = &r420_fini,
//	.suspend = &r420_suspend,
//	.resume = &r420_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r300_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r300_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rv370_pcie_gart_tlb_flush,
		.get_page_entry = &rv370_pcie_gart_get_page_entry,
		.set_page = &rv370_pcie_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

	},
};

 
static struct radeon_asic rs400_asic = {
	.init = &rs400_init,
	.fini = &rs400_fini,
//	.suspend = &rs400_suspend,
//	.resume = &rs400_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &r300_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rs400_gart_tlb_flush,
		.get_page_entry = &rs400_gart_get_page_entry,
		.set_page = &rs400_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

	},
};

 
static struct radeon_asic rs600_asic = {
	.init = &rs600_init,
	.fini = &rs600_fini,
//	.suspend = &rs600_suspend,
//	.resume = &rs600_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &rs600_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rs600_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

		.bandwidth_update = &rs600_bandwidth_update,
		.get_vblank_counter = &rs600_get_vblank_counter,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r100_copy_blit,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &r200_copy_dma,

	},
};

 
static struct radeon_asic rs690_asic = {
	.init = &rs690_init,
	.fini = &rs690_fini,
//	.suspend = &rs690_suspend,
//	.resume = &rs690_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &rs600_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rs400_gart_tlb_flush,
		.get_page_entry = &rs400_gart_get_page_entry,
		.set_page = &rs400_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring

		.get_vblank_counter = &rs600_get_vblank_counter,
		.bandwidth_update = &rs690_bandwidth_update,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r100_copy_blit,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &r200_copy_dma,

	},
};

 
static struct radeon_asic rv515_asic = {
	.init = &rv515_init,
	.fini = &rv515_fini,
//	.suspend = &rv515_suspend,
//	.resume = &rv515_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &rs600_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rv370_pcie_gart_tlb_flush,
		.get_page_entry = &rv370_pcie_gart_get_page_entry,
		.set_page = &rv370_pcie_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
	},
	.irq = {
		.set = &rs600_irq_set,
		.process = &rs600_irq_process,

	},
};

 
static struct radeon_asic r520_asic = {
	.init = &r520_init,
	.fini = &rv515_fini,
//	.suspend = &rv515_suspend,
//	.resume = &r520_resume,
//	.vga_set_state = &r100_vga_set_state,
	.asic_reset = &rs600_asic_reset,
	.mmio_hdp_flush = NULL,
	.gui_idle = &r100_gui_idle,
	.mc_wait_for_idle = &r520_mc_wait_for_idle,
	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
	.gart = {
		.tlb_flush = &rv370_pcie_gart_tlb_flush,
		.get_page_entry = &rv370_pcie_gart_get_page_entry,
		.set_page = &rv370_pcie_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
	},
	.irq = {
		.set = &rs600_irq_set,
		.process = &rs600_irq_process,

	.set_wptr = &r600_dma_set_wptr,
};

 
static struct radeon_asic r600_asic = {
	.init = &r600_init,
	.fini = &r600_fini,
//	.suspend = &r600_suspend,
//	.resume = &r600_resume,
//	.vga_set_state = &r600_vga_set_state,
	.asic_reset = &r600_asic_reset,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &r600_mc_wait_for_idle,
	.get_xclk = &r600_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = r600_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r600_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,

		.bandwidth_update = &rv515_bandwidth_update,
		.get_vblank_counter = &rs600_get_vblank_counter,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &r600_copy_dma,

//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static struct radeon_asic_ring rv6xx_uvd_ring = {
	.ib_execute = &uvd_v1_0_ib_execute,
	.emit_fence = &uvd_v1_0_fence_emit,
	.emit_semaphore = &uvd_v1_0_semaphore_emit,
	.cs_parse = &radeon_uvd_cs_parse,
	.ring_test = &uvd_v1_0_ring_test,
	.ib_test = &uvd_v1_0_ib_test,
	.is_lockup = &radeon_ring_test_lockup,
	.get_rptr = &uvd_v1_0_get_rptr,
	.get_wptr = &uvd_v1_0_get_wptr,
	.set_wptr = &uvd_v1_0_set_wptr,
};
 
static struct radeon_asic rv6xx_asic = {
	.init = &r600_init,
	.fini = &r600_fini,
//	.suspend = &r600_suspend,
//	.resume = &r600_resume,
//	.vga_set_state = &r600_vga_set_state,
	.asic_reset = &r600_asic_reset,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &r600_mc_wait_for_idle,
	.get_xclk = &r600_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = r600_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r600_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
	},
	.irq = {
		.set = &r600_irq_set,
		.process = &r600_irq_process,

		.bandwidth_update = &rv515_bandwidth_update,
		.get_vblank_counter = &rs600_get_vblank_counter,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &r600_copy_dma,

		.get_sclk = &rv6xx_dpm_get_sclk,
		.get_mclk = &rv6xx_dpm_get_mclk,
		.print_power_state = &rv6xx_dpm_print_power_state,
		.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &rv6xx_dpm_force_performance_level,
		.get_current_sclk = &rv6xx_dpm_get_current_sclk,
		.get_current_mclk = &rv6xx_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static struct radeon_asic rs780_asic = {
	.init = &r600_init,
	.fini = &r600_fini,
//	.suspend = &r600_suspend,
//	.resume = &r600_resume,
//	.vga_set_state = &r600_vga_set_state,
	.asic_reset = &r600_asic_reset,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &r600_mc_wait_for_idle,
	.get_xclk = &r600_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = r600_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r600_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
	},
	.irq = {
		.set = &r600_irq_set,
		.process = &r600_irq_process,

		.bandwidth_update = &rs690_bandwidth_update,
		.get_vblank_counter = &rs600_get_vblank_counter,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &r600_copy_dma,

		.get_sclk = &rs780_dpm_get_sclk,
		.get_mclk = &rs780_dpm_get_mclk,
		.print_power_state = &rs780_dpm_print_power_state,
		.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &rs780_dpm_force_performance_level,
		.get_current_sclk = &rs780_dpm_get_current_sclk,
		.get_current_mclk = &rs780_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rs600_page_flip,
	},
};

 
static struct radeon_asic_ring rv770_uvd_ring = {
	.ib_execute = &uvd_v1_0_ib_execute,
	.emit_fence = &uvd_v2_2_fence_emit,
	.emit_semaphore = &uvd_v2_2_semaphore_emit,
	.cs_parse = &radeon_uvd_cs_parse,
	.ring_test = &uvd_v1_0_ring_test,
	.ib_test = &uvd_v1_0_ib_test,
	.is_lockup = &radeon_ring_test_lockup,

	.set_wptr = &uvd_v1_0_set_wptr,
};

 
static struct radeon_asic rv770_asic = {
	.init = &rv770_init,
	.fini = &rv770_fini,
//	.suspend = &rv770_suspend,
//	.resume = &rv770_resume,
	.asic_reset = &r600_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &r600_mc_wait_for_idle,
	.get_xclk = &rv770_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = r600_get_allowed_info_register,
	.gart = {
		.tlb_flush = &r600_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,

		.bandwidth_update = &rv515_bandwidth_update,
		.get_vblank_counter = &rs600_get_vblank_counter,
		.wait_for_vblank = &avivo_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &rv770_copy_dma,

		.get_mclk = &rv770_dpm_get_mclk,
		.print_power_state = &rv770_dpm_print_power_state,
		.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &rv770_dpm_force_performance_level,
		.vblank_too_short = &rv770_dpm_vblank_too_short,
		.get_current_sclk = &rv770_dpm_get_current_sclk,
		.get_current_mclk = &rv770_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &rs600_pre_page_flip,
//		.page_flip = &rv770_page_flip,
	},

	.set_wptr = &r600_dma_set_wptr,
};

 
static struct radeon_asic evergreen_asic = {
	.init = &evergreen_init,
	.fini = &evergreen_fini,
//	.suspend = &evergreen_suspend,
//	.resume = &evergreen_resume,
	.asic_reset = &evergreen_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &rv770_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = evergreen_get_allowed_info_register,
	.gart = {
		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,

		.bandwidth_update = &evergreen_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &evergreen_copy_dma,

		.get_mclk = &rv770_dpm_get_mclk,
		.print_power_state = &rv770_dpm_print_power_state,
		.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &rv770_dpm_force_performance_level,
		.vblank_too_short = &cypress_dpm_vblank_too_short,
		.get_current_sclk = &rv770_dpm_get_current_sclk,
		.get_current_mclk = &rv770_dpm_get_current_mclk,
	},
	.pflip = {
	},
};

 
static struct radeon_asic sumo_asic = {
	.init = &evergreen_init,
	.fini = &evergreen_fini,
//	.suspend = &evergreen_suspend,
//	.resume = &evergreen_resume,
	.asic_reset = &evergreen_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &r600_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = evergreen_get_allowed_info_register,
	.gart = {
		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,

		.bandwidth_update = &evergreen_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &evergreen_copy_dma,

		.get_sclk = &sumo_dpm_get_sclk,
		.get_mclk = &sumo_dpm_get_mclk,
		.print_power_state = &sumo_dpm_print_power_state,
		.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &sumo_dpm_force_performance_level,
		.get_current_sclk = &sumo_dpm_get_current_sclk,
		.get_current_mclk = &sumo_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static struct radeon_asic btc_asic = {
	.init = &evergreen_init,
	.fini = &evergreen_fini,
//	.suspend = &evergreen_suspend,
//	.resume = &evergreen_resume,
	.asic_reset = &evergreen_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &rv770_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = evergreen_get_allowed_info_register,
	.gart = {
		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.ring = {
		[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,

		.bandwidth_update = &evergreen_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &evergreen_copy_dma,

		.get_mclk = &btc_dpm_get_mclk,
		.print_power_state = &rv770_dpm_print_power_state,
		.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &rv770_dpm_force_performance_level,
		.vblank_too_short = &btc_dpm_vblank_too_short,
		.get_current_sclk = &btc_dpm_get_current_sclk,
		.get_current_mclk = &btc_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},

	.set_wptr = &uvd_v1_0_set_wptr,
};

 
static struct radeon_asic cayman_asic = {
	.init = &cayman_init,
	.fini = &cayman_fini,
//	.suspend = &cayman_suspend,
//	.resume = &cayman_resume,
	.asic_reset = &cayman_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &rv770_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = cayman_get_allowed_info_register,
	.gart = {
		.tlb_flush = &cayman_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.vm = {
		.init = &cayman_vm_init,

		.bandwidth_update = &evergreen_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &evergreen_copy_dma,

		.get_mclk = &ni_dpm_get_mclk,
		.print_power_state = &ni_dpm_print_power_state,
		.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &ni_dpm_force_performance_level,
		.vblank_too_short = &ni_dpm_vblank_too_short,
		.get_current_sclk = &ni_dpm_get_current_sclk,
		.get_current_mclk = &ni_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static struct radeon_asic_ring trinity_vce_ring = {
	.ib_execute = &radeon_vce_ib_execute,
	.emit_fence = &radeon_vce_fence_emit,
	.emit_semaphore = &radeon_vce_semaphore_emit,
	.cs_parse = &radeon_vce_cs_parse,
	.ring_test = &radeon_vce_ring_test,
	.ib_test = &radeon_vce_ib_test,
	.is_lockup = &radeon_ring_test_lockup,
	.get_rptr = &vce_v1_0_get_rptr,
	.get_wptr = &vce_v1_0_get_wptr,
	.set_wptr = &vce_v1_0_set_wptr,
};
 
static struct radeon_asic trinity_asic = {
	.init = &cayman_init,
	.fini = &cayman_fini,
//	.suspend = &cayman_suspend,
//	.resume = &cayman_resume,
	.asic_reset = &cayman_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &r600_get_xclk,
	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
	.get_allowed_info_register = cayman_get_allowed_info_register,
	.gart = {
		.tlb_flush = &cayman_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.vm = {
		.init = &cayman_vm_init,

		[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
	},
	.irq = {
		.set = &evergreen_irq_set,
		.process = &evergreen_irq_process,
	},

		.bandwidth_update = &dce6_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &evergreen_copy_dma,

		.set_memory_clock = NULL,
		.get_pcie_lanes = NULL,
		.set_pcie_lanes = NULL,
		.set_clock_gating = NULL,
		.set_uvd_clocks = &sumo_set_uvd_clocks,
		.set_vce_clocks = &tn_set_vce_clocks,
		.get_temperature = &tn_get_temp,
	},
	.dpm = {
		.init = &trinity_dpm_init,
		.setup_asic = &trinity_dpm_setup_asic,

		.get_mclk = &trinity_dpm_get_mclk,
		.print_power_state = &trinity_dpm_print_power_state,
		.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &trinity_dpm_force_performance_level,
		.enable_bapm = &trinity_dpm_enable_bapm,
		.get_current_sclk = &trinity_dpm_get_current_sclk,
		.get_current_mclk = &trinity_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},

	.set_wptr = &cayman_dma_set_wptr,
};

 
static struct radeon_asic si_asic = {
	.init = &si_init,
	.fini = &si_fini,
//	.suspend = &si_suspend,
	.resume = &si_resume,
	.asic_reset = &si_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &si_get_xclk,
	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
	.get_allowed_info_register = si_get_allowed_info_register,
	.gart = {
		.tlb_flush = &si_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.vm = {
		.init = &si_vm_init,

		[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
		[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
		[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
		[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
		[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
	},
	.irq = {
		.set = &si_irq_set,
		.process = &si_irq_process,
	},

		.bandwidth_update = &dce6_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &r600_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &si_copy_dma,

		.set_memory_clock = &radeon_atom_set_memory_clock,
		.get_pcie_lanes = &r600_get_pcie_lanes,
		.set_pcie_lanes = &r600_set_pcie_lanes,
		.set_clock_gating = NULL,
		.set_uvd_clocks = &si_set_uvd_clocks,
		.set_vce_clocks = &si_set_vce_clocks,
		.get_temperature = &si_get_temp,
	},
	.dpm = {
		.init = &si_dpm_init,
		.setup_asic = &si_dpm_setup_asic,

		.get_mclk = &ni_dpm_get_mclk,
		.print_power_state = &ni_dpm_print_power_state,
		.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &si_dpm_force_performance_level,
		.vblank_too_short = &ni_dpm_vblank_too_short,
		.fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
		.fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
		.get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
		.set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
		.get_current_sclk = &si_dpm_get_current_sclk,
		.get_current_mclk = &si_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},

	.set_wptr = &vce_v1_0_set_wptr,
};

 
static struct radeon_asic ci_asic = {
	.init = &cik_init,
	.fini = &cik_fini,
//	.suspend = &cik_suspend,
//	.resume = &cik_resume,
	.asic_reset = &cik_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = &r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &cik_get_xclk,
	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
	.get_allowed_info_register = cik_get_allowed_info_register,
	.gart = {
		.tlb_flush = &cik_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.vm = {
		.init = &cik_vm_init,

		.bandwidth_update = &dce8_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &cik_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &cik_copy_dma,

		.print_power_state = &ci_dpm_print_power_state,
		.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &ci_dpm_force_performance_level,
		.vblank_too_short = &ci_dpm_vblank_too_short,
		.powergate_uvd = &ci_dpm_powergate_uvd,
		.fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
		.fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
		.get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
		.set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
		.get_current_sclk = &ci_dpm_get_current_sclk,
		.get_current_mclk = &ci_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},
};

 
static struct radeon_asic kv_asic = {
	.init = &cik_init,
	.fini = &cik_fini,
//	.suspend = &cik_suspend,
//	.resume = &cik_resume,
	.asic_reset = &cik_asic_reset,
//	.vga_set_state = &r600_vga_set_state,
	.mmio_hdp_flush = &r600_mmio_hdp_flush,
	.gui_idle = &r600_gui_idle,
	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
	.get_xclk = &cik_get_xclk,
	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
	.get_allowed_info_register = cik_get_allowed_info_register,
	.gart = {
		.tlb_flush = &cik_pcie_gart_tlb_flush,
		.get_page_entry = &rs600_gart_get_page_entry,
		.set_page = &rs600_gart_set_page,
	},
	.vm = {
		.init = &cik_vm_init,

		.bandwidth_update = &dce8_bandwidth_update,
		.get_vblank_counter = &evergreen_get_vblank_counter,
		.wait_for_vblank = &dce4_wait_for_vblank,
		.set_backlight_level = &atombios_set_backlight_level,
		.get_backlight_level = &atombios_get_backlight_level,
 
 
	},
	.copy = {
		.blit = &cik_copy_cpdma,
		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		.dma = &cik_copy_dma,

		.print_power_state = &kv_dpm_print_power_state,
		.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
		.force_performance_level = &kv_dpm_force_performance_level,
		.powergate_uvd = &kv_dpm_powergate_uvd,
		.enable_bapm = &kv_dpm_enable_bapm,
		.get_current_sclk = &kv_dpm_get_current_sclk,
		.get_current_mclk = &kv_dpm_get_current_mclk,
	},
	.pflip = {
//		.pre_page_flip = &evergreen_pre_page_flip,
//		.page_flip = &evergreen_page_flip,
	},

	case CHIP_ARUBA:
		rdev->asic = &trinity_asic;
		/* set num crtcs */
		rdev->num_crtc = 4;
		rdev->has_uvd = true;
		rdev->cg_flags =
			RADEON_CG_SUPPORT_VCE_MGCG;
		break;
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_VERDE:
	case CHIP_OLAND:

Rev 5271	Rev 6104
Line 28...	Line 28...
28		28
29	//#include	29	//#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	//#include	-
34	//#include	33	#include
35	#include "radeon_reg.h"	34	#include "radeon_reg.h"
36	#include "radeon.h"	35	#include "radeon.h"
37	#include "radeon_asic.h"	36	#include "radeon_asic.h"
Line 134...	Line 133...
134	rdev->pciep_rreg = &r600_pciep_rreg;	133	rdev->pciep_rreg = &r600_pciep_rreg;
135	rdev->pciep_wreg = &r600_pciep_wreg;	134	rdev->pciep_wreg = &r600_pciep_wreg;
136	}	135	}
137	}	136	}
Line -...	Line 137...
-		137
-		138	static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
-		139	u32 reg, u32 *val)
-		140	{
-		141	return -EINVAL;
Line 138...	Line 142...
138		142	}
139		143
140	/* helper to disable agp */	144	/* helper to disable agp */
141	/**	145	/**
Line 157...	Line 161...
157	rdev->family == CHIP_RV410 \|\|	161	rdev->family == CHIP_RV410 \|\|
158	rdev->family == CHIP_R423) {	162	rdev->family == CHIP_R423) {
159	DRM_INFO("Forcing AGP to PCIE mode\n");	163	DRM_INFO("Forcing AGP to PCIE mode\n");
160	rdev->flags \|= RADEON_IS_PCIE;	164	rdev->flags \|= RADEON_IS_PCIE;
161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;	165	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
-		166	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;	167	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163	} else {	168	} else {
164	DRM_INFO("Forcing AGP to PCI mode\n");	169	DRM_INFO("Forcing AGP to PCI mode\n");
165	rdev->flags \|= RADEON_IS_PCI;	170	rdev->flags \|= RADEON_IS_PCI;
166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;	171	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
-		172	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;	173	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168	}	174	}
169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;	175	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170	}	176	}
Line 187...	Line 193...
187	.set_wptr = &r100_gfx_set_wptr,	193	.set_wptr = &r100_gfx_set_wptr,
188	};	194	};
Line 189...	Line 195...
189		195
190	static struct radeon_asic r100_asic = {	196	static struct radeon_asic r100_asic = {
191	.init = &r100_init,	197	.init = &r100_init,
192	// .fini = &r100_fini,	198	.fini = &r100_fini,
193	// .suspend = &r100_suspend,	199	// .suspend = &r100_suspend,
194	// .resume = &r100_resume,	200	// .resume = &r100_resume,
195	// .vga_set_state = &r100_vga_set_state,	201	// .vga_set_state = &r100_vga_set_state,
196	.asic_reset = &r100_asic_reset,	202	.asic_reset = &r100_asic_reset,
197	.mmio_hdp_flush = NULL,	203	.mmio_hdp_flush = NULL,
198	.gui_idle = &r100_gui_idle,	204	.gui_idle = &r100_gui_idle,
-		205	.mc_wait_for_idle = &r100_mc_wait_for_idle,
199	.mc_wait_for_idle = &r100_mc_wait_for_idle,	206	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
200	.gart = {	207	.gart = {
-		208	.tlb_flush = &r100_pci_gart_tlb_flush,
201	.tlb_flush = &r100_pci_gart_tlb_flush,	209	.get_page_entry = &r100_pci_gart_get_page_entry,
202	.set_page = &r100_pci_gart_set_page,	210	.set_page = &r100_pci_gart_set_page,
203	},	211	},
204	.ring = {	212	.ring = {
205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	213	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
Line 253...	Line 261...
253	},	261	},
254	};	262	};
Line 255...	Line 263...
255		263
256	static struct radeon_asic r200_asic = {	264	static struct radeon_asic r200_asic = {
257	.init = &r100_init,	265	.init = &r100_init,
258	// .fini = &r100_fini,	266	.fini = &r100_fini,
259	// .suspend = &r100_suspend,	267	// .suspend = &r100_suspend,
260	// .resume = &r100_resume,	268	// .resume = &r100_resume,
261	// .vga_set_state = &r100_vga_set_state,	269	// .vga_set_state = &r100_vga_set_state,
262	.asic_reset = &r100_asic_reset,	270	.asic_reset = &r100_asic_reset,
263	.mmio_hdp_flush = NULL,	271	.mmio_hdp_flush = NULL,
264	.gui_idle = &r100_gui_idle,	272	.gui_idle = &r100_gui_idle,
-		273	.mc_wait_for_idle = &r100_mc_wait_for_idle,
265	.mc_wait_for_idle = &r100_mc_wait_for_idle,	274	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
266	.gart = {	275	.gart = {
-		276	.tlb_flush = &r100_pci_gart_tlb_flush,
267	.tlb_flush = &r100_pci_gart_tlb_flush,	277	.get_page_entry = &r100_pci_gart_get_page_entry,
268	.set_page = &r100_pci_gart_set_page,	278	.set_page = &r100_pci_gart_set_page,
269	},	279	},
270	.ring = {	280	.ring = {
271	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring	281	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
Line 331...	Line 341...
331	.get_rptr = &r100_gfx_get_rptr,	341	.get_rptr = &r100_gfx_get_rptr,
332	.get_wptr = &r100_gfx_get_wptr,	342	.get_wptr = &r100_gfx_get_wptr,
333	.set_wptr = &r100_gfx_set_wptr,	343	.set_wptr = &r100_gfx_set_wptr,
334	};	344	};
Line -...	Line 345...
-		345
-		346	static struct radeon_asic_ring rv515_gfx_ring = {
-		347	.ib_execute = &r100_ring_ib_execute,
-		348	.emit_fence = &r300_fence_ring_emit,
-		349	.emit_semaphore = &r100_semaphore_ring_emit,
-		350	.cs_parse = &r300_cs_parse,
-		351	.ring_start = &rv515_ring_start,
-		352	.ring_test = &r100_ring_test,
-		353	.ib_test = &r100_ib_test,
-		354	.is_lockup = &r100_gpu_is_lockup,
-		355	.get_rptr = &r100_gfx_get_rptr,
-		356	.get_wptr = &r100_gfx_get_wptr,
-		357	.set_wptr = &r100_gfx_set_wptr,
-		358	};
335		359
336	static struct radeon_asic r300_asic = {	360	static struct radeon_asic r300_asic = {
337	.init = &r300_init,	361	.init = &r300_init,
338	// .fini = &r300_fini,	362	.fini = &r300_fini,
339	// .suspend = &r300_suspend,	363	// .suspend = &r300_suspend,
340	// .resume = &r300_resume,	364	// .resume = &r300_resume,
341	// .vga_set_state = &r100_vga_set_state,	365	// .vga_set_state = &r100_vga_set_state,
342	.asic_reset = &r300_asic_reset,	366	.asic_reset = &r300_asic_reset,
343	.mmio_hdp_flush = NULL,	367	.mmio_hdp_flush = NULL,
344	.gui_idle = &r100_gui_idle,	368	.gui_idle = &r100_gui_idle,
-		369	.mc_wait_for_idle = &r300_mc_wait_for_idle,
345	.mc_wait_for_idle = &r300_mc_wait_for_idle,	370	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
346	.gart = {	371	.gart = {
-		372	.tlb_flush = &r100_pci_gart_tlb_flush,
347	.tlb_flush = &r100_pci_gart_tlb_flush,	373	.get_page_entry = &r100_pci_gart_get_page_entry,
348	.set_page = &r100_pci_gart_set_page,	374	.set_page = &r100_pci_gart_set_page,
349	},	375	},
350	.ring = {	376	.ring = {
351	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	377	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 399...	Line 425...
399	},	425	},
400	};	426	};
Line 401...	Line 427...
401		427
402	static struct radeon_asic r300_asic_pcie = {	428	static struct radeon_asic r300_asic_pcie = {
403	.init = &r300_init,	429	.init = &r300_init,
404	// .fini = &r300_fini,	430	.fini = &r300_fini,
405	// .suspend = &r300_suspend,	431	// .suspend = &r300_suspend,
406	// .resume = &r300_resume,	432	// .resume = &r300_resume,
407	// .vga_set_state = &r100_vga_set_state,	433	// .vga_set_state = &r100_vga_set_state,
408	.asic_reset = &r300_asic_reset,	434	.asic_reset = &r300_asic_reset,
409	.mmio_hdp_flush = NULL,	435	.mmio_hdp_flush = NULL,
410	.gui_idle = &r100_gui_idle,	436	.gui_idle = &r100_gui_idle,
-		437	.mc_wait_for_idle = &r300_mc_wait_for_idle,
411	.mc_wait_for_idle = &r300_mc_wait_for_idle,	438	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
412	.gart = {	439	.gart = {
-		440	.tlb_flush = &rv370_pcie_gart_tlb_flush,
413	.tlb_flush = &rv370_pcie_gart_tlb_flush,	441	.get_page_entry = &rv370_pcie_gart_get_page_entry,
414	.set_page = &rv370_pcie_gart_set_page,	442	.set_page = &rv370_pcie_gart_set_page,
415	},	443	},
416	.ring = {	444	.ring = {
417	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	445	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 465...	Line 493...
465	},	493	},
466	};	494	};
Line 467...	Line 495...
467		495
468	static struct radeon_asic r420_asic = {	496	static struct radeon_asic r420_asic = {
469	.init = &r420_init,	497	.init = &r420_init,
470	// .fini = &r420_fini,	498	.fini = &r420_fini,
471	// .suspend = &r420_suspend,	499	// .suspend = &r420_suspend,
472	// .resume = &r420_resume,	500	// .resume = &r420_resume,
473	// .vga_set_state = &r100_vga_set_state,	501	// .vga_set_state = &r100_vga_set_state,
474	.asic_reset = &r300_asic_reset,	502	.asic_reset = &r300_asic_reset,
475	.mmio_hdp_flush = NULL,	503	.mmio_hdp_flush = NULL,
476	.gui_idle = &r100_gui_idle,	504	.gui_idle = &r100_gui_idle,
-		505	.mc_wait_for_idle = &r300_mc_wait_for_idle,
477	.mc_wait_for_idle = &r300_mc_wait_for_idle,	506	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
478	.gart = {	507	.gart = {
-		508	.tlb_flush = &rv370_pcie_gart_tlb_flush,
479	.tlb_flush = &rv370_pcie_gart_tlb_flush,	509	.get_page_entry = &rv370_pcie_gart_get_page_entry,
480	.set_page = &rv370_pcie_gart_set_page,	510	.set_page = &rv370_pcie_gart_set_page,
481	},	511	},
482	.ring = {	512	.ring = {
483	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	513	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 531...	Line 561...
531	},	561	},
532	};	562	};
Line 533...	Line 563...
533		563
534	static struct radeon_asic rs400_asic = {	564	static struct radeon_asic rs400_asic = {
535	.init = &rs400_init,	565	.init = &rs400_init,
536	// .fini = &rs400_fini,	566	.fini = &rs400_fini,
537	// .suspend = &rs400_suspend,	567	// .suspend = &rs400_suspend,
538	// .resume = &rs400_resume,	568	// .resume = &rs400_resume,
539	// .vga_set_state = &r100_vga_set_state,	569	// .vga_set_state = &r100_vga_set_state,
540	.asic_reset = &r300_asic_reset,	570	.asic_reset = &r300_asic_reset,
541	.mmio_hdp_flush = NULL,	571	.mmio_hdp_flush = NULL,
542	.gui_idle = &r100_gui_idle,	572	.gui_idle = &r100_gui_idle,
-		573	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
543	.mc_wait_for_idle = &rs400_mc_wait_for_idle,	574	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
544	.gart = {	575	.gart = {
-		576	.tlb_flush = &rs400_gart_tlb_flush,
545	.tlb_flush = &rs400_gart_tlb_flush,	577	.get_page_entry = &rs400_gart_get_page_entry,
546	.set_page = &rs400_gart_set_page,	578	.set_page = &rs400_gart_set_page,
547	},	579	},
548	.ring = {	580	.ring = {
549	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	581	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 597...	Line 629...
597	},	629	},
598	};	630	};
Line 599...	Line 631...
599		631
600	static struct radeon_asic rs600_asic = {	632	static struct radeon_asic rs600_asic = {
601	.init = &rs600_init,	633	.init = &rs600_init,
602	// .fini = &rs600_fini,	634	.fini = &rs600_fini,
603	// .suspend = &rs600_suspend,	635	// .suspend = &rs600_suspend,
604	// .resume = &rs600_resume,	636	// .resume = &rs600_resume,
605	// .vga_set_state = &r100_vga_set_state,	637	// .vga_set_state = &r100_vga_set_state,
606	.asic_reset = &rs600_asic_reset,	638	.asic_reset = &rs600_asic_reset,
607	.mmio_hdp_flush = NULL,	639	.mmio_hdp_flush = NULL,
608	.gui_idle = &r100_gui_idle,	640	.gui_idle = &r100_gui_idle,
-		641	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
609	.mc_wait_for_idle = &rs600_mc_wait_for_idle,	642	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
610	.gart = {	643	.gart = {
-		644	.tlb_flush = &rs600_gart_tlb_flush,
611	.tlb_flush = &rs600_gart_tlb_flush,	645	.get_page_entry = &rs600_gart_get_page_entry,
612	.set_page = &rs600_gart_set_page,	646	.set_page = &rs600_gart_set_page,
613	},	647	},
614	.ring = {	648	.ring = {
615	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	649	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 622...	Line 656...
622	.bandwidth_update = &rs600_bandwidth_update,	656	.bandwidth_update = &rs600_bandwidth_update,
623	.get_vblank_counter = &rs600_get_vblank_counter,	657	.get_vblank_counter = &rs600_get_vblank_counter,
624	.wait_for_vblank = &avivo_wait_for_vblank,	658	.wait_for_vblank = &avivo_wait_for_vblank,
625	.set_backlight_level = &atombios_set_backlight_level,	659	.set_backlight_level = &atombios_set_backlight_level,
626	.get_backlight_level = &atombios_get_backlight_level,	660	.get_backlight_level = &atombios_get_backlight_level,
627	.hdmi_enable = &r600_hdmi_enable,	-
628	.hdmi_setmode = &r600_hdmi_setmode,	-
629	},	661	},
630	.copy = {	662	.copy = {
631	.blit = &r100_copy_blit,	663	.blit = &r100_copy_blit,
632	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	664	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
633	.dma = &r200_copy_dma,	665	.dma = &r200_copy_dma,
Line 665...	Line 697...
665	},	697	},
666	};	698	};
Line 667...	Line 699...
667		699
668	static struct radeon_asic rs690_asic = {	700	static struct radeon_asic rs690_asic = {
669	.init = &rs690_init,	701	.init = &rs690_init,
670	// .fini = &rs690_fini,	702	.fini = &rs690_fini,
671	// .suspend = &rs690_suspend,	703	// .suspend = &rs690_suspend,
672	// .resume = &rs690_resume,	704	// .resume = &rs690_resume,
673	// .vga_set_state = &r100_vga_set_state,	705	// .vga_set_state = &r100_vga_set_state,
674	.asic_reset = &rs600_asic_reset,	706	.asic_reset = &rs600_asic_reset,
675	.mmio_hdp_flush = NULL,	707	.mmio_hdp_flush = NULL,
676	.gui_idle = &r100_gui_idle,	708	.gui_idle = &r100_gui_idle,
-		709	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
677	.mc_wait_for_idle = &rs690_mc_wait_for_idle,	710	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
678	.gart = {	711	.gart = {
-		712	.tlb_flush = &rs400_gart_tlb_flush,
679	.tlb_flush = &rs400_gart_tlb_flush,	713	.get_page_entry = &rs400_gart_get_page_entry,
680	.set_page = &rs400_gart_set_page,	714	.set_page = &rs400_gart_set_page,
681	},	715	},
682	.ring = {	716	.ring = {
683	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	717	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
Line 690...	Line 724...
690	.get_vblank_counter = &rs600_get_vblank_counter,	724	.get_vblank_counter = &rs600_get_vblank_counter,
691	.bandwidth_update = &rs690_bandwidth_update,	725	.bandwidth_update = &rs690_bandwidth_update,
692	.wait_for_vblank = &avivo_wait_for_vblank,	726	.wait_for_vblank = &avivo_wait_for_vblank,
693	.set_backlight_level = &atombios_set_backlight_level,	727	.set_backlight_level = &atombios_set_backlight_level,
694	.get_backlight_level = &atombios_get_backlight_level,	728	.get_backlight_level = &atombios_get_backlight_level,
695	.hdmi_enable = &r600_hdmi_enable,	-
696	.hdmi_setmode = &r600_hdmi_setmode,	-
697	},	729	},
698	.copy = {	730	.copy = {
699	.blit = &r100_copy_blit,	731	.blit = &r100_copy_blit,
700	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	732	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
701	.dma = &r200_copy_dma,	733	.dma = &r200_copy_dma,
Line 733...	Line 765...
733	},	765	},
734	};	766	};
Line 735...	Line 767...
735		767
736	static struct radeon_asic rv515_asic = {	768	static struct radeon_asic rv515_asic = {
737	.init = &rv515_init,	769	.init = &rv515_init,
738	// .fini = &rv515_fini,	770	.fini = &rv515_fini,
739	// .suspend = &rv515_suspend,	771	// .suspend = &rv515_suspend,
740	// .resume = &rv515_resume,	772	// .resume = &rv515_resume,
741	// .vga_set_state = &r100_vga_set_state,	773	// .vga_set_state = &r100_vga_set_state,
742	.asic_reset = &rs600_asic_reset,	774	.asic_reset = &rs600_asic_reset,
743	.mmio_hdp_flush = NULL,	775	.mmio_hdp_flush = NULL,
744	.gui_idle = &r100_gui_idle,	776	.gui_idle = &r100_gui_idle,
-		777	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
745	.mc_wait_for_idle = &rv515_mc_wait_for_idle,	778	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
746	.gart = {	779	.gart = {
-		780	.tlb_flush = &rv370_pcie_gart_tlb_flush,
747	.tlb_flush = &rv370_pcie_gart_tlb_flush,	781	.get_page_entry = &rv370_pcie_gart_get_page_entry,
748	.set_page = &rv370_pcie_gart_set_page,	782	.set_page = &rv370_pcie_gart_set_page,
749	},	783	},
750	.ring = {	784	.ring = {
751	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	785	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
752	},	786	},
753	.irq = {	787	.irq = {
754	.set = &rs600_irq_set,	788	.set = &rs600_irq_set,
755	.process = &rs600_irq_process,	789	.process = &rs600_irq_process,
Line 799...	Line 833...
799	},	833	},
800	};	834	};
Line 801...	Line 835...
801		835
802	static struct radeon_asic r520_asic = {	836	static struct radeon_asic r520_asic = {
803	.init = &r520_init,	837	.init = &r520_init,
804	// .fini = &rv515_fini,	838	.fini = &rv515_fini,
805	// .suspend = &rv515_suspend,	839	// .suspend = &rv515_suspend,
806	// .resume = &r520_resume,	840	// .resume = &r520_resume,
807	// .vga_set_state = &r100_vga_set_state,	841	// .vga_set_state = &r100_vga_set_state,
808	.asic_reset = &rs600_asic_reset,	842	.asic_reset = &rs600_asic_reset,
809	.mmio_hdp_flush = NULL,	843	.mmio_hdp_flush = NULL,
810	.gui_idle = &r100_gui_idle,	844	.gui_idle = &r100_gui_idle,
-		845	.mc_wait_for_idle = &r520_mc_wait_for_idle,
811	.mc_wait_for_idle = &r520_mc_wait_for_idle,	846	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
812	.gart = {	847	.gart = {
-		848	.tlb_flush = &rv370_pcie_gart_tlb_flush,
813	.tlb_flush = &rv370_pcie_gart_tlb_flush,	849	.get_page_entry = &rv370_pcie_gart_get_page_entry,
814	.set_page = &rv370_pcie_gart_set_page,	850	.set_page = &rv370_pcie_gart_set_page,
815	},	851	},
816	.ring = {	852	.ring = {
817	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring	853	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
818	},	854	},
819	.irq = {	855	.irq = {
820	.set = &rs600_irq_set,	856	.set = &rs600_irq_set,
821	.process = &rs600_irq_process,	857	.process = &rs600_irq_process,
Line 891...	Line 927...
891	.set_wptr = &r600_dma_set_wptr,	927	.set_wptr = &r600_dma_set_wptr,
892	};	928	};
Line 893...	Line 929...
893		929
894	static struct radeon_asic r600_asic = {	930	static struct radeon_asic r600_asic = {
895	.init = &r600_init,	931	.init = &r600_init,
896	// .fini = &r600_fini,	932	.fini = &r600_fini,
897	// .suspend = &r600_suspend,	933	// .suspend = &r600_suspend,
898	// .resume = &r600_resume,	934	// .resume = &r600_resume,
899	// .vga_set_state = &r600_vga_set_state,	935	// .vga_set_state = &r600_vga_set_state,
900	.asic_reset = &r600_asic_reset,	936	.asic_reset = &r600_asic_reset,
901	.mmio_hdp_flush = r600_mmio_hdp_flush,	937	.mmio_hdp_flush = r600_mmio_hdp_flush,
902	.gui_idle = &r600_gui_idle,	938	.gui_idle = &r600_gui_idle,
903	.mc_wait_for_idle = &r600_mc_wait_for_idle,	939	.mc_wait_for_idle = &r600_mc_wait_for_idle,
904	.get_xclk = &r600_get_xclk,	940	.get_xclk = &r600_get_xclk,
-		941	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
905	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	942	.get_allowed_info_register = r600_get_allowed_info_register,
906	.gart = {	943	.gart = {
-		944	.tlb_flush = &r600_pcie_gart_tlb_flush,
907	.tlb_flush = &r600_pcie_gart_tlb_flush,	945	.get_page_entry = &rs600_gart_get_page_entry,
908	.set_page = &rs600_gart_set_page,	946	.set_page = &rs600_gart_set_page,
909	},	947	},
910	.ring = {	948	.ring = {
911	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	949	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
Line 919...	Line 957...
919	.bandwidth_update = &rv515_bandwidth_update,	957	.bandwidth_update = &rv515_bandwidth_update,
920	.get_vblank_counter = &rs600_get_vblank_counter,	958	.get_vblank_counter = &rs600_get_vblank_counter,
921	.wait_for_vblank = &avivo_wait_for_vblank,	959	.wait_for_vblank = &avivo_wait_for_vblank,
922	.set_backlight_level = &atombios_set_backlight_level,	960	.set_backlight_level = &atombios_set_backlight_level,
923	.get_backlight_level = &atombios_get_backlight_level,	961	.get_backlight_level = &atombios_get_backlight_level,
924	.hdmi_enable = &r600_hdmi_enable,	-
925	.hdmi_setmode = &r600_hdmi_setmode,	-
926	},	962	},
927	.copy = {	963	.copy = {
928	.blit = &r600_copy_cpdma,	964	.blit = &r600_copy_cpdma,
929	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	965	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
930	.dma = &r600_copy_dma,	966	.dma = &r600_copy_dma,
Line 961...	Line 997...
961	// .pre_page_flip = &rs600_pre_page_flip,	997	// .pre_page_flip = &rs600_pre_page_flip,
962	// .page_flip = &rs600_page_flip,	998	// .page_flip = &rs600_page_flip,
963	},	999	},
964	};	1000	};
Line -...	Line 1001...
-		1001
-		1002	static struct radeon_asic_ring rv6xx_uvd_ring = {
-		1003	.ib_execute = &uvd_v1_0_ib_execute,
-		1004	.emit_fence = &uvd_v1_0_fence_emit,
-		1005	.emit_semaphore = &uvd_v1_0_semaphore_emit,
-		1006	.cs_parse = &radeon_uvd_cs_parse,
-		1007	.ring_test = &uvd_v1_0_ring_test,
-		1008	.ib_test = &uvd_v1_0_ib_test,
-		1009	.is_lockup = &radeon_ring_test_lockup,
-		1010	.get_rptr = &uvd_v1_0_get_rptr,
-		1011	.get_wptr = &uvd_v1_0_get_wptr,
-		1012	.set_wptr = &uvd_v1_0_set_wptr,
-		1013	};
965		1014
966	static struct radeon_asic rv6xx_asic = {	1015	static struct radeon_asic rv6xx_asic = {
967	.init = &r600_init,	1016	.init = &r600_init,
968	// .fini = &r600_fini,	1017	.fini = &r600_fini,
969	// .suspend = &r600_suspend,	1018	// .suspend = &r600_suspend,
970	// .resume = &r600_resume,	1019	// .resume = &r600_resume,
971	// .vga_set_state = &r600_vga_set_state,	1020	// .vga_set_state = &r600_vga_set_state,
972	.asic_reset = &r600_asic_reset,	1021	.asic_reset = &r600_asic_reset,
973	.mmio_hdp_flush = r600_mmio_hdp_flush,	1022	.mmio_hdp_flush = r600_mmio_hdp_flush,
974	.gui_idle = &r600_gui_idle,	1023	.gui_idle = &r600_gui_idle,
975	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1024	.mc_wait_for_idle = &r600_mc_wait_for_idle,
976	.get_xclk = &r600_get_xclk,	1025	.get_xclk = &r600_get_xclk,
-		1026	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
977	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1027	.get_allowed_info_register = r600_get_allowed_info_register,
978	.gart = {	1028	.gart = {
-		1029	.tlb_flush = &r600_pcie_gart_tlb_flush,
979	.tlb_flush = &r600_pcie_gart_tlb_flush,	1030	.get_page_entry = &rs600_gart_get_page_entry,
980	.set_page = &rs600_gart_set_page,	1031	.set_page = &rs600_gart_set_page,
981	},	1032	},
982	.ring = {	1033	.ring = {
983	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1034	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
-		1035	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
984	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1036	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
985	},	1037	},
986	.irq = {	1038	.irq = {
987	.set = &r600_irq_set,	1039	.set = &r600_irq_set,
988	.process = &r600_irq_process,	1040	.process = &r600_irq_process,
Line 991...	Line 1043...
991	.bandwidth_update = &rv515_bandwidth_update,	1043	.bandwidth_update = &rv515_bandwidth_update,
992	.get_vblank_counter = &rs600_get_vblank_counter,	1044	.get_vblank_counter = &rs600_get_vblank_counter,
993	.wait_for_vblank = &avivo_wait_for_vblank,	1045	.wait_for_vblank = &avivo_wait_for_vblank,
994	.set_backlight_level = &atombios_set_backlight_level,	1046	.set_backlight_level = &atombios_set_backlight_level,
995	.get_backlight_level = &atombios_get_backlight_level,	1047	.get_backlight_level = &atombios_get_backlight_level,
996	.hdmi_enable = &r600_hdmi_enable,	-
997	.hdmi_setmode = &r600_hdmi_setmode,	-
998	},	1048	},
999	.copy = {	1049	.copy = {
1000	.blit = &r600_copy_cpdma,	1050	.blit = &r600_copy_cpdma,
1001	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1051	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1002	.dma = &r600_copy_dma,	1052	.dma = &r600_copy_dma,
Line 1044...	Line 1094...
1044	.get_sclk = &rv6xx_dpm_get_sclk,	1094	.get_sclk = &rv6xx_dpm_get_sclk,
1045	.get_mclk = &rv6xx_dpm_get_mclk,	1095	.get_mclk = &rv6xx_dpm_get_mclk,
1046	.print_power_state = &rv6xx_dpm_print_power_state,	1096	.print_power_state = &rv6xx_dpm_print_power_state,
1047	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,	1097	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1048	.force_performance_level = &rv6xx_dpm_force_performance_level,	1098	.force_performance_level = &rv6xx_dpm_force_performance_level,
-		1099	.get_current_sclk = &rv6xx_dpm_get_current_sclk,
-		1100	.get_current_mclk = &rv6xx_dpm_get_current_mclk,
1049	},	1101	},
1050	.pflip = {	1102	.pflip = {
1051	// .pre_page_flip = &rs600_pre_page_flip,	1103	// .pre_page_flip = &rs600_pre_page_flip,
1052	// .page_flip = &rs600_page_flip,	1104	// .page_flip = &rs600_page_flip,
1053	},	1105	},
1054	};	1106	};
Line 1055...	Line 1107...
1055		1107
1056	static struct radeon_asic rs780_asic = {	1108	static struct radeon_asic rs780_asic = {
1057	.init = &r600_init,	1109	.init = &r600_init,
1058	// .fini = &r600_fini,	1110	.fini = &r600_fini,
1059	// .suspend = &r600_suspend,	1111	// .suspend = &r600_suspend,
1060	// .resume = &r600_resume,	1112	// .resume = &r600_resume,
1061	// .vga_set_state = &r600_vga_set_state,	1113	// .vga_set_state = &r600_vga_set_state,
1062	.asic_reset = &r600_asic_reset,	1114	.asic_reset = &r600_asic_reset,
1063	.mmio_hdp_flush = r600_mmio_hdp_flush,	1115	.mmio_hdp_flush = r600_mmio_hdp_flush,
1064	.gui_idle = &r600_gui_idle,	1116	.gui_idle = &r600_gui_idle,
1065	.mc_wait_for_idle = &r600_mc_wait_for_idle,	1117	.mc_wait_for_idle = &r600_mc_wait_for_idle,
1066	.get_xclk = &r600_get_xclk,	1118	.get_xclk = &r600_get_xclk,
-		1119	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1067	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,	1120	.get_allowed_info_register = r600_get_allowed_info_register,
1068	.gart = {	1121	.gart = {
-		1122	.tlb_flush = &r600_pcie_gart_tlb_flush,
1069	.tlb_flush = &r600_pcie_gart_tlb_flush,	1123	.get_page_entry = &rs600_gart_get_page_entry,
1070	.set_page = &rs600_gart_set_page,	1124	.set_page = &rs600_gart_set_page,
1071	},	1125	},
1072	.ring = {	1126	.ring = {
1073	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,	1127	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
-		1128	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1074	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,	1129	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1075	},	1130	},
1076	.irq = {	1131	.irq = {
1077	.set = &r600_irq_set,	1132	.set = &r600_irq_set,
1078	.process = &r600_irq_process,	1133	.process = &r600_irq_process,
Line 1081...	Line 1136...
1081	.bandwidth_update = &rs690_bandwidth_update,	1136	.bandwidth_update = &rs690_bandwidth_update,
1082	.get_vblank_counter = &rs600_get_vblank_counter,	1137	.get_vblank_counter = &rs600_get_vblank_counter,
1083	.wait_for_vblank = &avivo_wait_for_vblank,	1138	.wait_for_vblank = &avivo_wait_for_vblank,
1084	.set_backlight_level = &atombios_set_backlight_level,	1139	.set_backlight_level = &atombios_set_backlight_level,
1085	.get_backlight_level = &atombios_get_backlight_level,	1140	.get_backlight_level = &atombios_get_backlight_level,
1086	.hdmi_enable = &r600_hdmi_enable,	-
1087	.hdmi_setmode = &r600_hdmi_setmode,	-
1088	},	1141	},
1089	.copy = {	1142	.copy = {
1090	.blit = &r600_copy_cpdma,	1143	.blit = &r600_copy_cpdma,
1091	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,	1144	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1092	.dma = &r600_copy_dma,	1145	.dma = &r600_copy_dma,
Line 1134...	Line 1187...
1134	.get_sclk = &rs780_dpm_get_sclk,	1187	.get_sclk = &rs780_dpm_get_sclk,
1135	.get_mclk = &rs780_dpm_get_mclk,	1188	.get_mclk = &rs780_dpm_get_mclk,
1136	.print_power_state = &rs780_dpm_print_power_state,	1189	.print_power_state = &rs780_dpm_print_power_state,
1137	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,	1190	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1138	.force_performance_level = &rs780_dpm_force_performance_level,	1191	.force_performance_level = &rs780_dpm_force_performance_level,
-		1192	.get_current_sclk = &rs780_dpm_get_current_sclk,
-		1193	.get_current_mclk = &rs780_dpm_get_current_mclk,
1139	},	1194	},
1140	.pflip = {	1195	.pflip = {
1141	// .pre_page_flip = &rs600_pre_page_flip,	1196	// .pre_page_flip = &rs600_pre_page_flip,
1142	// .page_flip = &rs600_page_flip,	1197	// .page_flip = &rs600_page_flip,
1143	},	1198	},
1144	};	1199	};
Line 1145...	Line 1200...
1145		1200
1146	static struct radeon_asic_ring rv770_uvd_ring = {	1201	static struct radeon_asic_ring rv770_uvd_ring = {
1147	.ib_execute = &uvd_v1_0_ib_execute,	1202	.ib_execute = &uvd_v1_0_ib_execute,
1148	.emit_fence = &uvd_v2_2_fence_emit,	1203	.emit_fence = &uvd_v2_2_fence_emit,
1149	.emit_semaphore = &uvd_v1_0_semaphore_emit,	1204	.emit_semaphore = &uvd_v2_2_semaphore_emit,
1150	.cs_parse = &radeon_uvd_cs_parse,	1205	.cs_parse = &radeon_uvd_cs_parse,
1151	.ring_test = &uvd_v1_0_ring_test,	1206	.ring_test = &uvd_v1_0_ring_test,
1152	.ib_test = &uvd_v1_0_ib_test,	1207	.ib_test = &uvd_v1_0_ib_test,
1153	.is_lockup = &radeon_ring_test_lockup,	1208	.is_lockup = &radeon_ring_test_lockup,

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 5271 → 6104