Rev 3120 | Rev 3764 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 3120 | Rev 3192 | ||
|---|---|---|---|
| Line 169... | Line 169... | ||
| 169 | // .fini = &r100_fini, |
169 | // .fini = &r100_fini, |
| 170 | // .suspend = &r100_suspend, |
170 | // .suspend = &r100_suspend, |
| 171 | // .resume = &r100_resume, |
171 | // .resume = &r100_resume, |
| 172 | // .vga_set_state = &r100_vga_set_state, |
172 | // .vga_set_state = &r100_vga_set_state, |
| 173 | .asic_reset = &r100_asic_reset, |
173 | .asic_reset = &r100_asic_reset, |
| 174 | // .ioctl_wait_idle = NULL, |
174 | .ioctl_wait_idle = NULL, |
| 175 | .gui_idle = &r100_gui_idle, |
175 | .gui_idle = &r100_gui_idle, |
| 176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
| 177 | .gart = { |
177 | .gart = { |
| 178 | .tlb_flush = &r100_pci_gart_tlb_flush, |
178 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 179 | .set_page = &r100_pci_gart_set_page, |
179 | .set_page = &r100_pci_gart_set_page, |
| Line 226... | Line 226... | ||
| 226 | // .init_profile = &r100_pm_init_profile, |
226 | // .init_profile = &r100_pm_init_profile, |
| 227 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
227 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
| 228 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
228 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 229 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
229 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 230 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
230 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 231 | // .set_memory_clock = NULL, |
231 | .set_memory_clock = NULL, |
| 232 | // .get_pcie_lanes = NULL, |
232 | .get_pcie_lanes = NULL, |
| 233 | // .set_pcie_lanes = NULL, |
233 | .set_pcie_lanes = NULL, |
| 234 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
234 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 235 | }, |
235 | }, |
| 236 | .pflip = { |
236 | .pflip = { |
| 237 | // .pre_page_flip = &r100_pre_page_flip, |
237 | // .pre_page_flip = &r100_pre_page_flip, |
| 238 | // .page_flip = &r100_page_flip, |
238 | // .page_flip = &r100_page_flip, |
| Line 245... | Line 245... | ||
| 245 | // .fini = &r100_fini, |
245 | // .fini = &r100_fini, |
| 246 | // .suspend = &r100_suspend, |
246 | // .suspend = &r100_suspend, |
| 247 | // .resume = &r100_resume, |
247 | // .resume = &r100_resume, |
| 248 | // .vga_set_state = &r100_vga_set_state, |
248 | // .vga_set_state = &r100_vga_set_state, |
| 249 | .asic_reset = &r100_asic_reset, |
249 | .asic_reset = &r100_asic_reset, |
| 250 | // .ioctl_wait_idle = NULL, |
250 | .ioctl_wait_idle = NULL, |
| 251 | .gui_idle = &r100_gui_idle, |
251 | .gui_idle = &r100_gui_idle, |
| 252 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
252 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
| 253 | .gart = { |
253 | .gart = { |
| 254 | .tlb_flush = &r100_pci_gart_tlb_flush, |
254 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 255 | .set_page = &r100_pci_gart_set_page, |
255 | .set_page = &r100_pci_gart_set_page, |
| Line 302... | Line 302... | ||
| 302 | // .init_profile = &r100_pm_init_profile, |
302 | // .init_profile = &r100_pm_init_profile, |
| 303 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
303 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
| 304 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
304 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 305 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
305 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 306 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
306 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 307 | // .set_memory_clock = NULL, |
307 | .set_memory_clock = NULL, |
| 308 | // .get_pcie_lanes = NULL, |
308 | .get_pcie_lanes = NULL, |
| 309 | // .set_pcie_lanes = NULL, |
309 | .set_pcie_lanes = NULL, |
| 310 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
310 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
| 311 | }, |
311 | }, |
| 312 | .pflip = { |
312 | .pflip = { |
| 313 | // .pre_page_flip = &r100_pre_page_flip, |
313 | // .pre_page_flip = &r100_pre_page_flip, |
| 314 | // .page_flip = &r100_page_flip, |
314 | // .page_flip = &r100_page_flip, |
| Line 321... | Line 321... | ||
| 321 | // .fini = &r300_fini, |
321 | // .fini = &r300_fini, |
| 322 | // .suspend = &r300_suspend, |
322 | // .suspend = &r300_suspend, |
| 323 | // .resume = &r300_resume, |
323 | // .resume = &r300_resume, |
| 324 | // .vga_set_state = &r100_vga_set_state, |
324 | // .vga_set_state = &r100_vga_set_state, |
| 325 | .asic_reset = &r300_asic_reset, |
325 | .asic_reset = &r300_asic_reset, |
| 326 | // .ioctl_wait_idle = NULL, |
326 | .ioctl_wait_idle = NULL, |
| 327 | .gui_idle = &r100_gui_idle, |
327 | .gui_idle = &r100_gui_idle, |
| 328 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
328 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 329 | .gart = { |
329 | .gart = { |
| 330 | .tlb_flush = &r100_pci_gart_tlb_flush, |
330 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 331 | .set_page = &r100_pci_gart_set_page, |
331 | .set_page = &r100_pci_gart_set_page, |
| Line 397... | Line 397... | ||
| 397 | // .fini = &r300_fini, |
397 | // .fini = &r300_fini, |
| 398 | // .suspend = &r300_suspend, |
398 | // .suspend = &r300_suspend, |
| 399 | // .resume = &r300_resume, |
399 | // .resume = &r300_resume, |
| 400 | // .vga_set_state = &r100_vga_set_state, |
400 | // .vga_set_state = &r100_vga_set_state, |
| 401 | .asic_reset = &r300_asic_reset, |
401 | .asic_reset = &r300_asic_reset, |
| 402 | // .ioctl_wait_idle = NULL, |
402 | .ioctl_wait_idle = NULL, |
| 403 | .gui_idle = &r100_gui_idle, |
403 | .gui_idle = &r100_gui_idle, |
| 404 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
404 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 405 | .gart = { |
405 | .gart = { |
| 406 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
406 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 407 | .set_page = &rv370_pcie_gart_set_page, |
407 | .set_page = &rv370_pcie_gart_set_page, |
| Line 473... | Line 473... | ||
| 473 | // .fini = &r420_fini, |
473 | // .fini = &r420_fini, |
| 474 | // .suspend = &r420_suspend, |
474 | // .suspend = &r420_suspend, |
| 475 | // .resume = &r420_resume, |
475 | // .resume = &r420_resume, |
| 476 | // .vga_set_state = &r100_vga_set_state, |
476 | // .vga_set_state = &r100_vga_set_state, |
| 477 | .asic_reset = &r300_asic_reset, |
477 | .asic_reset = &r300_asic_reset, |
| 478 | // .ioctl_wait_idle = NULL, |
478 | .ioctl_wait_idle = NULL, |
| 479 | .gui_idle = &r100_gui_idle, |
479 | .gui_idle = &r100_gui_idle, |
| 480 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
480 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
| 481 | .gart = { |
481 | .gart = { |
| 482 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
482 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 483 | .set_page = &rv370_pcie_gart_set_page, |
483 | .set_page = &rv370_pcie_gart_set_page, |
| Line 549... | Line 549... | ||
| 549 | // .fini = &rs400_fini, |
549 | // .fini = &rs400_fini, |
| 550 | // .suspend = &rs400_suspend, |
550 | // .suspend = &rs400_suspend, |
| 551 | // .resume = &rs400_resume, |
551 | // .resume = &rs400_resume, |
| 552 | // .vga_set_state = &r100_vga_set_state, |
552 | // .vga_set_state = &r100_vga_set_state, |
| 553 | .asic_reset = &r300_asic_reset, |
553 | .asic_reset = &r300_asic_reset, |
| 554 | // .ioctl_wait_idle = NULL, |
554 | .ioctl_wait_idle = NULL, |
| 555 | .gui_idle = &r100_gui_idle, |
555 | .gui_idle = &r100_gui_idle, |
| 556 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
556 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
| 557 | .gart = { |
557 | .gart = { |
| 558 | .tlb_flush = &rs400_gart_tlb_flush, |
558 | .tlb_flush = &rs400_gart_tlb_flush, |
| 559 | .set_page = &rs400_gart_set_page, |
559 | .set_page = &rs400_gart_set_page, |
| Line 625... | Line 625... | ||
| 625 | // .fini = &rs600_fini, |
625 | // .fini = &rs600_fini, |
| 626 | // .suspend = &rs600_suspend, |
626 | // .suspend = &rs600_suspend, |
| 627 | // .resume = &rs600_resume, |
627 | // .resume = &rs600_resume, |
| 628 | // .vga_set_state = &r100_vga_set_state, |
628 | // .vga_set_state = &r100_vga_set_state, |
| 629 | .asic_reset = &rs600_asic_reset, |
629 | .asic_reset = &rs600_asic_reset, |
| 630 | // .ioctl_wait_idle = NULL, |
630 | .ioctl_wait_idle = NULL, |
| 631 | .gui_idle = &r100_gui_idle, |
631 | .gui_idle = &r100_gui_idle, |
| 632 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
632 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
| 633 | .gart = { |
633 | .gart = { |
| 634 | .tlb_flush = &rs600_gart_tlb_flush, |
634 | .tlb_flush = &rs600_gart_tlb_flush, |
| 635 | .set_page = &rs600_gart_set_page, |
635 | .set_page = &rs600_gart_set_page, |
| Line 701... | Line 701... | ||
| 701 | // .fini = &rs690_fini, |
701 | // .fini = &rs690_fini, |
| 702 | // .suspend = &rs690_suspend, |
702 | // .suspend = &rs690_suspend, |
| 703 | // .resume = &rs690_resume, |
703 | // .resume = &rs690_resume, |
| 704 | // .vga_set_state = &r100_vga_set_state, |
704 | // .vga_set_state = &r100_vga_set_state, |
| 705 | .asic_reset = &rs600_asic_reset, |
705 | .asic_reset = &rs600_asic_reset, |
| 706 | // .ioctl_wait_idle = NULL, |
706 | .ioctl_wait_idle = NULL, |
| 707 | .gui_idle = &r100_gui_idle, |
707 | .gui_idle = &r100_gui_idle, |
| 708 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
708 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
| 709 | .gart = { |
709 | .gart = { |
| 710 | .tlb_flush = &rs400_gart_tlb_flush, |
710 | .tlb_flush = &rs400_gart_tlb_flush, |
| 711 | .set_page = &rs400_gart_set_page, |
711 | .set_page = &rs400_gart_set_page, |
| Line 777... | Line 777... | ||
| 777 | // .fini = &rv515_fini, |
777 | // .fini = &rv515_fini, |
| 778 | // .suspend = &rv515_suspend, |
778 | // .suspend = &rv515_suspend, |
| 779 | // .resume = &rv515_resume, |
779 | // .resume = &rv515_resume, |
| 780 | // .vga_set_state = &r100_vga_set_state, |
780 | // .vga_set_state = &r100_vga_set_state, |
| 781 | .asic_reset = &rs600_asic_reset, |
781 | .asic_reset = &rs600_asic_reset, |
| 782 | // .ioctl_wait_idle = NULL, |
782 | .ioctl_wait_idle = NULL, |
| 783 | .gui_idle = &r100_gui_idle, |
783 | .gui_idle = &r100_gui_idle, |
| 784 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
784 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
| 785 | .gart = { |
785 | .gart = { |
| 786 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
786 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 787 | .set_page = &rv370_pcie_gart_set_page, |
787 | .set_page = &rv370_pcie_gart_set_page, |
| Line 853... | Line 853... | ||
| 853 | // .fini = &rv515_fini, |
853 | // .fini = &rv515_fini, |
| 854 | // .suspend = &rv515_suspend, |
854 | // .suspend = &rv515_suspend, |
| 855 | // .resume = &r520_resume, |
855 | // .resume = &r520_resume, |
| 856 | // .vga_set_state = &r100_vga_set_state, |
856 | // .vga_set_state = &r100_vga_set_state, |
| 857 | .asic_reset = &rs600_asic_reset, |
857 | .asic_reset = &rs600_asic_reset, |
| 858 | // .ioctl_wait_idle = NULL, |
858 | .ioctl_wait_idle = NULL, |
| 859 | .gui_idle = &r100_gui_idle, |
859 | .gui_idle = &r100_gui_idle, |
| 860 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
860 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
| 861 | .gart = { |
861 | .gart = { |
| 862 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
862 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 863 | .set_page = &rv370_pcie_gart_set_page, |
863 | .set_page = &rv370_pcie_gart_set_page, |
| Line 945... | Line 945... | ||
| 945 | .emit_semaphore = &r600_semaphore_ring_emit, |
945 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 946 | // .cs_parse = &r600_cs_parse, |
946 | // .cs_parse = &r600_cs_parse, |
| 947 | .ring_test = &r600_ring_test, |
947 | .ring_test = &r600_ring_test, |
| 948 | .ib_test = &r600_ib_test, |
948 | .ib_test = &r600_ib_test, |
| 949 | .is_lockup = &r600_gpu_is_lockup, |
949 | .is_lockup = &r600_gpu_is_lockup, |
| - | 950 | }, |
|
| - | 951 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 952 | .ib_execute = &r600_dma_ring_ib_execute, |
|
| - | 953 | .emit_fence = &r600_dma_fence_ring_emit, |
|
| - | 954 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 955 | // .cs_parse = &r600_dma_cs_parse, |
|
| - | 956 | .ring_test = &r600_dma_ring_test, |
|
| - | 957 | .ib_test = &r600_dma_ib_test, |
|
| - | 958 | .is_lockup = &r600_dma_is_lockup, |
|
| 950 | } |
959 | } |
| 951 | }, |
960 | }, |
| 952 | .irq = { |
961 | .irq = { |
| 953 | .set = &r600_irq_set, |
962 | .set = &r600_irq_set, |
| 954 | .process = &r600_irq_process, |
963 | .process = &r600_irq_process, |
| Line 961... | Line 970... | ||
| 961 | // .get_backlight_level = &atombios_get_backlight_level, |
970 | // .get_backlight_level = &atombios_get_backlight_level, |
| 962 | }, |
971 | }, |
| 963 | .copy = { |
972 | .copy = { |
| 964 | .blit = &r600_copy_blit, |
973 | .blit = &r600_copy_blit, |
| 965 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
974 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 966 | .dma = NULL, |
975 | .dma = &r600_copy_dma, |
| 967 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
976 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 968 | .copy = &r600_copy_blit, |
977 | .copy = &r600_copy_dma, |
| 969 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
978 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 970 | }, |
979 | }, |
| 971 | .surface = { |
980 | .surface = { |
| 972 | .set_reg = r600_set_surface_reg, |
981 | .set_reg = r600_set_surface_reg, |
| 973 | .clear_reg = r600_clear_surface_reg, |
982 | .clear_reg = r600_clear_surface_reg, |
| 974 | }, |
983 | }, |
| Line 1020... | Line 1029... | ||
| 1020 | .emit_semaphore = &r600_semaphore_ring_emit, |
1029 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1021 | // .cs_parse = &r600_cs_parse, |
1030 | // .cs_parse = &r600_cs_parse, |
| 1022 | .ring_test = &r600_ring_test, |
1031 | .ring_test = &r600_ring_test, |
| 1023 | .ib_test = &r600_ib_test, |
1032 | .ib_test = &r600_ib_test, |
| 1024 | .is_lockup = &r600_gpu_is_lockup, |
1033 | .is_lockup = &r600_gpu_is_lockup, |
| - | 1034 | }, |
|
| - | 1035 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1036 | .ib_execute = &r600_dma_ring_ib_execute, |
|
| - | 1037 | .emit_fence = &r600_dma_fence_ring_emit, |
|
| - | 1038 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1039 | // .cs_parse = &r600_dma_cs_parse, |
|
| - | 1040 | .ring_test = &r600_dma_ring_test, |
|
| - | 1041 | .ib_test = &r600_dma_ib_test, |
|
| - | 1042 | .is_lockup = &r600_dma_is_lockup, |
|
| 1025 | } |
1043 | } |
| 1026 | }, |
1044 | }, |
| 1027 | .irq = { |
1045 | .irq = { |
| 1028 | .set = &r600_irq_set, |
1046 | .set = &r600_irq_set, |
| 1029 | .process = &r600_irq_process, |
1047 | .process = &r600_irq_process, |
| Line 1036... | Line 1054... | ||
| 1036 | // .get_backlight_level = &atombios_get_backlight_level, |
1054 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1037 | }, |
1055 | }, |
| 1038 | .copy = { |
1056 | .copy = { |
| 1039 | .blit = &r600_copy_blit, |
1057 | .blit = &r600_copy_blit, |
| 1040 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1058 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1041 | .dma = NULL, |
1059 | .dma = &r600_copy_dma, |
| 1042 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1060 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1043 | .copy = &r600_copy_blit, |
1061 | .copy = &r600_copy_dma, |
| 1044 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1062 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1045 | }, |
1063 | }, |
| 1046 | .surface = { |
1064 | .surface = { |
| 1047 | .set_reg = r600_set_surface_reg, |
1065 | .set_reg = r600_set_surface_reg, |
| 1048 | .clear_reg = r600_clear_surface_reg, |
1066 | .clear_reg = r600_clear_surface_reg, |
| 1049 | }, |
1067 | }, |
| Line 1095... | Line 1113... | ||
| 1095 | .emit_semaphore = &r600_semaphore_ring_emit, |
1113 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1096 | // .cs_parse = &r600_cs_parse, |
1114 | // .cs_parse = &r600_cs_parse, |
| 1097 | .ring_test = &r600_ring_test, |
1115 | .ring_test = &r600_ring_test, |
| 1098 | .ib_test = &r600_ib_test, |
1116 | .ib_test = &r600_ib_test, |
| 1099 | .is_lockup = &r600_gpu_is_lockup, |
1117 | .is_lockup = &r600_gpu_is_lockup, |
| - | 1118 | }, |
|
| - | 1119 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1120 | .ib_execute = &r600_dma_ring_ib_execute, |
|
| - | 1121 | .emit_fence = &r600_dma_fence_ring_emit, |
|
| - | 1122 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1123 | // .cs_parse = &r600_dma_cs_parse, |
|
| - | 1124 | .ring_test = &r600_dma_ring_test, |
|
| - | 1125 | .ib_test = &r600_dma_ib_test, |
|
| - | 1126 | .is_lockup = &r600_dma_is_lockup, |
|
| 1100 | } |
1127 | } |
| 1101 | }, |
1128 | }, |
| 1102 | .irq = { |
1129 | .irq = { |
| 1103 | .set = &r600_irq_set, |
1130 | .set = &r600_irq_set, |
| 1104 | .process = &r600_irq_process, |
1131 | .process = &r600_irq_process, |
| Line 1111... | Line 1138... | ||
| 1111 | // .get_backlight_level = &atombios_get_backlight_level, |
1138 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1112 | }, |
1139 | }, |
| 1113 | .copy = { |
1140 | .copy = { |
| 1114 | .blit = &r600_copy_blit, |
1141 | .blit = &r600_copy_blit, |
| 1115 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1142 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1116 | .dma = NULL, |
1143 | .dma = &r600_copy_dma, |
| 1117 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1144 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1118 | .copy = &r600_copy_blit, |
1145 | .copy = &r600_copy_dma, |
| 1119 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1146 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1120 | }, |
1147 | }, |
| 1121 | .surface = { |
1148 | .surface = { |
| 1122 | .set_reg = r600_set_surface_reg, |
1149 | .set_reg = r600_set_surface_reg, |
| 1123 | .clear_reg = r600_clear_surface_reg, |
1150 | .clear_reg = r600_clear_surface_reg, |
| 1124 | }, |
1151 | }, |
| Line 1170... | Line 1197... | ||
| 1170 | .emit_semaphore = &r600_semaphore_ring_emit, |
1197 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1171 | // .cs_parse = &evergreen_cs_parse, |
1198 | // .cs_parse = &evergreen_cs_parse, |
| 1172 | .ring_test = &r600_ring_test, |
1199 | .ring_test = &r600_ring_test, |
| 1173 | .ib_test = &r600_ib_test, |
1200 | .ib_test = &r600_ib_test, |
| 1174 | .is_lockup = &evergreen_gpu_is_lockup, |
1201 | .is_lockup = &evergreen_gpu_is_lockup, |
| - | 1202 | }, |
|
| - | 1203 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1204 | .ib_execute = &evergreen_dma_ring_ib_execute, |
|
| - | 1205 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1206 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1207 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1208 | .ring_test = &r600_dma_ring_test, |
|
| - | 1209 | .ib_test = &r600_dma_ib_test, |
|
| - | 1210 | .is_lockup = &r600_dma_is_lockup, |
|
| 1175 | } |
1211 | } |
| 1176 | }, |
1212 | }, |
| 1177 | .irq = { |
1213 | .irq = { |
| 1178 | .set = &evergreen_irq_set, |
1214 | .set = &evergreen_irq_set, |
| 1179 | .process = &evergreen_irq_process, |
1215 | .process = &evergreen_irq_process, |
| Line 1186... | Line 1222... | ||
| 1186 | // .get_backlight_level = &atombios_get_backlight_level, |
1222 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1187 | }, |
1223 | }, |
| 1188 | .copy = { |
1224 | .copy = { |
| 1189 | .blit = &r600_copy_blit, |
1225 | .blit = &r600_copy_blit, |
| 1190 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1226 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1191 | .dma = NULL, |
1227 | .dma = &evergreen_copy_dma, |
| 1192 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1228 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1193 | .copy = &r600_copy_blit, |
1229 | .copy = &evergreen_copy_dma, |
| 1194 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1230 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1195 | }, |
1231 | }, |
| 1196 | .surface = { |
1232 | .surface = { |
| 1197 | .set_reg = r600_set_surface_reg, |
1233 | .set_reg = r600_set_surface_reg, |
| 1198 | .clear_reg = r600_clear_surface_reg, |
1234 | .clear_reg = r600_clear_surface_reg, |
| 1199 | }, |
1235 | }, |
| Line 1246... | Line 1282... | ||
| 1246 | // .cs_parse = &evergreen_cs_parse, |
1282 | // .cs_parse = &evergreen_cs_parse, |
| 1247 | .ring_test = &r600_ring_test, |
1283 | .ring_test = &r600_ring_test, |
| 1248 | .ib_test = &r600_ib_test, |
1284 | .ib_test = &r600_ib_test, |
| 1249 | .is_lockup = &evergreen_gpu_is_lockup, |
1285 | .is_lockup = &evergreen_gpu_is_lockup, |
| 1250 | }, |
1286 | }, |
| - | 1287 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1288 | .ib_execute = &evergreen_dma_ring_ib_execute, |
|
| - | 1289 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1290 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1291 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1292 | .ring_test = &r600_dma_ring_test, |
|
| - | 1293 | .ib_test = &r600_dma_ib_test, |
|
| - | 1294 | .is_lockup = &r600_dma_is_lockup, |
|
| - | 1295 | } |
|
| 1251 | }, |
1296 | }, |
| 1252 | .irq = { |
1297 | .irq = { |
| 1253 | .set = &evergreen_irq_set, |
1298 | .set = &evergreen_irq_set, |
| 1254 | .process = &evergreen_irq_process, |
1299 | .process = &evergreen_irq_process, |
| 1255 | }, |
1300 | }, |
| Line 1261... | Line 1306... | ||
| 1261 | // .get_backlight_level = &atombios_get_backlight_level, |
1306 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1262 | }, |
1307 | }, |
| 1263 | .copy = { |
1308 | .copy = { |
| 1264 | .blit = &r600_copy_blit, |
1309 | .blit = &r600_copy_blit, |
| 1265 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1310 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1266 | .dma = NULL, |
1311 | .dma = &evergreen_copy_dma, |
| 1267 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1312 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1268 | .copy = &r600_copy_blit, |
1313 | .copy = &evergreen_copy_dma, |
| 1269 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1314 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1270 | }, |
1315 | }, |
| 1271 | .surface = { |
1316 | .surface = { |
| 1272 | .set_reg = r600_set_surface_reg, |
1317 | .set_reg = r600_set_surface_reg, |
| 1273 | .clear_reg = r600_clear_surface_reg, |
1318 | .clear_reg = r600_clear_surface_reg, |
| 1274 | }, |
1319 | }, |
| Line 1320... | Line 1365... | ||
| 1320 | .emit_semaphore = &r600_semaphore_ring_emit, |
1365 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1321 | // .cs_parse = &evergreen_cs_parse, |
1366 | // .cs_parse = &evergreen_cs_parse, |
| 1322 | .ring_test = &r600_ring_test, |
1367 | .ring_test = &r600_ring_test, |
| 1323 | .ib_test = &r600_ib_test, |
1368 | .ib_test = &r600_ib_test, |
| 1324 | .is_lockup = &evergreen_gpu_is_lockup, |
1369 | .is_lockup = &evergreen_gpu_is_lockup, |
| - | 1370 | }, |
|
| - | 1371 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1372 | .ib_execute = &evergreen_dma_ring_ib_execute, |
|
| - | 1373 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1374 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1375 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1376 | .ring_test = &r600_dma_ring_test, |
|
| - | 1377 | .ib_test = &r600_dma_ib_test, |
|
| - | 1378 | .is_lockup = &r600_dma_is_lockup, |
|
| 1325 | } |
1379 | } |
| 1326 | }, |
1380 | }, |
| 1327 | .irq = { |
1381 | .irq = { |
| 1328 | .set = &evergreen_irq_set, |
1382 | .set = &evergreen_irq_set, |
| 1329 | .process = &evergreen_irq_process, |
1383 | .process = &evergreen_irq_process, |
| Line 1336... | Line 1390... | ||
| 1336 | // .get_backlight_level = &atombios_get_backlight_level, |
1390 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1337 | }, |
1391 | }, |
| 1338 | .copy = { |
1392 | .copy = { |
| 1339 | .blit = &r600_copy_blit, |
1393 | .blit = &r600_copy_blit, |
| 1340 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1394 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1341 | .dma = NULL, |
1395 | .dma = &evergreen_copy_dma, |
| 1342 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1396 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1343 | .copy = &r600_copy_blit, |
1397 | .copy = &evergreen_copy_dma, |
| 1344 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1398 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1345 | }, |
1399 | }, |
| 1346 | .surface = { |
1400 | .surface = { |
| 1347 | .set_reg = r600_set_surface_reg, |
1401 | .set_reg = r600_set_surface_reg, |
| 1348 | .clear_reg = r600_clear_surface_reg, |
1402 | .clear_reg = r600_clear_surface_reg, |
| 1349 | }, |
1403 | }, |
| Line 1389... | Line 1443... | ||
| 1389 | .set_page = &rs600_gart_set_page, |
1443 | .set_page = &rs600_gart_set_page, |
| 1390 | }, |
1444 | }, |
| 1391 | .vm = { |
1445 | .vm = { |
| 1392 | .init = &cayman_vm_init, |
1446 | .init = &cayman_vm_init, |
| 1393 | .fini = &cayman_vm_fini, |
1447 | .fini = &cayman_vm_fini, |
| 1394 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1448 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1395 | .set_page = &cayman_vm_set_page, |
1449 | .set_page = &cayman_vm_set_page, |
| 1396 | }, |
1450 | }, |
| 1397 | .ring = { |
1451 | .ring = { |
| 1398 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1452 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1399 | .ib_execute = &cayman_ring_ib_execute, |
1453 | .ib_execute = &cayman_ring_ib_execute, |
| Line 1425... | Line 1479... | ||
| 1425 | // .cs_parse = &evergreen_cs_parse, |
1479 | // .cs_parse = &evergreen_cs_parse, |
| 1426 | .ring_test = &r600_ring_test, |
1480 | .ring_test = &r600_ring_test, |
| 1427 | .ib_test = &r600_ib_test, |
1481 | .ib_test = &r600_ib_test, |
| 1428 | .is_lockup = &evergreen_gpu_is_lockup, |
1482 | .is_lockup = &evergreen_gpu_is_lockup, |
| 1429 | .vm_flush = &cayman_vm_flush, |
1483 | .vm_flush = &cayman_vm_flush, |
| - | 1484 | }, |
|
| - | 1485 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1486 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1487 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1488 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1489 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1490 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1491 | .ring_test = &r600_dma_ring_test, |
|
| - | 1492 | .ib_test = &r600_dma_ib_test, |
|
| - | 1493 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1494 | .vm_flush = &cayman_dma_vm_flush, |
|
| - | 1495 | }, |
|
| - | 1496 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
|
| - | 1497 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1498 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1499 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1500 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1501 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1502 | .ring_test = &r600_dma_ring_test, |
|
| - | 1503 | .ib_test = &r600_dma_ib_test, |
|
| - | 1504 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1505 | .vm_flush = &cayman_dma_vm_flush, |
|
| 1430 | } |
1506 | } |
| 1431 | }, |
1507 | }, |
| 1432 | .irq = { |
1508 | .irq = { |
| 1433 | .set = &evergreen_irq_set, |
1509 | .set = &evergreen_irq_set, |
| 1434 | .process = &evergreen_irq_process, |
1510 | .process = &evergreen_irq_process, |
| Line 1441... | Line 1517... | ||
| 1441 | // .get_backlight_level = &atombios_get_backlight_level, |
1517 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1442 | }, |
1518 | }, |
| 1443 | .copy = { |
1519 | .copy = { |
| 1444 | .blit = &r600_copy_blit, |
1520 | .blit = &r600_copy_blit, |
| 1445 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1521 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1446 | .dma = NULL, |
1522 | .dma = &evergreen_copy_dma, |
| 1447 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1523 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1448 | .copy = &r600_copy_blit, |
1524 | .copy = &evergreen_copy_dma, |
| 1449 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1525 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1450 | }, |
1526 | }, |
| 1451 | .surface = { |
1527 | .surface = { |
| 1452 | .set_reg = r600_set_surface_reg, |
1528 | .set_reg = r600_set_surface_reg, |
| 1453 | .clear_reg = r600_clear_surface_reg, |
1529 | .clear_reg = r600_clear_surface_reg, |
| 1454 | }, |
1530 | }, |
| Line 1494... | Line 1570... | ||
| 1494 | .set_page = &rs600_gart_set_page, |
1570 | .set_page = &rs600_gart_set_page, |
| 1495 | }, |
1571 | }, |
| 1496 | .vm = { |
1572 | .vm = { |
| 1497 | .init = &cayman_vm_init, |
1573 | .init = &cayman_vm_init, |
| 1498 | .fini = &cayman_vm_fini, |
1574 | .fini = &cayman_vm_fini, |
| 1499 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1575 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1500 | .set_page = &cayman_vm_set_page, |
1576 | .set_page = &cayman_vm_set_page, |
| 1501 | }, |
1577 | }, |
| 1502 | .ring = { |
1578 | .ring = { |
| 1503 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1579 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1504 | .ib_execute = &cayman_ring_ib_execute, |
1580 | .ib_execute = &cayman_ring_ib_execute, |
| Line 1530... | Line 1606... | ||
| 1530 | // .cs_parse = &evergreen_cs_parse, |
1606 | // .cs_parse = &evergreen_cs_parse, |
| 1531 | .ring_test = &r600_ring_test, |
1607 | .ring_test = &r600_ring_test, |
| 1532 | .ib_test = &r600_ib_test, |
1608 | .ib_test = &r600_ib_test, |
| 1533 | .is_lockup = &evergreen_gpu_is_lockup, |
1609 | .is_lockup = &evergreen_gpu_is_lockup, |
| 1534 | .vm_flush = &cayman_vm_flush, |
1610 | .vm_flush = &cayman_vm_flush, |
| - | 1611 | }, |
|
| - | 1612 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1613 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1614 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1615 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1616 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1617 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1618 | .ring_test = &r600_dma_ring_test, |
|
| - | 1619 | .ib_test = &r600_dma_ib_test, |
|
| - | 1620 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1621 | .vm_flush = &cayman_dma_vm_flush, |
|
| - | 1622 | }, |
|
| - | 1623 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
|
| - | 1624 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1625 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1626 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1627 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1628 | // .cs_parse = &evergreen_dma_cs_parse, |
|
| - | 1629 | .ring_test = &r600_dma_ring_test, |
|
| - | 1630 | .ib_test = &r600_dma_ib_test, |
|
| - | 1631 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1632 | .vm_flush = &cayman_dma_vm_flush, |
|
| 1535 | } |
1633 | } |
| 1536 | }, |
1634 | }, |
| 1537 | .irq = { |
1635 | .irq = { |
| 1538 | .set = &evergreen_irq_set, |
1636 | .set = &evergreen_irq_set, |
| 1539 | .process = &evergreen_irq_process, |
1637 | .process = &evergreen_irq_process, |
| Line 1546... | Line 1644... | ||
| 1546 | // .get_backlight_level = &atombios_get_backlight_level, |
1644 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1547 | }, |
1645 | }, |
| 1548 | .copy = { |
1646 | .copy = { |
| 1549 | .blit = &r600_copy_blit, |
1647 | .blit = &r600_copy_blit, |
| 1550 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1648 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1551 | .dma = NULL, |
1649 | .dma = &evergreen_copy_dma, |
| 1552 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1650 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1553 | .copy = &r600_copy_blit, |
1651 | .copy = &evergreen_copy_dma, |
| 1554 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1652 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1555 | }, |
1653 | }, |
| 1556 | .surface = { |
1654 | .surface = { |
| 1557 | .set_reg = r600_set_surface_reg, |
1655 | .set_reg = r600_set_surface_reg, |
| 1558 | .clear_reg = r600_clear_surface_reg, |
1656 | .clear_reg = r600_clear_surface_reg, |
| 1559 | }, |
1657 | }, |
| Line 1599... | Line 1697... | ||
| 1599 | .set_page = &rs600_gart_set_page, |
1697 | .set_page = &rs600_gart_set_page, |
| 1600 | }, |
1698 | }, |
| 1601 | .vm = { |
1699 | .vm = { |
| 1602 | .init = &si_vm_init, |
1700 | .init = &si_vm_init, |
| 1603 | .fini = &si_vm_fini, |
1701 | .fini = &si_vm_fini, |
| 1604 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1702 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1605 | .set_page = &si_vm_set_page, |
1703 | .set_page = &si_vm_set_page, |
| 1606 | }, |
1704 | }, |
| 1607 | .ring = { |
1705 | .ring = { |
| 1608 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1706 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1609 | .ib_execute = &si_ring_ib_execute, |
1707 | .ib_execute = &si_ring_ib_execute, |
| Line 1635... | Line 1733... | ||
| 1635 | .cs_parse = NULL, |
1733 | .cs_parse = NULL, |
| 1636 | .ring_test = &r600_ring_test, |
1734 | .ring_test = &r600_ring_test, |
| 1637 | .ib_test = &r600_ib_test, |
1735 | .ib_test = &r600_ib_test, |
| 1638 | .is_lockup = &si_gpu_is_lockup, |
1736 | .is_lockup = &si_gpu_is_lockup, |
| 1639 | .vm_flush = &si_vm_flush, |
1737 | .vm_flush = &si_vm_flush, |
| - | 1738 | }, |
|
| - | 1739 | [R600_RING_TYPE_DMA_INDEX] = { |
|
| - | 1740 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1741 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1742 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1743 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1744 | .cs_parse = NULL, |
|
| - | 1745 | .ring_test = &r600_dma_ring_test, |
|
| - | 1746 | .ib_test = &r600_dma_ib_test, |
|
| - | 1747 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1748 | .vm_flush = &si_dma_vm_flush, |
|
| - | 1749 | }, |
|
| - | 1750 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
|
| - | 1751 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
| - | 1752 | // .ib_parse = &evergreen_dma_ib_parse, |
|
| - | 1753 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
| - | 1754 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
| - | 1755 | .cs_parse = NULL, |
|
| - | 1756 | .ring_test = &r600_dma_ring_test, |
|
| - | 1757 | .ib_test = &r600_dma_ib_test, |
|
| - | 1758 | .is_lockup = &cayman_dma_is_lockup, |
|
| - | 1759 | .vm_flush = &si_dma_vm_flush, |
|
| 1640 | } |
1760 | } |
| 1641 | }, |
1761 | }, |
| 1642 | .irq = { |
1762 | .irq = { |
| 1643 | .set = &si_irq_set, |
1763 | .set = &si_irq_set, |
| 1644 | .process = &si_irq_process, |
1764 | .process = &si_irq_process, |
| Line 1651... | Line 1771... | ||
| 1651 | // .get_backlight_level = &atombios_get_backlight_level, |
1771 | // .get_backlight_level = &atombios_get_backlight_level, |
| 1652 | }, |
1772 | }, |
| 1653 | .copy = { |
1773 | .copy = { |
| 1654 | .blit = NULL, |
1774 | .blit = NULL, |
| 1655 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1775 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1656 | .dma = NULL, |
1776 | .dma = &si_copy_dma, |
| 1657 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1777 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1658 | .copy = NULL, |
1778 | .copy = &si_copy_dma, |
| 1659 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1779 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
| 1660 | }, |
1780 | }, |
| 1661 | .surface = { |
1781 | .surface = { |
| 1662 | .set_reg = r600_set_surface_reg, |
1782 | .set_reg = r600_set_surface_reg, |
| 1663 | .clear_reg = r600_clear_surface_reg, |
1783 | .clear_reg = r600_clear_surface_reg, |
| 1664 | }, |
1784 | }, |