WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_asic.c

 #include "atom.h"
 /*
  * Registers accessors functions.
+ */
+/**
+ * radeon_invalid_rreg - dummy reg read function
+ *
+ * @rdev: radeon device pointer
+ * @reg: offset of register
+ *
+ * Dummy register read function.  Used for register blocks
+ * that certain asics don't have (all asics).
+ * Returns the value in the register.
  */
 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
+{
 	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 	BUG_ON(1);
 	return 0;
+}
+/**
+ * radeon_invalid_wreg - dummy reg write function
+ *
+ * @rdev: radeon device pointer
+ * @reg: offset of register
+ * @v: value to write to the register
+ *
+ * Dummy register read function.  Used for register blocks
  * that certain asics don't have (all asics).
  */
 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
 	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 		  reg, v);
+	BUG_ON(1);
+}
+/**
+ * radeon_register_accessor_init - sets up the register accessor callbacks
+ *
+ * @rdev: radeon device pointer
+ *
-	BUG_ON(1);
+ * Sets up the register accessor callbacks for various register
  * apertures.  Not all asics have all apertures (all asics).
  */
 static void radeon_register_accessor_init(struct radeon_device *rdev)
+{
+	}
+}
+/* helper to disable agp */
+/**
+ * radeon_agp_disable - AGP disable helper function
+ *
+ * @rdev: radeon device pointer
+ *
+ * Removes AGP flags and changes the gart callbacks on AGP
  * cards when using the internal gart rather than AGP (all asics).
-/* helper to disable agp */
+ */
 void radeon_agp_disable(struct radeon_device *rdev)
+{
 	rdev->flags &= ~RADEON_IS_AGP;
 			rdev->family == CHIP_RV380 ||
 			rdev->family == CHIP_RV410 ||
 			rdev->family == CHIP_R423) {
 		DRM_INFO("Forcing AGP to PCIE mode\n");
 		rdev->flags |= RADEON_IS_PCIE;
-		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+		rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
-		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+		rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 	} else {
 		DRM_INFO("Forcing AGP to PCI mode\n");
 		rdev->flags |= RADEON_IS_PCI;
-		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+		rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
-		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+		rdev->asic->gart.set_page = &r100_pci_gart_set_page;
+	}
 	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+}
 	.init = &r100_init,
 //	.fini = &r100_fini,
 //	.suspend = &r100_suspend,
 //	.resume = &r100_resume,
 //	.vga_set_state = &r100_vga_set_state,
-	.gpu_is_lockup = &r100_gpu_is_lockup,
 	.asic_reset = &r100_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &r100_mc_wait_for_idle,
+	.gart = {
-	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
+		.tlb_flush = &r100_pci_gart_tlb_flush,
-	.gart_set_page = &r100_pci_gart_set_page,
+		.set_page = &r100_pci_gart_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &r100_ring_ib_execute,
+			.emit_fence = &r100_fence_ring_emit,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.cp_commit = &r100_cp_commit,
+//			.cs_parse = &r100_cs_parse,
-	.ring_start = &r100_ring_start,
+			.ring_start = &r100_ring_start,
-	.ring_test = &r100_ring_test,
+			.ring_test = &r100_ring_test,
-	.ring_ib_execute = &r100_ring_ib_execute,
-	.irq_set = &r100_irq_set,
+			.ib_test = &r100_ib_test,
-	.irq_process = &r100_irq_process,
+			.is_lockup = &r100_gpu_is_lockup,
-//	.get_vblank_counter = &r100_get_vblank_counter,
-	.fence_ring_emit = &r100_fence_ring_emit,
-//	.cs_parse = &r100_cs_parse,
+		}
-	.copy_blit = &r100_copy_blit,
+	},
-	.copy_dma = NULL,
+	.irq = {
-	.copy = &r100_copy_blit,
+		.set = &r100_irq_set,
-	.get_engine_clock = &radeon_legacy_get_engine_clock,
-	.set_engine_clock = &radeon_legacy_set_engine_clock,
-	.get_memory_clock = &radeon_legacy_get_memory_clock,
-	.set_memory_clock = NULL,
+		.process = &r100_irq_process,
-	.get_pcie_lanes = NULL,
+	},
-	.set_pcie_lanes = NULL,
+	.display = {
-	.set_clock_gating = &radeon_legacy_set_clock_gating,
-	.set_surface_reg = r100_set_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
-	.bandwidth_update = &r100_bandwidth_update,
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &radeon_legacy_set_backlight_level,
+//		.get_backlight_level = &radeon_legacy_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
+	},
+	.hpd = {
-	.hpd_init = &r100_hpd_init,
+//		.init = &r100_hpd_init,
-	.hpd_fini = &r100_hpd_fini,
+//		.fini = &r100_hpd_fini,
-	.hpd_sense = &r100_hpd_sense,
+//		.sense = &r100_hpd_sense,
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+//		.set_polarity = &r100_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r100_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_legacy_get_engine_clock,
+//		.set_engine_clock = &radeon_legacy_set_engine_clock,
+//		.get_memory_clock = &radeon_legacy_get_memory_clock,
+//		.set_memory_clock = NULL,
+//		.get_pcie_lanes = NULL,
-	.ioctl_wait_idle = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = &radeon_legacy_set_clock_gating,
+	},
+	.pflip = {
+//		.pre_page_flip = &r100_pre_page_flip,
-	.gui_idle = &r100_gui_idle,
+//		.page_flip = &r100_page_flip,
+//		.post_page_flip = &r100_post_page_flip,
+	},
 };
 static struct radeon_asic r200_asic = {
 	.init = &r100_init,
 //	.fini = &r100_fini,
 //	.suspend = &r100_suspend,
 //	.resume = &r100_resume,
-//	.vga_set_state = &r100_vga_set_state,
-	.gpu_is_lockup = &r100_gpu_is_lockup,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &r100_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &r100_mc_wait_for_idle,
-	.asic_reset = &r100_asic_reset,
+	.gart = {
-	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
+		.tlb_flush = &r100_pci_gart_tlb_flush,
+		.set_page = &r100_pci_gart_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &r100_ring_ib_execute,
+			.emit_fence = &r100_fence_ring_emit,
-	.gart_set_page = &r100_pci_gart_set_page,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.cp_commit = &r100_cp_commit,
+//			.cs_parse = &r100_cs_parse,
-	.ring_start = &r100_ring_start,
+			.ring_start = &r100_ring_start,
-	.ring_test = &r100_ring_test,
-	.ring_ib_execute = &r100_ring_ib_execute,
+			.ring_test = &r100_ring_test,
-	.irq_set = &r100_irq_set,
+			.ib_test = &r100_ib_test,
-	.irq_process = &r100_irq_process,
-//	.get_vblank_counter = &r100_get_vblank_counter,
+			.is_lockup = &r100_gpu_is_lockup,
+		}
-	.fence_ring_emit = &r100_fence_ring_emit,
+	},
-//	.cs_parse = &r100_cs_parse,
+	.irq = {
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
+		.set = &r100_irq_set,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_legacy_get_engine_clock,
-	.set_engine_clock = &radeon_legacy_set_engine_clock,
-	.get_memory_clock = &radeon_legacy_get_memory_clock,
+		.process = &r100_irq_process,
-	.set_memory_clock = NULL,
+	},
-	.set_pcie_lanes = NULL,
-	.set_clock_gating = &radeon_legacy_set_clock_gating,
-	.set_surface_reg = r100_set_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
+	.display = {
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &radeon_legacy_set_backlight_level,
+//		.get_backlight_level = &radeon_legacy_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
+	},
-	.bandwidth_update = &r100_bandwidth_update,
+	.hpd = {
-	.hpd_init = &r100_hpd_init,
+//		.init = &r100_hpd_init,
-	.hpd_fini = &r100_hpd_fini,
+//		.fini = &r100_hpd_fini,
-	.hpd_sense = &r100_hpd_sense,
+//		.sense = &r100_hpd_sense,
+//		.set_polarity = &r100_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r100_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_legacy_get_engine_clock,
+//		.set_engine_clock = &radeon_legacy_set_engine_clock,
+//		.get_memory_clock = &radeon_legacy_get_memory_clock,
+//		.set_memory_clock = NULL,
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = &radeon_legacy_set_clock_gating,
+	},
+	.pflip = {
-	.ioctl_wait_idle = NULL,
+//		.pre_page_flip = &r100_pre_page_flip,
+//		.page_flip = &r100_page_flip,
+//		.post_page_flip = &r100_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
 static struct radeon_asic r300_asic = {
 	.init = &r300_init,
 //	.fini = &r300_fini,
 //	.suspend = &r300_suspend,
 //	.resume = &r300_resume,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &r300_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
-//	.vga_set_state = &r100_vga_set_state,
+	.mc_wait_for_idle = &r300_mc_wait_for_idle,
-	.asic_reset = &r300_asic_reset,
+	.gart = {
+		.tlb_flush = &r100_pci_gart_tlb_flush,
+		.set_page = &r100_pci_gart_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
+			.emit_fence = &r300_fence_ring_emit,
-	.gart_set_page = &r100_pci_gart_set_page,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.cp_commit = &r100_cp_commit,
+//			.cs_parse = &r300_cs_parse,
-	.ring_start = &r300_ring_start,
-	.ring_test = &r100_ring_test,
+			.ring_start = &r300_ring_start,
-	.ring_ib_execute = &r100_ring_ib_execute,
+			.ring_test = &r100_ring_test,
-	.irq_set = &r100_irq_set,
-	.irq_process = &r100_irq_process,
+			.ib_test = &r100_ib_test,
+			.is_lockup = &r100_gpu_is_lockup,
-//	.get_vblank_counter = &r100_get_vblank_counter,
+		}
-	.fence_ring_emit = &r300_fence_ring_emit,
+	},
-//	.cs_parse = &r300_cs_parse,
+	.irq = {
-	.copy_blit = &r100_copy_blit,
+		.set = &r100_irq_set,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_legacy_get_engine_clock,
-	.set_engine_clock = &radeon_legacy_set_engine_clock,
+		.process = &r100_irq_process,
-	.get_memory_clock = &radeon_legacy_get_memory_clock,
-	.set_memory_clock = NULL,
-	.get_pcie_lanes = &rv370_get_pcie_lanes,
-	.set_pcie_lanes = &rv370_set_pcie_lanes,
-	.set_clock_gating = &radeon_legacy_set_clock_gating,
-	.set_surface_reg = r100_set_surface_reg,
+	},
+	.display = {
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &radeon_legacy_set_backlight_level,
+//		.get_backlight_level = &radeon_legacy_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
+	},
-	.bandwidth_update = &r100_bandwidth_update,
+	.hpd = {
-	.hpd_init = &r100_hpd_init,
+//		.init = &r100_hpd_init,
-	.hpd_fini = &r100_hpd_fini,
+//		.fini = &r100_hpd_fini,
+//		.sense = &r100_hpd_sense,
+//		.set_polarity = &r100_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r100_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_legacy_get_engine_clock,
-	.hpd_sense = &r100_hpd_sense,
+//		.set_engine_clock = &radeon_legacy_set_engine_clock,
+//		.get_memory_clock = &radeon_legacy_get_memory_clock,
+//		.set_memory_clock = NULL,
+//		.get_pcie_lanes = &rv370_get_pcie_lanes,
+//		.set_pcie_lanes = &rv370_set_pcie_lanes,
+//		.set_clock_gating = &radeon_legacy_set_clock_gating,
+	},
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+	.pflip = {
+//		.pre_page_flip = &r100_pre_page_flip,
+//		.page_flip = &r100_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &r100_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
 static struct radeon_asic r300_asic_pcie = {
 	.init = &r300_init,
 //	.fini = &r300_fini,
 //	.suspend = &r300_suspend,
+//	.resume = &r300_resume,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &r300_asic_reset,
+//	.ioctl_wait_idle = NULL,
-//	.resume = &r300_resume,
+	.gui_idle = &r100_gui_idle,
-//	.vga_set_state = &r100_vga_set_state,
+	.mc_wait_for_idle = &r300_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.set_page = &rv370_pcie_gart_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.asic_reset = &r300_asic_reset,
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+			.emit_fence = &r300_fence_ring_emit,
-	.gart_set_page = &rv370_pcie_gart_set_page,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.cp_commit = &r100_cp_commit,
-	.ring_start = &r300_ring_start,
+//			.cs_parse = &r300_cs_parse,
-	.ring_test = &r100_ring_test,
+			.ring_start = &r300_ring_start,
-	.ring_ib_execute = &r100_ring_ib_execute,
-	.irq_set = &r100_irq_set,
+			.ring_test = &r100_ring_test,
+			.ib_test = &r100_ib_test,
-	.irq_process = &r100_irq_process,
+			.is_lockup = &r100_gpu_is_lockup,
-//	.get_vblank_counter = &r100_get_vblank_counter,
+		}
-	.fence_ring_emit = &r300_fence_ring_emit,
+	},
-//	.cs_parse = &r300_cs_parse,
+	.irq = {
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_legacy_get_engine_clock,
+		.set = &r100_irq_set,
-	.set_engine_clock = &radeon_legacy_set_engine_clock,
-	.get_memory_clock = &radeon_legacy_get_memory_clock,
-	.set_memory_clock = NULL,
-	.set_pcie_lanes = &rv370_set_pcie_lanes,
-	.set_clock_gating = &radeon_legacy_set_clock_gating,
+		.process = &r100_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &radeon_legacy_set_backlight_level,
+//		.get_backlight_level = &radeon_legacy_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r100_set_surface_reg,
-	.set_surface_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
+	},
-	.bandwidth_update = &r100_bandwidth_update,
+	.hpd = {
-	.hpd_init = &r100_hpd_init,
+		.init = &r100_hpd_init,
+		.fini = &r100_hpd_fini,
+		.sense = &r100_hpd_sense,
+		.set_polarity = &r100_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r100_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
-	.hpd_fini = &r100_hpd_fini,
+//		.get_engine_clock = &radeon_legacy_get_engine_clock,
+//		.set_engine_clock = &radeon_legacy_set_engine_clock,
+//		.get_memory_clock = &radeon_legacy_get_memory_clock,
+//		.set_memory_clock = NULL,
+//		.get_pcie_lanes = &rv370_get_pcie_lanes,
+//		.set_pcie_lanes = &rv370_set_pcie_lanes,
+//		.set_clock_gating = &radeon_legacy_set_clock_gating,
-	.hpd_sense = &r100_hpd_sense,
+	},
+	.pflip = {
+//		.pre_page_flip = &r100_pre_page_flip,
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+//		.page_flip = &r100_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &r100_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
 static struct radeon_asic r420_asic = {
 	.init = &r420_init,
 //	.fini = &r420_fini,
+//	.suspend = &r420_suspend,
+//	.resume = &r420_resume,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &r300_asic_reset,
-//	.suspend = &r420_suspend,
+//	.ioctl_wait_idle = NULL,
-//	.resume = &r420_resume,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &r300_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.set_page = &rv370_pcie_gart_set_page,
+	},
+	.ring = {
-//	.vga_set_state = &r100_vga_set_state,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.asic_reset = &r300_asic_reset,
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+			.emit_fence = &r300_fence_ring_emit,
-	.gart_set_page = &rv370_pcie_gart_set_page,
-	.cp_commit = &r100_cp_commit,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.ring_start = &r300_ring_start,
+//			.cs_parse = &r300_cs_parse,
-	.ring_test = &r100_ring_test,
-	.ring_ib_execute = &r100_ring_ib_execute,
-	.irq_set = &r100_irq_set,
+			.ring_start = &r300_ring_start,
-	.irq_process = &r100_irq_process,
+			.ring_test = &r100_ring_test,
-//	.get_vblank_counter = &r100_get_vblank_counter,
+			.ib_test = &r100_ib_test,
-	.fence_ring_emit = &r300_fence_ring_emit,
+			.is_lockup = &r100_gpu_is_lockup,
-//	.cs_parse = &r300_cs_parse,
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		}
+	},
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+	.irq = {
-	.get_memory_clock = &radeon_atom_get_memory_clock,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
-	.get_pcie_lanes = &rv370_get_pcie_lanes,
-	.set_pcie_lanes = &rv370_set_pcie_lanes,
+		.set = &r100_irq_set,
+		.process = &r100_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+		.set_reg = r100_set_surface_reg,
-	.set_surface_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
+	},
-	.bandwidth_update = &r100_bandwidth_update,
+	.hpd = {
+//		.init = &r100_hpd_init,
+//		.fini = &r100_hpd_fini,
-	.hpd_init = &r100_hpd_init,
+//		.sense = &r100_hpd_sense,
+//		.set_polarity = &r100_hpd_set_polarity,
-	.hpd_fini = &r100_hpd_fini,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r420_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_pcie_lanes = &rv370_get_pcie_lanes,
+//		.set_pcie_lanes = &rv370_set_pcie_lanes,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
+	},
+	.pflip = {
-	.hpd_sense = &r100_hpd_sense,
+//		.pre_page_flip = &r100_pre_page_flip,
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+//		.page_flip = &r100_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &r100_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
 static struct radeon_asic rs400_asic = {
 	.init = &rs400_init,
+//	.fini = &rs400_fini,
+//	.suspend = &rs400_suspend,
+//	.resume = &rs400_resume,
+//	.vga_set_state = &r100_vga_set_state,
-//	.fini = &rs400_fini,
+	.asic_reset = &r300_asic_reset,
-//	.suspend = &rs400_suspend,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &rs400_gart_tlb_flush,
+		.set_page = &rs400_gart_set_page,
+	},
-//	.resume = &rs400_resume,
+	.ring = {
-//	.vga_set_state = &r100_vga_set_state,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.asic_reset = &r300_asic_reset,
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_tlb_flush = &rs400_gart_tlb_flush,
-	.gart_set_page = &rs400_gart_set_page,
+			.emit_fence = &r300_fence_ring_emit,
-	.cp_commit = &r100_cp_commit,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.ring_start = &r300_ring_start,
-	.ring_test = &r100_ring_test,
+//			.cs_parse = &r300_cs_parse,
+			.ring_start = &r300_ring_start,
-	.ring_ib_execute = &r100_ring_ib_execute,
+			.ring_test = &r100_ring_test,
-	.irq_set = &r100_irq_set,
+			.ib_test = &r100_ib_test,
-	.irq_process = &r100_irq_process,
-//	.get_vblank_counter = &r100_get_vblank_counter,
+			.is_lockup = &r100_gpu_is_lockup,
-	.fence_ring_emit = &r300_fence_ring_emit,
-//	.cs_parse = &r300_cs_parse,
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
+		}
-	.get_engine_clock = &radeon_legacy_get_engine_clock,
+	},
-	.set_engine_clock = &radeon_legacy_set_engine_clock,
-	.get_memory_clock = &radeon_legacy_get_memory_clock,
-	.set_memory_clock = NULL,
-	.get_pcie_lanes = NULL,
+	.irq = {
+		.set = &r100_irq_set,
+		.process = &r100_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &r100_bandwidth_update,
+		.get_vblank_counter = &r100_get_vblank_counter,
+		.wait_for_vblank = &r100_wait_for_vblank,
+//		.set_backlight_level = &radeon_legacy_set_backlight_level,
+//		.get_backlight_level = &radeon_legacy_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
-	.set_pcie_lanes = NULL,
+	.surface = {
-	.set_clock_gating = &radeon_legacy_set_clock_gating,
+		.set_reg = r100_set_surface_reg,
-	.set_surface_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
-	.clear_surface_reg = r100_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &r100_hpd_init,
+//		.fini = &r100_hpd_fini,
+//		.sense = &r100_hpd_sense,
+//		.set_polarity = &r100_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r100_pm_misc,
+//		.prepare = &r100_pm_prepare,
+//		.finish = &r100_pm_finish,
+//		.init_profile = &r100_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
-	.bandwidth_update = &r100_bandwidth_update,
+//		.get_engine_clock = &radeon_legacy_get_engine_clock,
+//		.set_engine_clock = &radeon_legacy_set_engine_clock,
+//		.get_memory_clock = &radeon_legacy_get_memory_clock,
+//		.set_memory_clock = NULL,
+//		.get_pcie_lanes = NULL,
-	.hpd_init = &r100_hpd_init,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = &radeon_legacy_set_clock_gating,
+	},
-	.hpd_fini = &r100_hpd_fini,
+	.pflip = {
-	.hpd_sense = &r100_hpd_sense,
+//		.pre_page_flip = &r100_pre_page_flip,
-	.hpd_set_polarity = &r100_hpd_set_polarity,
+//		.page_flip = &r100_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &r100_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
 static struct radeon_asic rs600_asic = {
+	.init = &rs600_init,
+//	.fini = &rs600_fini,
+//	.suspend = &rs600_suspend,
+//	.resume = &rs600_resume,
-	.init = &rs600_init,
+//	.vga_set_state = &r100_vga_set_state,
-//	.fini = &rs600_fini,
+	.asic_reset = &rs600_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &rs600_gart_tlb_flush,
+		.set_page = &rs600_gart_set_page,
-//	.suspend = &rs600_suspend,
+	},
-//	.resume = &rs600_resume,
+	.ring = {
-//	.vga_set_state = &r100_vga_set_state,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.asic_reset = &rs600_asic_reset,
-	.gart_tlb_flush = &rs600_gart_tlb_flush,
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_set_page = &rs600_gart_set_page,
+			.emit_fence = &r300_fence_ring_emit,
-	.cp_commit = &r100_cp_commit,
-	.ring_start = &r300_ring_start,
+			.emit_semaphore = &r100_semaphore_ring_emit,
+//			.cs_parse = &r300_cs_parse,
-	.ring_test = &r100_ring_test,
+			.ring_start = &r300_ring_start,
-	.ring_ib_execute = &r100_ring_ib_execute,
-	.irq_set = &rs600_irq_set,
+			.ring_test = &r100_ring_test,
-	.irq_process = &rs600_irq_process,
+			.ib_test = &r100_ib_test,
-//	.get_vblank_counter = &rs600_get_vblank_counter,
-	.fence_ring_emit = &r300_fence_ring_emit,
-//   .cs_parse = &r300_cs_parse,
-    .copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
+			.is_lockup = &r100_gpu_is_lockup,
-    .copy = &r100_copy_blit,
+		}
-	.get_engine_clock = &radeon_atom_get_engine_clock,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+	},
+	.irq = {
+		.set = &rs600_irq_set,
+		.process = &rs600_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &rs600_bandwidth_update,
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r100_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_pcie_lanes = NULL,
+	},
-	.set_pcie_lanes = NULL,
+	.surface = {
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+		.set_reg = r100_set_surface_reg,
-	.set_surface_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &rs600_hpd_init,
+//		.fini = &rs600_hpd_fini,
+//		.sense = &rs600_hpd_sense,
+//		.set_polarity = &rs600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &rs600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &r420_pm_init_profile,
-	.clear_surface_reg = r100_clear_surface_reg,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.bandwidth_update = &rs600_bandwidth_update,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
-	.hpd_init = &rs600_hpd_init,
+	},
-	.hpd_fini = &rs600_hpd_fini,
+	.pflip = {
-	.hpd_sense = &rs600_hpd_sense,
+//		.pre_page_flip = &rs600_pre_page_flip,
-	.hpd_set_polarity = &rs600_hpd_set_polarity,
+//		.page_flip = &rs600_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &rs600_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
+static struct radeon_asic rs690_asic = {
+	.init = &rs690_init,
+//	.fini = &rs690_fini,
+//	.suspend = &rs690_suspend,
-static struct radeon_asic rs690_asic = {
+//	.resume = &rs690_resume,
-	.init = &rs690_init,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &rs600_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &rs400_gart_tlb_flush,
-//	.fini = &rs690_fini,
+		.set_page = &rs400_gart_set_page,
-//	.suspend = &rs690_suspend,
+	},
-//	.resume = &rs690_resume,
+	.ring = {
-//	.vga_set_state = &r100_vga_set_state,
-	.asic_reset = &rs600_asic_reset,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.gart_tlb_flush = &rs400_gart_tlb_flush,
+			.ib_execute = &r100_ring_ib_execute,
-	.gart_set_page = &rs400_gart_set_page,
-	.cp_commit = &r100_cp_commit,
+			.emit_fence = &r300_fence_ring_emit,
-	.ring_start = &r300_ring_start,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.ring_test = &r100_ring_test,
+//			.cs_parse = &r300_cs_parse,
-	.ring_ib_execute = &r100_ring_ib_execute,
+			.ring_start = &r300_ring_start,
-	.irq_set = &rs600_irq_set,
+			.ring_test = &r100_ring_test,
-	.irq_process = &rs600_irq_process,
-//	.get_vblank_counter = &rs600_get_vblank_counter,
-	.fence_ring_emit = &r300_fence_ring_emit,
-//	.cs_parse = &r300_cs_parse,
-	.copy_blit = &r100_copy_blit,
+			.ib_test = &r100_ib_test,
-	.copy_dma = &r200_copy_dma,
+			.is_lockup = &r100_gpu_is_lockup,
-	.copy = &r200_copy_dma,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		}
-	.set_engine_clock = &radeon_atom_set_engine_clock,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+	},
+	.irq = {
+		.set = &rs600_irq_set,
+		.process = &rs600_irq_process,
+	},
+	.display = {
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.bandwidth_update = &rs690_bandwidth_update,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r200_copy_dma,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_pcie_lanes = NULL,
+	},
-	.set_pcie_lanes = NULL,
+	.surface = {
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+		.set_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &rs600_hpd_init,
+//		.fini = &rs600_hpd_fini,
+		.sense = &rs600_hpd_sense,
+		.set_polarity = &rs600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &rs600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
-	.set_surface_reg = r100_set_surface_reg,
+//		.init_profile = &r420_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
-	.clear_surface_reg = r100_clear_surface_reg,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
-	.bandwidth_update = &rs690_bandwidth_update,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
-	.hpd_init = &rs600_hpd_init,
+	},
-	.hpd_fini = &rs600_hpd_fini,
+	.pflip = {
-	.hpd_sense = &rs600_hpd_sense,
+//		.pre_page_flip = &rs600_pre_page_flip,
-	.hpd_set_polarity = &rs600_hpd_set_polarity,
+//		.page_flip = &rs600_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &rs600_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
 };
+static struct radeon_asic rv515_asic = {
+	.init = &rv515_init,
+//	.fini = &rv515_fini,
+//	.suspend = &rv515_suspend,
-static struct radeon_asic rv515_asic = {
+//	.resume = &rv515_resume,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &rs600_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
+	.gart = {
-	.init = &rv515_init,
+		.tlb_flush = &rv370_pcie_gart_tlb_flush,
-//	.fini = &rv515_fini,
+		.set_page = &rv370_pcie_gart_set_page,
-//	.suspend = &rv515_suspend,
+	},
-//	.resume = &rv515_resume,
-//	.vga_set_state = &r100_vga_set_state,
+	.ring = {
-	.asic_reset = &rs600_asic_reset,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-	.gart_set_page = &rv370_pcie_gart_set_page,
+			.ib_execute = &r100_ring_ib_execute,
+			.emit_fence = &r300_fence_ring_emit,
-	.cp_commit = &r100_cp_commit,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.ring_start = &rv515_ring_start,
+//			.cs_parse = &r300_cs_parse,
-	.ring_test = &r100_ring_test,
+			.ring_start = &rv515_ring_start,
+			.ring_test = &r100_ring_test,
-	.ring_ib_execute = &r100_ring_ib_execute,
+			.ib_test = &r100_ib_test,
-	.irq_set = &rs600_irq_set,
-	.irq_process = &rs600_irq_process,
-//	.get_vblank_counter = &rs600_get_vblank_counter,
-	.fence_ring_emit = &r300_fence_ring_emit,
-//	.cs_parse = &r300_cs_parse,
+			.is_lockup = &r100_gpu_is_lockup,
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
 	.set_engine_clock = &radeon_atom_set_engine_clock,
+	},
+	.irq = {
+		.set = &rs600_irq_set,
+		.process = &rs600_irq_process,
+	},
+	.display = {
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.bandwidth_update = &rv515_bandwidth_update,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+		.copy = &r100_copy_blit,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_pcie_lanes = &rv370_get_pcie_lanes,
+	},
-	.set_pcie_lanes = &rv370_set_pcie_lanes,
+	.surface = {
+		.set_reg = r100_set_surface_reg,
+		.clear_reg = r100_clear_surface_reg,
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+	},
+	.hpd = {
-	.set_surface_reg = r100_set_surface_reg,
+//		.init = &rs600_hpd_init,
+//		.fini = &rs600_hpd_fini,
+//		.sense = &rs600_hpd_sense,
+//		.set_polarity = &rs600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &rs600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &r420_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_pcie_lanes = &rv370_get_pcie_lanes,
-	.clear_surface_reg = r100_clear_surface_reg,
+//		.set_pcie_lanes = &rv370_set_pcie_lanes,
-	.bandwidth_update = &rv515_bandwidth_update,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
-	.hpd_init = &rs600_hpd_init,
+	},
-	.hpd_fini = &rs600_hpd_fini,
+	.pflip = {
-	.hpd_sense = &rs600_hpd_sense,
+//		.pre_page_flip = &rs600_pre_page_flip,
-	.hpd_set_polarity = &rs600_hpd_set_polarity,
+//		.page_flip = &rs600_page_flip,
-	.ioctl_wait_idle = NULL,
+//		.post_page_flip = &rs600_post_page_flip,
-	.gui_idle = &r100_gui_idle,
+	},
+};
+static struct radeon_asic r520_asic = {
+	.init = &r520_init,
-};
+//	.fini = &rv515_fini,
+//	.suspend = &rv515_suspend,
+//	.resume = &r520_resume,
+//	.vga_set_state = &r100_vga_set_state,
+	.asic_reset = &rs600_asic_reset,
+//	.ioctl_wait_idle = NULL,
+	.gui_idle = &r100_gui_idle,
+	.mc_wait_for_idle = &r520_mc_wait_for_idle,
-static struct radeon_asic r520_asic = {
+	.gart = {
-	.init = &r520_init,
+		.tlb_flush = &rv370_pcie_gart_tlb_flush,
-//	.fini = &rv515_fini,
+		.set_page = &rv370_pcie_gart_set_page,
-//	.suspend = &rv515_suspend,
-//	.resume = &r520_resume,
+	},
-//	.vga_set_state = &r100_vga_set_state,
+	.ring = {
-	.asic_reset = &rs600_asic_reset,
-	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
-	.gart_set_page = &rv370_pcie_gart_set_page,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.cp_commit = &r100_cp_commit,
+			.ib_execute = &r100_ring_ib_execute,
-	.ring_start = &rv515_ring_start,
+			.emit_fence = &r300_fence_ring_emit,
-	.ring_test = &r100_ring_test,
+			.emit_semaphore = &r100_semaphore_ring_emit,
-	.ring_ib_execute = &r100_ring_ib_execute,
-	.irq_set = &rs600_irq_set,
-	.irq_process = &rs600_irq_process,
-//	.get_vblank_counter = &rs600_get_vblank_counter,
-	.fence_ring_emit = &r300_fence_ring_emit,
+//			.cs_parse = &r300_cs_parse,
+			.ring_start = &rv515_ring_start,
-//	.cs_parse = &r300_cs_parse,
+			.ring_test = &r100_ring_test,
-	.copy_blit = &r100_copy_blit,
-	.copy_dma = &r200_copy_dma,
-	.copy = &r100_copy_blit,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+			.ib_test = &r100_ib_test,
+			.is_lockup = &r100_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &rs600_irq_set,
+		.process = &rs600_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &rv515_bandwidth_update,
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r100_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = &r200_copy_dma,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+		.copy = &r100_copy_blit,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_pcie_lanes = &rv370_get_pcie_lanes,
+	},
+	.surface = {
+		.set_reg = r100_set_surface_reg,
-	.set_pcie_lanes = &rv370_set_pcie_lanes,
+		.clear_reg = r100_clear_surface_reg,
+	},
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+	.hpd = {
+//		.init = &rs600_hpd_init,
+//		.fini = &rs600_hpd_fini,
+//		.sense = &rs600_hpd_sense,
+//		.set_polarity = &rs600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &rs600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &r420_pm_init_profile,
+//		.get_dynpm_state = &r100_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.set_surface_reg = r100_set_surface_reg,
+//		.get_pcie_lanes = &rv370_get_pcie_lanes,
-	.clear_surface_reg = r100_clear_surface_reg,
+//		.set_pcie_lanes = &rv370_set_pcie_lanes,
-	.bandwidth_update = &rv515_bandwidth_update,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
-	.hpd_init = &rs600_hpd_init,
+	},
-	.hpd_fini = &rs600_hpd_fini,
+	.pflip = {
-	.hpd_sense = &rs600_hpd_sense,
+//		.pre_page_flip = &rs600_pre_page_flip,
-	.hpd_set_polarity = &rs600_hpd_set_polarity,
-	.ioctl_wait_idle = NULL,
+//		.page_flip = &rs600_page_flip,
-	.gui_idle = &r100_gui_idle,
+//		.post_page_flip = &rs600_post_page_flip,
+	},
+};
+static struct radeon_asic r600_asic = {
-};
+	.init = &r600_init,
+//	.fini = &r600_fini,
+//	.suspend = &r600_suspend,
-static struct radeon_asic r600_asic = {
+//	.resume = &r600_resume,
-	.init = &r600_init,
+//	.vga_set_state = &r600_vga_set_state,
-//	.fini = &r600_fini,
+	.asic_reset = &r600_asic_reset,
-//	.suspend = &r600_suspend,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-//	.resume = &r600_resume,
+	.gui_idle = &r600_gui_idle,
-	.cp_commit = &r600_cp_commit,
+	.mc_wait_for_idle = &r600_mc_wait_for_idle,
-	.vga_set_state = &r600_vga_set_state,
+	.gart = {
-	.asic_reset = &r600_asic_reset,
-	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+		.tlb_flush = &r600_pcie_gart_tlb_flush,
-	.gart_set_page = &rs600_gart_set_page,
+		.set_page = &rs600_gart_set_page,
-	.ring_test = &r600_ring_test,
-	.ring_ib_execute = &r600_ring_ib_execute,
+	},
+	.ring = {
-	.irq_set = &r600_irq_set,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.irq_process = &r600_irq_process,
+			.ib_execute = &r600_ring_ib_execute,
-	.fence_ring_emit = &r600_fence_ring_emit,
+			.emit_fence = &r600_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
-//	.cs_parse = &r600_cs_parse,
+//			.cs_parse = &r600_cs_parse,
-	.copy_blit = &r600_copy_blit,
-	.copy_dma = NULL,
-	.copy = &r600_copy_blit,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &r600_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &r600_irq_set,
+		.process = &r600_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &rv515_bandwidth_update,
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		.dma = NULL,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+		.copy = &r600_copy_blit,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &r600_hpd_init,
+//		.fini = &r600_hpd_fini,
+//		.sense = &r600_hpd_sense,
+//		.set_polarity = &r600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &r600_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
-	.get_pcie_lanes = &r600_get_pcie_lanes,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
-	.set_pcie_lanes = &r600_set_pcie_lanes,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.set_clock_gating = NULL,
+//		.get_pcie_lanes = &r600_get_pcie_lanes,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_pcie_lanes = &r600_set_pcie_lanes,
-	.clear_surface_reg = r600_clear_surface_reg,
+//		.set_clock_gating = NULL,
-	.bandwidth_update = &rv515_bandwidth_update,
+	},
-	.hpd_init = &r600_hpd_init,
+	.pflip = {
-	.hpd_fini = &r600_hpd_fini,
-	.hpd_sense = &r600_hpd_sense,
-	.hpd_set_polarity = &r600_hpd_set_polarity,
+//		.pre_page_flip = &rs600_pre_page_flip,
-//	.ioctl_wait_idle = r600_ioctl_wait_idle,
+//		.page_flip = &rs600_page_flip,
+//		.post_page_flip = &rs600_post_page_flip,
+	},
+};
-};
+static struct radeon_asic rs780_asic = {
+	.init = &r600_init,
+//	.fini = &r600_fini,
-static struct radeon_asic rs780_asic = {
+//	.suspend = &r600_suspend,
-	.init = &r600_init,
+//	.resume = &r600_resume,
-//	.fini = &r600_fini,
+//	.vga_set_state = &r600_vga_set_state,
-//	.suspend = &r600_suspend,
+	.asic_reset = &r600_asic_reset,
-//	.resume = &r600_resume,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-	.cp_commit = &r600_cp_commit,
+	.gui_idle = &r600_gui_idle,
-	.gpu_is_lockup = &r600_gpu_is_lockup,
+	.mc_wait_for_idle = &r600_mc_wait_for_idle,
-	.vga_set_state = &r600_vga_set_state,
-	.asic_reset = &r600_asic_reset,
+	.gart = {
-	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+		.tlb_flush = &r600_pcie_gart_tlb_flush,
-	.gart_set_page = &rs600_gart_set_page,
-	.ring_test = &r600_ring_test,
-	.ring_ib_execute = &r600_ring_ib_execute,
+		.set_page = &rs600_gart_set_page,
-	.irq_set = &r600_irq_set,
+	},
-	.irq_process = &r600_irq_process,
+	.ring = {
-	.fence_ring_emit = &r600_fence_ring_emit,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-//	.cs_parse = &r600_cs_parse,
+			.ib_execute = &r600_ring_ib_execute,
+			.emit_fence = &r600_fence_ring_emit,
-	.copy_blit = &r600_copy_blit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
-	.copy_dma = NULL,
+//			.cs_parse = &r600_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &r600_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &r600_irq_set,
+		.process = &r600_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &rs690_bandwidth_update,
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r600_copy_blit,
-	.copy = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		.dma = NULL,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_memory_clock = NULL,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &r600_hpd_init,
+//		.fini = &r600_hpd_fini,
+//		.sense = &r600_hpd_sense,
+//		.set_polarity = &r600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &r600_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &rs780_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
-	.set_memory_clock = NULL,
+//		.get_memory_clock = NULL,
-	.get_pcie_lanes = NULL,
+//		.set_memory_clock = NULL,
-	.set_pcie_lanes = NULL,
+//		.get_pcie_lanes = NULL,
-	.set_clock_gating = NULL,
+//		.set_pcie_lanes = NULL,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_clock_gating = NULL,
-	.clear_surface_reg = r600_clear_surface_reg,
+	},
-	.bandwidth_update = &rs690_bandwidth_update,
-	.hpd_init = &r600_hpd_init,
+	.pflip = {
-	.hpd_fini = &r600_hpd_fini,
+//		.pre_page_flip = &rs600_pre_page_flip,
+//		.page_flip = &rs600_page_flip,
+//		.post_page_flip = &rs600_post_page_flip,
+	},
+};
-	.hpd_sense = &r600_hpd_sense,
-	.hpd_set_polarity = &r600_hpd_set_polarity,
+static struct radeon_asic rv770_asic = {
+	.init = &rv770_init,
-};
+//	.fini = &rv770_fini,
+//	.suspend = &rv770_suspend,
-static struct radeon_asic rv770_asic = {
+//	.resume = &rv770_resume,
-	.init = &rv770_init,
+	.asic_reset = &r600_asic_reset,
-//	.fini = &rv770_fini,
+//	.vga_set_state = &r600_vga_set_state,
-//	.suspend = &rv770_suspend,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-//	.resume = &rv770_resume,
+	.gui_idle = &r600_gui_idle,
-	.cp_commit = &r600_cp_commit,
-	.asic_reset = &r600_asic_reset,
+	.mc_wait_for_idle = &r600_mc_wait_for_idle,
-	.vga_set_state = &r600_vga_set_state,
+	.gart = {
-	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
-	.gart_set_page = &rs600_gart_set_page,
-	.ring_test = &r600_ring_test,
+		.tlb_flush = &r600_pcie_gart_tlb_flush,
+		.set_page = &rs600_gart_set_page,
-	.ring_ib_execute = &r600_ring_ib_execute,
+	},
-	.irq_set = &r600_irq_set,
+	.ring = {
-	.irq_process = &r600_irq_process,
-	.fence_ring_emit = &r600_fence_ring_emit,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &r600_ring_ib_execute,
-//	.cs_parse = &r600_cs_parse,
+			.emit_fence = &r600_fence_ring_emit,
-	.copy_blit = &r600_copy_blit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &r600_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &r600_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &r600_irq_set,
+		.process = &r600_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &rv515_bandwidth_update,
+		.get_vblank_counter = &rs600_get_vblank_counter,
+		.wait_for_vblank = &avivo_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
-	.copy_dma = NULL,
+		.blit = &r600_copy_blit,
-	.copy = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		.dma = NULL,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &r600_hpd_init,
+//		.fini = &r600_hpd_fini,
+//		.sense = &r600_hpd_sense,
+//		.set_polarity = &r600_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &rv770_pm_misc,
+//		.prepare = &rs600_pm_prepare,
+//		.finish = &rs600_pm_finish,
+//		.init_profile = &r600_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
-	.get_pcie_lanes = &r600_get_pcie_lanes,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.set_pcie_lanes = &r600_set_pcie_lanes,
+//		.get_pcie_lanes = &r600_get_pcie_lanes,
-	.set_clock_gating = &radeon_atom_set_clock_gating,
+//		.set_pcie_lanes = &r600_set_pcie_lanes,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_clock_gating = &radeon_atom_set_clock_gating,
-	.clear_surface_reg = r600_clear_surface_reg,
-	.bandwidth_update = &rv515_bandwidth_update,
+	},
-	.hpd_init = &r600_hpd_init,
+	.pflip = {
+//		.pre_page_flip = &rs600_pre_page_flip,
+//		.page_flip = &rv770_page_flip,
+//		.post_page_flip = &rs600_post_page_flip,
+	},
-	.hpd_fini = &r600_hpd_fini,
+};
-	.hpd_sense = &r600_hpd_sense,
+static struct radeon_asic evergreen_asic = {
-	.hpd_set_polarity = &r600_hpd_set_polarity,
+	.init = &evergreen_init,
-};
+//	.fini = &evergreen_fini,
+//	.suspend = &evergreen_suspend,
-static struct radeon_asic evergreen_asic = {
+//	.resume = &evergreen_resume,
-	.init = &evergreen_init,
+	.asic_reset = &evergreen_asic_reset,
-//	.fini = &evergreen_fini,
+//	.vga_set_state = &r600_vga_set_state,
-//	.suspend = &evergreen_suspend,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-//	.resume = &evergreen_resume,
+	.gui_idle = &r600_gui_idle,
-	.cp_commit = &r600_cp_commit,
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
-	.asic_reset = &evergreen_asic_reset,
-	.vga_set_state = &r600_vga_set_state,
-	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
+	.gart = {
+		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
-	.gart_set_page = &rs600_gart_set_page,
+		.set_page = &rs600_gart_set_page,
-	.ring_test = &r600_ring_test,
+	},
-	.ring_ib_execute = &evergreen_ring_ib_execute,
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.irq_set = &evergreen_irq_set,
+			.ib_execute = &evergreen_ring_ib_execute,
-	.irq_process = &evergreen_irq_process,
-	.fence_ring_emit = &r600_fence_ring_emit,
-//	.cs_parse = &evergreen_cs_parse,
+			.emit_fence = &r600_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &evergreen_irq_set,
+		.process = &evergreen_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &evergreen_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
-	.copy_blit = &evergreen_copy_blit,
+	.copy = {
-	.copy_dma = NULL,
+		.blit = &r600_copy_blit,
-	.copy = &evergreen_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &evergreen_hpd_init,
+//		.fini = &evergreen_hpd_fini,
+//		.sense = &evergreen_hpd_sense,
+//		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
+//		.finish = &evergreen_pm_finish,
+//		.init_profile = &r600_pm_init_profile,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
-	.get_pcie_lanes = &r600_get_pcie_lanes,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
-	.set_pcie_lanes = &r600_set_pcie_lanes,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.set_clock_gating = NULL,
+//		.get_pcie_lanes = &r600_get_pcie_lanes,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_pcie_lanes = &r600_set_pcie_lanes,
-	.clear_surface_reg = r600_clear_surface_reg,
-	.bandwidth_update = &evergreen_bandwidth_update,
+//		.set_clock_gating = NULL,
-	.hpd_init = &evergreen_hpd_init,
+	},
-	.hpd_fini = &evergreen_hpd_fini,
-	.hpd_sense = &evergreen_hpd_sense,
+	.pflip = {
-	.hpd_set_polarity = &evergreen_hpd_set_polarity,
+//		.pre_page_flip = &evergreen_pre_page_flip,
+//		.page_flip = &evergreen_page_flip,
-};
+//		.post_page_flip = &evergreen_post_page_flip,
+	},
-static struct radeon_asic sumo_asic = {
+};
+static struct radeon_asic sumo_asic = {
 	.init = &evergreen_init,
 //	.fini = &evergreen_fini,
-//	.suspend = &evergreen_suspend,
-//	.resume = &evergreen_resume,
+//	.suspend = &evergreen_suspend,
-	.cp_commit = &r600_cp_commit,
+//	.resume = &evergreen_resume,
 	.asic_reset = &evergreen_asic_reset,
-	.vga_set_state = &r600_vga_set_state,
+//	.vga_set_state = &r600_vga_set_state,
-	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-	.gart_set_page = &rs600_gart_set_page,
+	.gui_idle = &r600_gui_idle,
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+	.gart = {
-	.ring_test = &r600_ring_test,
+		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
-	.ring_ib_execute = &evergreen_ring_ib_execute,
+		.set_page = &rs600_gart_set_page,
-	.irq_set = &evergreen_irq_set,
+	},
+	.ring = {
-	.irq_process = &evergreen_irq_process,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
-	.fence_ring_emit = &r600_fence_ring_emit,
+			.ib_execute = &evergreen_ring_ib_execute,
+			.emit_fence = &r600_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+		},
+	},
+	.irq = {
+		.set = &evergreen_irq_set,
+		.process = &evergreen_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &evergreen_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
-//	.cs_parse = &r600_cs_parse,
+	},
-	.copy_blit = &evergreen_copy_blit,
+	.copy = {
-	.copy_dma = NULL,
+		.blit = &r600_copy_blit,
-	.copy = &evergreen_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &evergreen_hpd_init,
+//		.fini = &evergreen_hpd_fini,
+//		.sense = &evergreen_hpd_sense,
+//		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
+//		.finish = &evergreen_pm_finish,
+//		.init_profile = &sumo_pm_init_profile,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
-	.get_memory_clock = NULL,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
-	.set_memory_clock = NULL,
+//		.get_memory_clock = NULL,
-	.get_pcie_lanes = NULL,
+//		.set_memory_clock = NULL,
-	.set_pcie_lanes = NULL,
+//		.get_pcie_lanes = NULL,
-	.set_clock_gating = NULL,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_pcie_lanes = NULL,
-	.clear_surface_reg = r600_clear_surface_reg,
+//		.set_clock_gating = NULL,
+	},
+	.pflip = {
+//		.pre_page_flip = &evergreen_pre_page_flip,
+//		.page_flip = &evergreen_page_flip,
-	.bandwidth_update = &evergreen_bandwidth_update,
+//		.post_page_flip = &evergreen_post_page_flip,
-	.hpd_init = &evergreen_hpd_init,
+	},
+};
-	.hpd_fini = &evergreen_hpd_fini,
-	.hpd_sense = &evergreen_hpd_sense,
+static struct radeon_asic btc_asic = {
-	.hpd_set_polarity = &evergreen_hpd_set_polarity,
+	.init = &evergreen_init,
-};
+//	.fini = &evergreen_fini,
+//	.suspend = &evergreen_suspend,
-static struct radeon_asic btc_asic = {
+//	.resume = &evergreen_resume,
-	.init = &evergreen_init,
+	.asic_reset = &evergreen_asic_reset,
-//	.fini = &evergreen_fini,
+//	.vga_set_state = &r600_vga_set_state,
-//	.suspend = &evergreen_suspend,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-//	.resume = &evergreen_resume,
-	.cp_commit = &r600_cp_commit,
-	.asic_reset = &evergreen_asic_reset,
-	.vga_set_state = &r600_vga_set_state,
+	.gui_idle = &r600_gui_idle,
-	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
-	.gart_set_page = &rs600_gart_set_page,
+	.gart = {
-	.ring_test = &r600_ring_test,
+		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
-	.ring_ib_execute = &evergreen_ring_ib_execute,
+		.set_page = &rs600_gart_set_page,
+	},
-	.irq_set = &evergreen_irq_set,
+	.ring = {
-	.irq_process = &evergreen_irq_process,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &evergreen_ring_ib_execute,
+			.emit_fence = &r600_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+		}
+	},
+	.irq = {
+		.set = &evergreen_irq_set,
+		.process = &evergreen_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &evergreen_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
-	.fence_ring_emit = &r600_fence_ring_emit,
+//		.get_backlight_level = &atombios_get_backlight_level,
-//	.cs_parse = &evergreen_cs_parse,
+	},
-	.copy_blit = &evergreen_copy_blit,
+	.copy = {
-	.copy_dma = NULL,
+		.blit = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &evergreen_hpd_init,
+//		.fini = &evergreen_hpd_fini,
+//		.sense = &evergreen_hpd_sense,
+//		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
+//		.finish = &evergreen_pm_finish,
-	.copy = &evergreen_copy_blit,
+//		.init_profile = &btc_pm_init_profile,
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
-	.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
-	.get_pcie_lanes = NULL,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
-	.set_pcie_lanes = NULL,
-	.set_clock_gating = NULL,
+//		.get_pcie_lanes = NULL,
-	.set_surface_reg = r600_set_surface_reg,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = NULL,
+	},
+	.pflip = {
+//		.pre_page_flip = &evergreen_pre_page_flip,
-	.clear_surface_reg = r600_clear_surface_reg,
+//		.page_flip = &evergreen_page_flip,
-	.bandwidth_update = &evergreen_bandwidth_update,
+//		.post_page_flip = &evergreen_post_page_flip,
+	},
+};
-	.hpd_init = &evergreen_hpd_init,
+static struct radeon_asic cayman_asic = {
+	.init = &cayman_init,
+//	.fini = &cayman_fini,
+//	.suspend = &cayman_suspend,
+//	.resume = &cayman_resume,
+	.asic_reset = &cayman_asic_reset,
-	.hpd_fini = &evergreen_hpd_fini,
+//	.vga_set_state = &r600_vga_set_state,
-	.hpd_sense = &evergreen_hpd_sense,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
-	.hpd_set_polarity = &evergreen_hpd_set_polarity,
+	.gui_idle = &r600_gui_idle,
-};
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
 	.gart = {
+		.tlb_flush = &cayman_pcie_gart_tlb_flush,
+		.set_page = &rs600_gart_set_page,
-static struct radeon_asic cayman_asic = {
+	},
-	.init = &cayman_init,
+	.vm = {
+		.init = &cayman_vm_init,
+		.fini = &cayman_vm_fini,
+		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.set_page = &cayman_vm_set_page,
+	},
+	.ring = {
-//	.fini = &evergreen_fini,
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &cayman_ring_ib_execute,
+//           .ib_parse = &evergreen_ib_parse,
-//	.suspend = &evergreen_suspend,
+			.emit_fence = &cayman_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
-//	.resume = &evergreen_resume,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
-	.cp_commit = &r600_cp_commit,
+			.vm_flush = &cayman_vm_flush,
-	.asic_reset = &cayman_asic_reset,
+		},
+		[CAYMAN_RING_TYPE_CP1_INDEX] = {
-	.vga_set_state = &r600_vga_set_state,
+			.ib_execute = &cayman_ring_ib_execute,
-	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
+//           .ib_parse = &evergreen_ib_parse,
+			.emit_fence = &cayman_fence_ring_emit,
-	.gart_set_page = &rs600_gart_set_page,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
-	.ring_test = &r600_ring_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
-	.ring_ib_execute = &evergreen_ring_ib_execute,
+			.vm_flush = &cayman_vm_flush,
+		},
+		[CAYMAN_RING_TYPE_CP2_INDEX] = {
-	.irq_set = &evergreen_irq_set,
+			.ib_execute = &cayman_ring_ib_execute,
+//           .ib_parse = &evergreen_ib_parse,
+			.emit_fence = &cayman_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+			.vm_flush = &cayman_vm_flush,
+		}
+	},
+	.irq = {
+		.set = &evergreen_irq_set,
+		.process = &evergreen_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &evergreen_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &evergreen_hpd_init,
+//		.fini = &evergreen_hpd_fini,
+//		.sense = &evergreen_hpd_sense,
+//		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
+//		.finish = &evergreen_pm_finish,
+//		.init_profile = &btc_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = NULL,
+	},
+	.pflip = {
+//		.pre_page_flip = &evergreen_pre_page_flip,
+//		.page_flip = &evergreen_page_flip,
+//		.post_page_flip = &evergreen_post_page_flip,
+	},
+};
+static struct radeon_asic trinity_asic = {
+	.init = &cayman_init,
+//	.fini = &cayman_fini,
+//	.suspend = &cayman_suspend,
+//	.resume = &cayman_resume,
+	.asic_reset = &cayman_asic_reset,
+//	.vga_set_state = &r600_vga_set_state,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
+	.gui_idle = &r600_gui_idle,
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &cayman_pcie_gart_tlb_flush,
+		.set_page = &rs600_gart_set_page,
+	},
+	.vm = {
+		.init = &cayman_vm_init,
+		.fini = &cayman_vm_fini,
+		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.set_page = &cayman_vm_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &cayman_ring_ib_execute,
+//           .ib_parse = &evergreen_ib_parse,
+			.emit_fence = &cayman_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+			.vm_flush = &cayman_vm_flush,
+		},
+		[CAYMAN_RING_TYPE_CP1_INDEX] = {
+			.ib_execute = &cayman_ring_ib_execute,
+//           .ib_parse = &evergreen_ib_parse,
+			.emit_fence = &cayman_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+			.vm_flush = &cayman_vm_flush,
+		},
+		[CAYMAN_RING_TYPE_CP2_INDEX] = {
+			.ib_execute = &cayman_ring_ib_execute,
+//           .ib_parse = &evergreen_ib_parse,
+			.emit_fence = &cayman_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = &evergreen_cs_parse,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &evergreen_gpu_is_lockup,
+			.vm_flush = &cayman_vm_flush,
+		}
+	},
+	.irq = {
+		.set = &evergreen_irq_set,
+		.process = &evergreen_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &dce6_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
+//		.set_backlight_level = &atombios_set_backlight_level,
+//		.get_backlight_level = &atombios_get_backlight_level,
+	},
+	.copy = {
+		.blit = &r600_copy_blit,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = &r600_copy_blit,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+//		.init = &evergreen_hpd_init,
+//		.fini = &evergreen_hpd_fini,
+//		.sense = &evergreen_hpd_sense,
+//		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
+//		.finish = &evergreen_pm_finish,
+//		.init_profile = &sumo_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = NULL,
+//		.set_memory_clock = NULL,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = NULL,
+	},
+	.pflip = {
+//		.pre_page_flip = &evergreen_pre_page_flip,
+//		.page_flip = &evergreen_page_flip,
+//		.post_page_flip = &evergreen_post_page_flip,
+	},
+};
+static struct radeon_asic si_asic = {
+	.init = &si_init,
+//	.fini = &si_fini,
+//	.suspend = &si_suspend,
+//	.resume = &si_resume,
+	.asic_reset = &si_asic_reset,
+//	.vga_set_state = &r600_vga_set_state,
+//	.ioctl_wait_idle = r600_ioctl_wait_idle,
+	.gui_idle = &r600_gui_idle,
+	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+	.gart = {
+		.tlb_flush = &si_pcie_gart_tlb_flush,
+		.set_page = &rs600_gart_set_page,
+	},
+	.vm = {
+		.init = &si_vm_init,
+		.fini = &si_vm_fini,
+		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.set_page = &si_vm_set_page,
+	},
+	.ring = {
+		[RADEON_RING_TYPE_GFX_INDEX] = {
+			.ib_execute = &si_ring_ib_execute,
+//           .ib_parse = &si_ib_parse,
+			.emit_fence = &si_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = NULL,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &si_gpu_is_lockup,
+			.vm_flush = &si_vm_flush,
+		},
+		[CAYMAN_RING_TYPE_CP1_INDEX] = {
+			.ib_execute = &si_ring_ib_execute,
+//           .ib_parse = &si_ib_parse,
+			.emit_fence = &si_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = NULL,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &si_gpu_is_lockup,
+			.vm_flush = &si_vm_flush,
+		},
+		[CAYMAN_RING_TYPE_CP2_INDEX] = {
+			.ib_execute = &si_ring_ib_execute,
+//           .ib_parse = &si_ib_parse,
+			.emit_fence = &si_fence_ring_emit,
+			.emit_semaphore = &r600_semaphore_ring_emit,
+//			.cs_parse = NULL,
+			.ring_test = &r600_ring_test,
+			.ib_test = &r600_ib_test,
+			.is_lockup = &si_gpu_is_lockup,
+			.vm_flush = &si_vm_flush,
+		}
+	},
+	.irq = {
+		.set = &si_irq_set,
+		.process = &si_irq_process,
+	},
+	.display = {
+		.bandwidth_update = &dce6_bandwidth_update,
+		.get_vblank_counter = &evergreen_get_vblank_counter,
+		.wait_for_vblank = &dce4_wait_for_vblank,
-	.irq_process = &evergreen_irq_process,
+//		.set_backlight_level = &atombios_set_backlight_level,
-	.fence_ring_emit = &r600_fence_ring_emit,
+//		.get_backlight_level = &atombios_get_backlight_level,
-//	.cs_parse = &evergreen_cs_parse,
+	},
-	.copy_blit = &evergreen_copy_blit,
+	.copy = {
+		.blit = NULL,
+		.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.dma = NULL,
+		.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+		.copy = NULL,
+		.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+	},
+	.surface = {
+		.set_reg = r600_set_surface_reg,
+		.clear_reg = r600_clear_surface_reg,
+	},
+	.hpd = {
+		.init = &evergreen_hpd_init,
+		.fini = &evergreen_hpd_fini,
+		.sense = &evergreen_hpd_sense,
+		.set_polarity = &evergreen_hpd_set_polarity,
+	},
+	.pm = {
+//		.misc = &evergreen_pm_misc,
+//		.prepare = &evergreen_pm_prepare,
-	.copy_dma = NULL,
+//		.finish = &evergreen_pm_finish,
+//		.init_profile = &sumo_pm_init_profile,
+//		.get_dynpm_state = &r600_pm_get_dynpm_state,
+//		.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.set_memory_clock = &radeon_atom_set_memory_clock,
+//		.get_pcie_lanes = NULL,
+//		.set_pcie_lanes = NULL,
+//		.set_clock_gating = NULL,
+	},
-	.copy = &evergreen_copy_blit,
+	.pflip = {
-	.get_engine_clock = &radeon_atom_get_engine_clock,
+//		.pre_page_flip = &evergreen_pre_page_flip,
-	.set_engine_clock = &radeon_atom_set_engine_clock,
+//		.page_flip = &evergreen_page_flip,
-	.get_memory_clock = &radeon_atom_get_memory_clock,
+//		.post_page_flip = &evergreen_post_page_flip,
 	case CHIP_R423:
 	case CHIP_RV410:
 		rdev->asic = &r420_asic;
 		/* handle macs */
 		if (rdev->bios == NULL) {
-			rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
+			rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
-			rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
+			rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
-			rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
+			rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
-			rdev->asic->set_memory_clock = NULL;
+			rdev->asic->pm.set_memory_clock = NULL;
+			rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
+		}
 		break;
 	case CHIP_RS400:
 	case CHIP_RS480:
 		rdev->asic = &rs400_asic;
 	case CHIP_CAYMAN:
 		rdev->asic = &cayman_asic;
 		/* set num crtcs */
 		rdev->num_crtc = 6;
 		break;
+	case CHIP_ARUBA:
+		rdev->asic = &trinity_asic;
+		/* set num crtcs */
+		rdev->num_crtc = 4;
+		break;
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+		rdev->asic = &si_asic;
+		/* set num crtcs */
+		rdev->num_crtc = 6;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
+	}
 	if (rdev->flags & RADEON_IS_IGP) {
-		rdev->asic->get_memory_clock = NULL;
+		rdev->asic->pm.get_memory_clock = NULL;
-		rdev->asic->set_memory_clock = NULL;
+		rdev->asic->pm.set_memory_clock = NULL;
+	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 2160 → 2997