Rev 2007 | Rev 2997 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 2007 | Rev 2160 | ||
|---|---|---|---|
| Line 318... | Line 318... | ||
| 318 | .hpd_init = &r100_hpd_init, |
318 | .hpd_init = &r100_hpd_init, |
| 319 | .hpd_fini = &r100_hpd_fini, |
319 | .hpd_fini = &r100_hpd_fini, |
| 320 | .hpd_sense = &r100_hpd_sense, |
320 | .hpd_sense = &r100_hpd_sense, |
| 321 | .hpd_set_polarity = &r100_hpd_set_polarity, |
321 | .hpd_set_polarity = &r100_hpd_set_polarity, |
| 322 | .ioctl_wait_idle = NULL, |
322 | .ioctl_wait_idle = NULL, |
| - | 323 | .gui_idle = &r100_gui_idle, |
|
| 323 | }; |
324 | }; |
| Line 324... | Line 325... | ||
| 324 | 325 | ||
| 325 | static struct radeon_asic rs400_asic = { |
326 | static struct radeon_asic rs400_asic = { |
| 326 | .init = &rs400_init, |
327 | .init = &rs400_init, |
| Line 356... | Line 357... | ||
| 356 | .hpd_init = &r100_hpd_init, |
357 | .hpd_init = &r100_hpd_init, |
| 357 | .hpd_fini = &r100_hpd_fini, |
358 | .hpd_fini = &r100_hpd_fini, |
| 358 | .hpd_sense = &r100_hpd_sense, |
359 | .hpd_sense = &r100_hpd_sense, |
| 359 | .hpd_set_polarity = &r100_hpd_set_polarity, |
360 | .hpd_set_polarity = &r100_hpd_set_polarity, |
| 360 | .ioctl_wait_idle = NULL, |
361 | .ioctl_wait_idle = NULL, |
| - | 362 | .gui_idle = &r100_gui_idle, |
|
| 361 | }; |
363 | }; |
| Line 362... | Line 364... | ||
| 362 | 364 | ||
| 363 | static struct radeon_asic rs600_asic = { |
365 | static struct radeon_asic rs600_asic = { |
| 364 | .init = &rs600_init, |
366 | .init = &rs600_init, |
| Line 394... | Line 396... | ||
| 394 | .hpd_init = &rs600_hpd_init, |
396 | .hpd_init = &rs600_hpd_init, |
| 395 | .hpd_fini = &rs600_hpd_fini, |
397 | .hpd_fini = &rs600_hpd_fini, |
| 396 | .hpd_sense = &rs600_hpd_sense, |
398 | .hpd_sense = &rs600_hpd_sense, |
| 397 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
399 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
| 398 | .ioctl_wait_idle = NULL, |
400 | .ioctl_wait_idle = NULL, |
| - | 401 | .gui_idle = &r100_gui_idle, |
|
| 399 | }; |
402 | }; |
| Line 400... | Line 403... | ||
| 400 | 403 | ||
| 401 | static struct radeon_asic rs690_asic = { |
404 | static struct radeon_asic rs690_asic = { |
| 402 | .init = &rs690_init, |
405 | .init = &rs690_init, |
| Line 432... | Line 435... | ||
| 432 | .hpd_init = &rs600_hpd_init, |
435 | .hpd_init = &rs600_hpd_init, |
| 433 | .hpd_fini = &rs600_hpd_fini, |
436 | .hpd_fini = &rs600_hpd_fini, |
| 434 | .hpd_sense = &rs600_hpd_sense, |
437 | .hpd_sense = &rs600_hpd_sense, |
| 435 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
438 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
| 436 | .ioctl_wait_idle = NULL, |
439 | .ioctl_wait_idle = NULL, |
| - | 440 | .gui_idle = &r100_gui_idle, |
|
| 437 | }; |
441 | }; |
| Line 438... | Line 442... | ||
| 438 | 442 | ||
| 439 | static struct radeon_asic rv515_asic = { |
443 | static struct radeon_asic rv515_asic = { |
| 440 | .init = &rv515_init, |
444 | .init = &rv515_init, |
| Line 470... | Line 474... | ||
| 470 | .hpd_init = &rs600_hpd_init, |
474 | .hpd_init = &rs600_hpd_init, |
| 471 | .hpd_fini = &rs600_hpd_fini, |
475 | .hpd_fini = &rs600_hpd_fini, |
| 472 | .hpd_sense = &rs600_hpd_sense, |
476 | .hpd_sense = &rs600_hpd_sense, |
| 473 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
477 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
| 474 | .ioctl_wait_idle = NULL, |
478 | .ioctl_wait_idle = NULL, |
| - | 479 | .gui_idle = &r100_gui_idle, |
|
| 475 | }; |
480 | }; |
| Line 476... | Line 481... | ||
| 476 | 481 | ||
| 477 | static struct radeon_asic r520_asic = { |
482 | static struct radeon_asic r520_asic = { |
| 478 | .init = &r520_init, |
483 | .init = &r520_init, |
| Line 508... | Line 513... | ||
| 508 | .hpd_init = &rs600_hpd_init, |
513 | .hpd_init = &rs600_hpd_init, |
| 509 | .hpd_fini = &rs600_hpd_fini, |
514 | .hpd_fini = &rs600_hpd_fini, |
| 510 | .hpd_sense = &rs600_hpd_sense, |
515 | .hpd_sense = &rs600_hpd_sense, |
| 511 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
516 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
| 512 | .ioctl_wait_idle = NULL, |
517 | .ioctl_wait_idle = NULL, |
| - | 518 | .gui_idle = &r100_gui_idle, |
|
| 513 | }; |
519 | }; |
| Line 514... | Line 520... | ||
| 514 | 520 | ||
| 515 | static struct radeon_asic r600_asic = { |
521 | static struct radeon_asic r600_asic = { |
| 516 | .init = &r600_init, |
522 | .init = &r600_init, |
| Line 527... | Line 533... | ||
| 527 | .irq_set = &r600_irq_set, |
533 | .irq_set = &r600_irq_set, |
| 528 | .irq_process = &r600_irq_process, |
534 | .irq_process = &r600_irq_process, |
| 529 | .fence_ring_emit = &r600_fence_ring_emit, |
535 | .fence_ring_emit = &r600_fence_ring_emit, |
| 530 | // .cs_parse = &r600_cs_parse, |
536 | // .cs_parse = &r600_cs_parse, |
| 531 | .copy_blit = &r600_copy_blit, |
537 | .copy_blit = &r600_copy_blit, |
| 532 | .copy_dma = &r600_copy_blit, |
538 | .copy_dma = NULL, |
| 533 | .copy = &r600_copy_blit, |
539 | .copy = &r600_copy_blit, |
| 534 | .get_engine_clock = &radeon_atom_get_engine_clock, |
540 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 535 | .set_engine_clock = &radeon_atom_set_engine_clock, |
541 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 536 | .get_memory_clock = &radeon_atom_get_memory_clock, |
542 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 537 | .set_memory_clock = &radeon_atom_set_memory_clock, |
543 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 564... | Line 570... | ||
| 564 | .irq_set = &r600_irq_set, |
570 | .irq_set = &r600_irq_set, |
| 565 | .irq_process = &r600_irq_process, |
571 | .irq_process = &r600_irq_process, |
| 566 | .fence_ring_emit = &r600_fence_ring_emit, |
572 | .fence_ring_emit = &r600_fence_ring_emit, |
| 567 | // .cs_parse = &r600_cs_parse, |
573 | // .cs_parse = &r600_cs_parse, |
| 568 | .copy_blit = &r600_copy_blit, |
574 | .copy_blit = &r600_copy_blit, |
| 569 | .copy_dma = &r600_copy_blit, |
575 | .copy_dma = NULL, |
| 570 | .copy = &r600_copy_blit, |
576 | .copy = &r600_copy_blit, |
| 571 | .get_engine_clock = &radeon_atom_get_engine_clock, |
577 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 572 | .set_engine_clock = &radeon_atom_set_engine_clock, |
578 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 573 | .get_memory_clock = NULL, |
579 | .get_memory_clock = NULL, |
| 574 | .set_memory_clock = NULL, |
580 | .set_memory_clock = NULL, |
| Line 599... | Line 605... | ||
| 599 | .irq_set = &r600_irq_set, |
605 | .irq_set = &r600_irq_set, |
| 600 | .irq_process = &r600_irq_process, |
606 | .irq_process = &r600_irq_process, |
| 601 | .fence_ring_emit = &r600_fence_ring_emit, |
607 | .fence_ring_emit = &r600_fence_ring_emit, |
| 602 | // .cs_parse = &r600_cs_parse, |
608 | // .cs_parse = &r600_cs_parse, |
| 603 | .copy_blit = &r600_copy_blit, |
609 | .copy_blit = &r600_copy_blit, |
| 604 | .copy_dma = &r600_copy_blit, |
610 | .copy_dma = NULL, |
| 605 | .copy = &r600_copy_blit, |
611 | .copy = &r600_copy_blit, |
| 606 | .get_engine_clock = &radeon_atom_get_engine_clock, |
612 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 607 | .set_engine_clock = &radeon_atom_set_engine_clock, |
613 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 608 | .get_memory_clock = &radeon_atom_get_memory_clock, |
614 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 609 | .set_memory_clock = &radeon_atom_set_memory_clock, |
615 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 634... | Line 640... | ||
| 634 | .irq_set = &evergreen_irq_set, |
640 | .irq_set = &evergreen_irq_set, |
| 635 | .irq_process = &evergreen_irq_process, |
641 | .irq_process = &evergreen_irq_process, |
| 636 | .fence_ring_emit = &r600_fence_ring_emit, |
642 | .fence_ring_emit = &r600_fence_ring_emit, |
| 637 | // .cs_parse = &evergreen_cs_parse, |
643 | // .cs_parse = &evergreen_cs_parse, |
| 638 | .copy_blit = &evergreen_copy_blit, |
644 | .copy_blit = &evergreen_copy_blit, |
| 639 | .copy_dma = &evergreen_copy_blit, |
645 | .copy_dma = NULL, |
| 640 | .copy = &evergreen_copy_blit, |
646 | .copy = &evergreen_copy_blit, |
| 641 | .get_engine_clock = &radeon_atom_get_engine_clock, |
647 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 642 | .set_engine_clock = &radeon_atom_set_engine_clock, |
648 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 643 | .get_memory_clock = &radeon_atom_get_memory_clock, |
649 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 644 | .set_memory_clock = &radeon_atom_set_memory_clock, |
650 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 670... | Line 676... | ||
| 670 | .irq_set = &evergreen_irq_set, |
676 | .irq_set = &evergreen_irq_set, |
| 671 | .irq_process = &evergreen_irq_process, |
677 | .irq_process = &evergreen_irq_process, |
| 672 | .fence_ring_emit = &r600_fence_ring_emit, |
678 | .fence_ring_emit = &r600_fence_ring_emit, |
| 673 | // .cs_parse = &r600_cs_parse, |
679 | // .cs_parse = &r600_cs_parse, |
| 674 | .copy_blit = &evergreen_copy_blit, |
680 | .copy_blit = &evergreen_copy_blit, |
| 675 | .copy_dma = &evergreen_copy_blit, |
681 | .copy_dma = NULL, |
| 676 | .copy = &evergreen_copy_blit, |
682 | .copy = &evergreen_copy_blit, |
| 677 | .get_engine_clock = &radeon_atom_get_engine_clock, |
683 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 678 | .set_engine_clock = &radeon_atom_set_engine_clock, |
684 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 679 | .get_memory_clock = NULL, |
685 | .get_memory_clock = NULL, |
| 680 | .set_memory_clock = NULL, |
686 | .set_memory_clock = NULL, |
| Line 705... | Line 711... | ||
| 705 | .irq_set = &evergreen_irq_set, |
711 | .irq_set = &evergreen_irq_set, |
| 706 | .irq_process = &evergreen_irq_process, |
712 | .irq_process = &evergreen_irq_process, |
| 707 | .fence_ring_emit = &r600_fence_ring_emit, |
713 | .fence_ring_emit = &r600_fence_ring_emit, |
| 708 | // .cs_parse = &evergreen_cs_parse, |
714 | // .cs_parse = &evergreen_cs_parse, |
| 709 | .copy_blit = &evergreen_copy_blit, |
715 | .copy_blit = &evergreen_copy_blit, |
| 710 | .copy_dma = &evergreen_copy_blit, |
716 | .copy_dma = NULL, |
| 711 | .copy = &evergreen_copy_blit, |
717 | .copy = &evergreen_copy_blit, |
| 712 | .get_engine_clock = &radeon_atom_get_engine_clock, |
718 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 713 | .set_engine_clock = &radeon_atom_set_engine_clock, |
719 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 714 | .get_memory_clock = &radeon_atom_get_memory_clock, |
720 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 715 | .set_memory_clock = &radeon_atom_set_memory_clock, |
721 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| Line 740... | Line 746... | ||
| 740 | .irq_set = &evergreen_irq_set, |
746 | .irq_set = &evergreen_irq_set, |
| 741 | .irq_process = &evergreen_irq_process, |
747 | .irq_process = &evergreen_irq_process, |
| 742 | .fence_ring_emit = &r600_fence_ring_emit, |
748 | .fence_ring_emit = &r600_fence_ring_emit, |
| 743 | // .cs_parse = &evergreen_cs_parse, |
749 | // .cs_parse = &evergreen_cs_parse, |
| 744 | .copy_blit = &evergreen_copy_blit, |
750 | .copy_blit = &evergreen_copy_blit, |
| 745 | .copy_dma = &evergreen_copy_blit, |
751 | .copy_dma = NULL, |
| 746 | .copy = &evergreen_copy_blit, |
752 | .copy = &evergreen_copy_blit, |
| 747 | .get_engine_clock = &radeon_atom_get_engine_clock, |
753 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 748 | .set_engine_clock = &radeon_atom_set_engine_clock, |
754 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 749 | .get_memory_clock = &radeon_atom_get_memory_clock, |
755 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 750 | .set_memory_clock = &radeon_atom_set_memory_clock, |
756 | .set_memory_clock = &radeon_atom_set_memory_clock, |