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| Rev 2004 | Rev 2005 | ||
|---|---|---|---|
| Line 132... | Line 132... | ||
| 132 | .init = &r100_init, |
132 | .init = &r100_init, |
| 133 | // .fini = &r100_fini, |
133 | // .fini = &r100_fini, |
| 134 | // .suspend = &r100_suspend, |
134 | // .suspend = &r100_suspend, |
| 135 | // .resume = &r100_resume, |
135 | // .resume = &r100_resume, |
| 136 | // .vga_set_state = &r100_vga_set_state, |
136 | // .vga_set_state = &r100_vga_set_state, |
| - | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
|
| 137 | .asic_reset = &r100_asic_reset, |
138 | .asic_reset = &r100_asic_reset, |
| 138 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 139 | .gart_set_page = &r100_pci_gart_set_page, |
140 | .gart_set_page = &r100_pci_gart_set_page, |
| 140 | .cp_commit = &r100_cp_commit, |
141 | .cp_commit = &r100_cp_commit, |
| 141 | .ring_start = &r100_ring_start, |
142 | .ring_start = &r100_ring_start, |
| 142 | .ring_test = &r100_ring_test, |
143 | .ring_test = &r100_ring_test, |
| 143 | // .ring_ib_execute = &r100_ring_ib_execute, |
144 | .ring_ib_execute = &r100_ring_ib_execute, |
| 144 | // .irq_set = &r100_irq_set, |
145 | .irq_set = &r100_irq_set, |
| 145 | // .irq_process = &r100_irq_process, |
146 | .irq_process = &r100_irq_process, |
| 146 | // .get_vblank_counter = &r100_get_vblank_counter, |
147 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 147 | .fence_ring_emit = &r100_fence_ring_emit, |
148 | .fence_ring_emit = &r100_fence_ring_emit, |
| 148 | // .cs_parse = &r100_cs_parse, |
149 | // .cs_parse = &r100_cs_parse, |
| 149 | // .copy_blit = &r100_copy_blit, |
150 | .copy_blit = &r100_copy_blit, |
| 150 | // .copy_dma = NULL, |
151 | .copy_dma = NULL, |
| 151 | // .copy = &r100_copy_blit, |
152 | .copy = &r100_copy_blit, |
| 152 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
153 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 153 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
154 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 154 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
155 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 155 | .set_memory_clock = NULL, |
156 | .set_memory_clock = NULL, |
| 156 | .get_pcie_lanes = NULL, |
157 | .get_pcie_lanes = NULL, |
| Line 170... | Line 171... | ||
| 170 | .init = &r100_init, |
171 | .init = &r100_init, |
| 171 | // .fini = &r100_fini, |
172 | // .fini = &r100_fini, |
| 172 | // .suspend = &r100_suspend, |
173 | // .suspend = &r100_suspend, |
| 173 | // .resume = &r100_resume, |
174 | // .resume = &r100_resume, |
| 174 | // .vga_set_state = &r100_vga_set_state, |
175 | // .vga_set_state = &r100_vga_set_state, |
| - | 176 | .gpu_is_lockup = &r100_gpu_is_lockup, |
|
| 175 | .asic_reset = &r100_asic_reset, |
177 | .asic_reset = &r100_asic_reset, |
| 176 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
178 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 177 | .gart_set_page = &r100_pci_gart_set_page, |
179 | .gart_set_page = &r100_pci_gart_set_page, |
| 178 | .cp_commit = &r100_cp_commit, |
180 | .cp_commit = &r100_cp_commit, |
| 179 | .ring_start = &r100_ring_start, |
181 | .ring_start = &r100_ring_start, |
| 180 | .ring_test = &r100_ring_test, |
182 | .ring_test = &r100_ring_test, |
| 181 | // .ring_ib_execute = &r100_ring_ib_execute, |
183 | .ring_ib_execute = &r100_ring_ib_execute, |
| 182 | // .irq_set = &r100_irq_set, |
184 | .irq_set = &r100_irq_set, |
| 183 | // .irq_process = &r100_irq_process, |
185 | .irq_process = &r100_irq_process, |
| 184 | // .get_vblank_counter = &r100_get_vblank_counter, |
186 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 185 | .fence_ring_emit = &r100_fence_ring_emit, |
187 | .fence_ring_emit = &r100_fence_ring_emit, |
| 186 | // .cs_parse = &r100_cs_parse, |
188 | // .cs_parse = &r100_cs_parse, |
| 187 | // .copy_blit = &r100_copy_blit, |
189 | .copy_blit = &r100_copy_blit, |
| 188 | // .copy_dma = NULL, |
190 | .copy_dma = &r200_copy_dma, |
| 189 | // .copy = &r100_copy_blit, |
191 | .copy = &r100_copy_blit, |
| 190 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
192 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 191 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
193 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 192 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
194 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 193 | .set_memory_clock = NULL, |
195 | .set_memory_clock = NULL, |
| 194 | .set_pcie_lanes = NULL, |
196 | .set_pcie_lanes = NULL, |
| Line 213... | Line 215... | ||
| 213 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
215 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 214 | .gart_set_page = &r100_pci_gart_set_page, |
216 | .gart_set_page = &r100_pci_gart_set_page, |
| 215 | .cp_commit = &r100_cp_commit, |
217 | .cp_commit = &r100_cp_commit, |
| 216 | .ring_start = &r300_ring_start, |
218 | .ring_start = &r300_ring_start, |
| 217 | .ring_test = &r100_ring_test, |
219 | .ring_test = &r100_ring_test, |
| 218 | // .ring_ib_execute = &r100_ring_ib_execute, |
220 | .ring_ib_execute = &r100_ring_ib_execute, |
| 219 | // .irq_set = &r100_irq_set, |
221 | .irq_set = &r100_irq_set, |
| 220 | // .irq_process = &r100_irq_process, |
222 | .irq_process = &r100_irq_process, |
| 221 | // .get_vblank_counter = &r100_get_vblank_counter, |
223 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 222 | .fence_ring_emit = &r300_fence_ring_emit, |
224 | .fence_ring_emit = &r300_fence_ring_emit, |
| 223 | // .cs_parse = &r300_cs_parse, |
225 | // .cs_parse = &r300_cs_parse, |
| 224 | // .copy_blit = &r100_copy_blit, |
226 | .copy_blit = &r100_copy_blit, |
| 225 | // .copy_dma = &r300_copy_dma, |
227 | .copy_dma = &r200_copy_dma, |
| 226 | // .copy = &r100_copy_blit, |
228 | .copy = &r100_copy_blit, |
| 227 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
229 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 228 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
230 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 229 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
231 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 230 | .set_memory_clock = NULL, |
232 | .set_memory_clock = NULL, |
| 231 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
233 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| Line 251... | Line 253... | ||
| 251 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
253 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 252 | .gart_set_page = &rv370_pcie_gart_set_page, |
254 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 253 | .cp_commit = &r100_cp_commit, |
255 | .cp_commit = &r100_cp_commit, |
| 254 | .ring_start = &r300_ring_start, |
256 | .ring_start = &r300_ring_start, |
| 255 | .ring_test = &r100_ring_test, |
257 | .ring_test = &r100_ring_test, |
| 256 | // .ring_ib_execute = &r100_ring_ib_execute, |
258 | .ring_ib_execute = &r100_ring_ib_execute, |
| 257 | // .irq_set = &r100_irq_set, |
259 | .irq_set = &r100_irq_set, |
| 258 | // .irq_process = &r100_irq_process, |
260 | .irq_process = &r100_irq_process, |
| 259 | // .get_vblank_counter = &r100_get_vblank_counter, |
261 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 260 | .fence_ring_emit = &r300_fence_ring_emit, |
262 | .fence_ring_emit = &r300_fence_ring_emit, |
| 261 | // .cs_parse = &r300_cs_parse, |
263 | // .cs_parse = &r300_cs_parse, |
| 262 | // .copy_blit = &r100_copy_blit, |
264 | .copy_blit = &r100_copy_blit, |
| 263 | // .copy_dma = &r300_copy_dma, |
265 | .copy_dma = &r200_copy_dma, |
| 264 | // .copy = &r100_copy_blit, |
266 | .copy = &r100_copy_blit, |
| 265 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
267 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 266 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
268 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 267 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
269 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 268 | .set_memory_clock = NULL, |
270 | .set_memory_clock = NULL, |
| 269 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
271 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| Line 288... | Line 290... | ||
| 288 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
290 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 289 | .gart_set_page = &rv370_pcie_gart_set_page, |
291 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 290 | .cp_commit = &r100_cp_commit, |
292 | .cp_commit = &r100_cp_commit, |
| 291 | .ring_start = &r300_ring_start, |
293 | .ring_start = &r300_ring_start, |
| 292 | .ring_test = &r100_ring_test, |
294 | .ring_test = &r100_ring_test, |
| 293 | // .ring_ib_execute = &r100_ring_ib_execute, |
295 | .ring_ib_execute = &r100_ring_ib_execute, |
| 294 | // .irq_set = &r100_irq_set, |
296 | .irq_set = &r100_irq_set, |
| 295 | // .irq_process = &r100_irq_process, |
297 | .irq_process = &r100_irq_process, |
| 296 | // .get_vblank_counter = &r100_get_vblank_counter, |
298 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 297 | .fence_ring_emit = &r300_fence_ring_emit, |
299 | .fence_ring_emit = &r300_fence_ring_emit, |
| 298 | // .cs_parse = &r300_cs_parse, |
300 | // .cs_parse = &r300_cs_parse, |
| 299 | // .copy_blit = &r100_copy_blit, |
301 | .copy_blit = &r100_copy_blit, |
| 300 | // .copy_dma = &r300_copy_dma, |
302 | .copy_dma = &r200_copy_dma, |
| 301 | // .copy = &r100_copy_blit, |
303 | .copy = &r100_copy_blit, |
| 302 | .get_engine_clock = &radeon_atom_get_engine_clock, |
304 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 303 | .set_engine_clock = &radeon_atom_set_engine_clock, |
305 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 304 | .get_memory_clock = &radeon_atom_get_memory_clock, |
306 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 305 | .set_memory_clock = &radeon_atom_set_memory_clock, |
307 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 306 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
308 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| Line 326... | Line 328... | ||
| 326 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
328 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 327 | .gart_set_page = &rs400_gart_set_page, |
329 | .gart_set_page = &rs400_gart_set_page, |
| 328 | .cp_commit = &r100_cp_commit, |
330 | .cp_commit = &r100_cp_commit, |
| 329 | .ring_start = &r300_ring_start, |
331 | .ring_start = &r300_ring_start, |
| 330 | .ring_test = &r100_ring_test, |
332 | .ring_test = &r100_ring_test, |
| 331 | // .ring_ib_execute = &r100_ring_ib_execute, |
333 | .ring_ib_execute = &r100_ring_ib_execute, |
| 332 | // .irq_set = &r100_irq_set, |
334 | .irq_set = &r100_irq_set, |
| 333 | // .irq_process = &r100_irq_process, |
335 | .irq_process = &r100_irq_process, |
| 334 | // .get_vblank_counter = &r100_get_vblank_counter, |
336 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 335 | .fence_ring_emit = &r300_fence_ring_emit, |
337 | .fence_ring_emit = &r300_fence_ring_emit, |
| 336 | // .cs_parse = &r300_cs_parse, |
338 | // .cs_parse = &r300_cs_parse, |
| 337 | // .copy_blit = &r100_copy_blit, |
339 | .copy_blit = &r100_copy_blit, |
| 338 | // .copy_dma = &r300_copy_dma, |
340 | .copy_dma = &r200_copy_dma, |
| 339 | // .copy = &r100_copy_blit, |
341 | .copy = &r100_copy_blit, |
| 340 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
342 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 341 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
343 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 342 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
344 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 343 | .set_memory_clock = NULL, |
345 | .set_memory_clock = NULL, |
| 344 | .get_pcie_lanes = NULL, |
346 | .get_pcie_lanes = NULL, |
| Line 364... | Line 366... | ||
| 364 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
366 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
| 365 | .gart_set_page = &rs600_gart_set_page, |
367 | .gart_set_page = &rs600_gart_set_page, |
| 366 | .cp_commit = &r100_cp_commit, |
368 | .cp_commit = &r100_cp_commit, |
| 367 | .ring_start = &r300_ring_start, |
369 | .ring_start = &r300_ring_start, |
| 368 | .ring_test = &r100_ring_test, |
370 | .ring_test = &r100_ring_test, |
| 369 | // .ring_ib_execute = &r100_ring_ib_execute, |
371 | .ring_ib_execute = &r100_ring_ib_execute, |
| 370 | // .irq_set = &rs600_irq_set, |
372 | .irq_set = &rs600_irq_set, |
| 371 | // .irq_process = &rs600_irq_process, |
373 | .irq_process = &rs600_irq_process, |
| 372 | // .get_vblank_counter = &rs600_get_vblank_counter, |
374 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 373 | .fence_ring_emit = &r300_fence_ring_emit, |
375 | .fence_ring_emit = &r300_fence_ring_emit, |
| 374 | // .cs_parse = &r300_cs_parse, |
376 | // .cs_parse = &r300_cs_parse, |
| 375 | // .copy_blit = &r100_copy_blit, |
377 | .copy_blit = &r100_copy_blit, |
| 376 | // .copy_dma = &r300_copy_dma, |
378 | .copy_dma = &r200_copy_dma, |
| 377 | // .copy = &r100_copy_blit, |
379 | .copy = &r100_copy_blit, |
| 378 | .get_engine_clock = &radeon_atom_get_engine_clock, |
380 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 379 | .set_engine_clock = &radeon_atom_set_engine_clock, |
381 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 380 | .get_memory_clock = &radeon_atom_get_memory_clock, |
382 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 381 | .set_memory_clock = &radeon_atom_set_memory_clock, |
383 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 382 | .get_pcie_lanes = NULL, |
384 | .get_pcie_lanes = NULL, |
| Line 402... | Line 404... | ||
| 402 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
404 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 403 | .gart_set_page = &rs400_gart_set_page, |
405 | .gart_set_page = &rs400_gart_set_page, |
| 404 | .cp_commit = &r100_cp_commit, |
406 | .cp_commit = &r100_cp_commit, |
| 405 | .ring_start = &r300_ring_start, |
407 | .ring_start = &r300_ring_start, |
| 406 | .ring_test = &r100_ring_test, |
408 | .ring_test = &r100_ring_test, |
| 407 | // .ring_ib_execute = &r100_ring_ib_execute, |
409 | .ring_ib_execute = &r100_ring_ib_execute, |
| 408 | // .irq_set = &rs600_irq_set, |
410 | .irq_set = &rs600_irq_set, |
| 409 | // .irq_process = &rs600_irq_process, |
411 | .irq_process = &rs600_irq_process, |
| 410 | // .get_vblank_counter = &rs600_get_vblank_counter, |
412 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 411 | .fence_ring_emit = &r300_fence_ring_emit, |
413 | .fence_ring_emit = &r300_fence_ring_emit, |
| 412 | // .cs_parse = &r300_cs_parse, |
414 | // .cs_parse = &r300_cs_parse, |
| 413 | // .copy_blit = &r100_copy_blit, |
415 | .copy_blit = &r100_copy_blit, |
| 414 | // .copy_dma = &r300_copy_dma, |
416 | .copy_dma = &r200_copy_dma, |
| 415 | // .copy = &r300_copy_dma, |
417 | .copy = &r200_copy_dma, |
| 416 | .get_engine_clock = &radeon_atom_get_engine_clock, |
418 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 417 | .set_engine_clock = &radeon_atom_set_engine_clock, |
419 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 418 | .get_memory_clock = &radeon_atom_get_memory_clock, |
420 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 419 | .set_memory_clock = &radeon_atom_set_memory_clock, |
421 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 420 | .get_pcie_lanes = NULL, |
422 | .get_pcie_lanes = NULL, |
| Line 440... | Line 442... | ||
| 440 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
442 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 441 | .gart_set_page = &rv370_pcie_gart_set_page, |
443 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 442 | .cp_commit = &r100_cp_commit, |
444 | .cp_commit = &r100_cp_commit, |
| 443 | .ring_start = &rv515_ring_start, |
445 | .ring_start = &rv515_ring_start, |
| 444 | .ring_test = &r100_ring_test, |
446 | .ring_test = &r100_ring_test, |
| 445 | // .ring_ib_execute = &r100_ring_ib_execute, |
447 | .ring_ib_execute = &r100_ring_ib_execute, |
| 446 | // .irq_set = &rs600_irq_set, |
448 | .irq_set = &rs600_irq_set, |
| 447 | // .irq_process = &rs600_irq_process, |
449 | .irq_process = &rs600_irq_process, |
| 448 | // .get_vblank_counter = &rs600_get_vblank_counter, |
450 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 449 | .fence_ring_emit = &r300_fence_ring_emit, |
451 | .fence_ring_emit = &r300_fence_ring_emit, |
| 450 | // .cs_parse = &r300_cs_parse, |
452 | // .cs_parse = &r300_cs_parse, |
| 451 | // .copy_blit = &r100_copy_blit, |
453 | .copy_blit = &r100_copy_blit, |
| 452 | // .copy_dma = &r300_copy_dma, |
454 | .copy_dma = &r200_copy_dma, |
| 453 | // .copy = &r100_copy_blit, |
455 | .copy = &r100_copy_blit, |
| 454 | .get_engine_clock = &radeon_atom_get_engine_clock, |
456 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 455 | .set_engine_clock = &radeon_atom_set_engine_clock, |
457 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 456 | .get_memory_clock = &radeon_atom_get_memory_clock, |
458 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 457 | .set_memory_clock = &radeon_atom_set_memory_clock, |
459 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 458 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
460 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| Line 478... | Line 480... | ||
| 478 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
480 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 479 | .gart_set_page = &rv370_pcie_gart_set_page, |
481 | .gart_set_page = &rv370_pcie_gart_set_page, |
| 480 | .cp_commit = &r100_cp_commit, |
482 | .cp_commit = &r100_cp_commit, |
| 481 | .ring_start = &rv515_ring_start, |
483 | .ring_start = &rv515_ring_start, |
| 482 | .ring_test = &r100_ring_test, |
484 | .ring_test = &r100_ring_test, |
| 483 | // .ring_ib_execute = &r100_ring_ib_execute, |
485 | .ring_ib_execute = &r100_ring_ib_execute, |
| 484 | // .irq_set = &rs600_irq_set, |
486 | .irq_set = &rs600_irq_set, |
| 485 | // .irq_process = &rs600_irq_process, |
487 | .irq_process = &rs600_irq_process, |
| 486 | // .get_vblank_counter = &rs600_get_vblank_counter, |
488 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 487 | .fence_ring_emit = &r300_fence_ring_emit, |
489 | .fence_ring_emit = &r300_fence_ring_emit, |
| 488 | // .cs_parse = &r300_cs_parse, |
490 | // .cs_parse = &r300_cs_parse, |
| 489 | // .copy_blit = &r100_copy_blit, |
491 | .copy_blit = &r100_copy_blit, |
| 490 | // .copy_dma = &r300_copy_dma, |
492 | .copy_dma = &r200_copy_dma, |
| 491 | // .copy = &r100_copy_blit, |
493 | .copy = &r100_copy_blit, |
| 492 | .get_engine_clock = &radeon_atom_get_engine_clock, |
494 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 493 | .set_engine_clock = &radeon_atom_set_engine_clock, |
495 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 494 | .get_memory_clock = &radeon_atom_get_memory_clock, |
496 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 495 | .set_memory_clock = &radeon_atom_set_memory_clock, |
497 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 496 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
498 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| Line 515... | Line 517... | ||
| 515 | .vga_set_state = &r600_vga_set_state, |
517 | .vga_set_state = &r600_vga_set_state, |
| 516 | .asic_reset = &r600_asic_reset, |
518 | .asic_reset = &r600_asic_reset, |
| 517 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
519 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 518 | .gart_set_page = &rs600_gart_set_page, |
520 | .gart_set_page = &rs600_gart_set_page, |
| 519 | .ring_test = &r600_ring_test, |
521 | .ring_test = &r600_ring_test, |
| 520 | // .ring_ib_execute = &r600_ring_ib_execute, |
522 | .ring_ib_execute = &r600_ring_ib_execute, |
| 521 | .irq_set = &r600_irq_set, |
523 | .irq_set = &r600_irq_set, |
| 522 | .irq_process = &r600_irq_process, |
524 | .irq_process = &r600_irq_process, |
| 523 | .fence_ring_emit = &r600_fence_ring_emit, |
525 | .fence_ring_emit = &r600_fence_ring_emit, |
| 524 | // .cs_parse = &r600_cs_parse, |
526 | // .cs_parse = &r600_cs_parse, |
| 525 | // .copy_blit = &r600_copy_blit, |
527 | .copy_blit = &r600_copy_blit, |
| 526 | // .copy_dma = &r600_copy_blit, |
528 | .copy_dma = &r600_copy_blit, |
| 527 | // .copy = &r600_copy_blit, |
529 | .copy = &r600_copy_blit, |
| 528 | .get_engine_clock = &radeon_atom_get_engine_clock, |
530 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 529 | .set_engine_clock = &radeon_atom_set_engine_clock, |
531 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 530 | .get_memory_clock = &radeon_atom_get_memory_clock, |
532 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 531 | .set_memory_clock = &radeon_atom_set_memory_clock, |
533 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 532 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
534 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 533 | .set_pcie_lanes = NULL, |
535 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 534 | .set_clock_gating = NULL, |
536 | .set_clock_gating = NULL, |
| 535 | .set_surface_reg = r600_set_surface_reg, |
537 | .set_surface_reg = r600_set_surface_reg, |
| 536 | .clear_surface_reg = r600_clear_surface_reg, |
538 | .clear_surface_reg = r600_clear_surface_reg, |
| 537 | .bandwidth_update = &rv515_bandwidth_update, |
539 | .bandwidth_update = &rv515_bandwidth_update, |
| 538 | .hpd_init = &r600_hpd_init, |
540 | .hpd_init = &r600_hpd_init, |
| Line 552... | Line 554... | ||
| 552 | .vga_set_state = &r600_vga_set_state, |
554 | .vga_set_state = &r600_vga_set_state, |
| 553 | .asic_reset = &r600_asic_reset, |
555 | .asic_reset = &r600_asic_reset, |
| 554 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
556 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 555 | .gart_set_page = &rs600_gart_set_page, |
557 | .gart_set_page = &rs600_gart_set_page, |
| 556 | .ring_test = &r600_ring_test, |
558 | .ring_test = &r600_ring_test, |
| 557 | // .ring_ib_execute = &r600_ring_ib_execute, |
559 | .ring_ib_execute = &r600_ring_ib_execute, |
| 558 | .irq_set = &r600_irq_set, |
560 | .irq_set = &r600_irq_set, |
| 559 | .irq_process = &r600_irq_process, |
561 | .irq_process = &r600_irq_process, |
| 560 | .fence_ring_emit = &r600_fence_ring_emit, |
562 | .fence_ring_emit = &r600_fence_ring_emit, |
| 561 | // .cs_parse = &r600_cs_parse, |
563 | // .cs_parse = &r600_cs_parse, |
| 562 | // .copy_blit = &r600_copy_blit, |
564 | .copy_blit = &r600_copy_blit, |
| 563 | // .copy_dma = &r600_copy_blit, |
565 | .copy_dma = &r600_copy_blit, |
| 564 | // .copy = &r600_copy_blit, |
566 | .copy = &r600_copy_blit, |
| 565 | .get_engine_clock = &radeon_atom_get_engine_clock, |
567 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 566 | .set_engine_clock = &radeon_atom_set_engine_clock, |
568 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 567 | .get_memory_clock = NULL, |
569 | .get_memory_clock = NULL, |
| 568 | .set_memory_clock = NULL, |
570 | .set_memory_clock = NULL, |
| 569 | .get_pcie_lanes = NULL, |
571 | .get_pcie_lanes = NULL, |
| Line 592... | Line 594... | ||
| 592 | .ring_ib_execute = &r600_ring_ib_execute, |
594 | .ring_ib_execute = &r600_ring_ib_execute, |
| 593 | .irq_set = &r600_irq_set, |
595 | .irq_set = &r600_irq_set, |
| 594 | .irq_process = &r600_irq_process, |
596 | .irq_process = &r600_irq_process, |
| 595 | .fence_ring_emit = &r600_fence_ring_emit, |
597 | .fence_ring_emit = &r600_fence_ring_emit, |
| 596 | // .cs_parse = &r600_cs_parse, |
598 | // .cs_parse = &r600_cs_parse, |
| 597 | // .copy_blit = &r600_copy_blit, |
599 | .copy_blit = &r600_copy_blit, |
| 598 | // .copy_dma = &r600_copy_blit, |
600 | .copy_dma = &r600_copy_blit, |
| 599 | // .copy = &r600_copy_blit, |
601 | .copy = &r600_copy_blit, |
| 600 | .get_engine_clock = &radeon_atom_get_engine_clock, |
602 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 601 | .set_engine_clock = &radeon_atom_set_engine_clock, |
603 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 602 | .get_memory_clock = &radeon_atom_get_memory_clock, |
604 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 603 | .set_memory_clock = &radeon_atom_set_memory_clock, |
605 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 604 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
606 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 605 | .set_pcie_lanes = NULL, |
607 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 606 | .set_clock_gating = &radeon_atom_set_clock_gating, |
608 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 607 | .set_surface_reg = r600_set_surface_reg, |
609 | .set_surface_reg = r600_set_surface_reg, |
| 608 | .clear_surface_reg = r600_clear_surface_reg, |
610 | .clear_surface_reg = r600_clear_surface_reg, |
| 609 | .bandwidth_update = &rv515_bandwidth_update, |
611 | .bandwidth_update = &rv515_bandwidth_update, |
| 610 | .hpd_init = &r600_hpd_init, |
612 | .hpd_init = &r600_hpd_init, |
| Line 622... | Line 624... | ||
| 622 | .asic_reset = &evergreen_asic_reset, |
624 | .asic_reset = &evergreen_asic_reset, |
| 623 | .vga_set_state = &r600_vga_set_state, |
625 | .vga_set_state = &r600_vga_set_state, |
| 624 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
626 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 625 | .gart_set_page = &rs600_gart_set_page, |
627 | .gart_set_page = &rs600_gart_set_page, |
| 626 | .ring_test = &r600_ring_test, |
628 | .ring_test = &r600_ring_test, |
| 627 | // .ring_ib_execute = &r600_ring_ib_execute, |
629 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 628 | // .irq_set = &r600_irq_set, |
630 | .irq_set = &evergreen_irq_set, |
| 629 | // .irq_process = &r600_irq_process, |
631 | .irq_process = &evergreen_irq_process, |
| 630 | .fence_ring_emit = &r600_fence_ring_emit, |
632 | .fence_ring_emit = &r600_fence_ring_emit, |
| 631 | // .cs_parse = &r600_cs_parse, |
633 | // .cs_parse = &evergreen_cs_parse, |
| 632 | // .copy_blit = &r600_copy_blit, |
634 | .copy_blit = &evergreen_copy_blit, |
| 633 | // .copy_dma = &r600_copy_blit, |
635 | .copy_dma = &evergreen_copy_blit, |
| 634 | // .copy = &r600_copy_blit, |
636 | .copy = &evergreen_copy_blit, |
| 635 | .get_engine_clock = &radeon_atom_get_engine_clock, |
637 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 636 | .set_engine_clock = &radeon_atom_set_engine_clock, |
638 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 637 | .get_memory_clock = &radeon_atom_get_memory_clock, |
639 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 638 | .set_memory_clock = &radeon_atom_set_memory_clock, |
640 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 639 | .get_pcie_lanes = &r600_get_pcie_lanes, |
641 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 640 | .set_pcie_lanes = &r600_set_pcie_lanes, |
642 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 641 | .set_clock_gating = NULL, |
643 | .set_clock_gating = NULL, |
| 642 | .set_surface_reg = r600_set_surface_reg, |
644 | .set_surface_reg = r600_set_surface_reg, |
| 643 | .clear_surface_reg = r600_clear_surface_reg, |
645 | .clear_surface_reg = r600_clear_surface_reg, |
| 644 | .bandwidth_update = &evergreen_bandwidth_update, |
646 | .bandwidth_update = &evergreen_bandwidth_update, |
| - | 647 | .hpd_init = &evergreen_hpd_init, |
|
| - | 648 | .hpd_fini = &evergreen_hpd_fini, |
|
| - | 649 | .hpd_sense = &evergreen_hpd_sense, |
|
| - | 650 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
|
| Line 645... | Line 651... | ||
| 645 | 651 | ||
| Line 646... | Line 652... | ||
| 646 | }; |
652 | }; |
| 647 | 653 | ||
| Line 654... | Line 660... | ||
| 654 | .asic_reset = &evergreen_asic_reset, |
660 | .asic_reset = &evergreen_asic_reset, |
| 655 | .vga_set_state = &r600_vga_set_state, |
661 | .vga_set_state = &r600_vga_set_state, |
| 656 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
662 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 657 | .gart_set_page = &rs600_gart_set_page, |
663 | .gart_set_page = &rs600_gart_set_page, |
| 658 | .ring_test = &r600_ring_test, |
664 | .ring_test = &r600_ring_test, |
| 659 | // .ring_ib_execute = &r600_ring_ib_execute, |
665 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 660 | // .irq_set = &r600_irq_set, |
666 | .irq_set = &evergreen_irq_set, |
| 661 | // .irq_process = &r600_irq_process, |
667 | .irq_process = &evergreen_irq_process, |
| 662 | .fence_ring_emit = &r600_fence_ring_emit, |
668 | .fence_ring_emit = &r600_fence_ring_emit, |
| 663 | // .cs_parse = &r600_cs_parse, |
669 | // .cs_parse = &r600_cs_parse, |
| 664 | // .copy_blit = &r600_copy_blit, |
670 | .copy_blit = &evergreen_copy_blit, |
| 665 | // .copy_dma = &r600_copy_blit, |
671 | .copy_dma = &evergreen_copy_blit, |
| 666 | // .copy = &r600_copy_blit, |
672 | .copy = &evergreen_copy_blit, |
| 667 | .get_engine_clock = &radeon_atom_get_engine_clock, |
673 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 668 | .set_engine_clock = &radeon_atom_set_engine_clock, |
674 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 669 | .get_memory_clock = NULL, |
675 | .get_memory_clock = NULL, |
| 670 | .set_memory_clock = NULL, |
676 | .set_memory_clock = NULL, |
| 671 | .get_pcie_lanes = NULL, |
677 | .get_pcie_lanes = NULL, |
| 672 | .set_pcie_lanes = NULL, |
678 | .set_pcie_lanes = NULL, |
| 673 | .set_clock_gating = NULL, |
679 | .set_clock_gating = NULL, |
| 674 | .set_surface_reg = r600_set_surface_reg, |
680 | .set_surface_reg = r600_set_surface_reg, |
| 675 | .clear_surface_reg = r600_clear_surface_reg, |
681 | .clear_surface_reg = r600_clear_surface_reg, |
| 676 | .bandwidth_update = &evergreen_bandwidth_update, |
682 | .bandwidth_update = &evergreen_bandwidth_update, |
| - | 683 | .hpd_init = &evergreen_hpd_init, |
|
| - | 684 | .hpd_fini = &evergreen_hpd_fini, |
|
| - | 685 | .hpd_sense = &evergreen_hpd_sense, |
|
| - | 686 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
|
| 677 | }; |
687 | }; |
| Line 678... | Line -... | ||
| 678 | - | ||
| 679 | 688 | ||
| 680 | static struct radeon_asic btc_asic = { |
689 | static struct radeon_asic btc_asic = { |
| 681 | .init = &evergreen_init, |
690 | .init = &evergreen_init, |
| 682 | // .fini = &evergreen_fini, |
691 | // .fini = &evergreen_fini, |
| 683 | // .suspend = &evergreen_suspend, |
692 | // .suspend = &evergreen_suspend, |
| Line 686... | Line 695... | ||
| 686 | .asic_reset = &evergreen_asic_reset, |
695 | .asic_reset = &evergreen_asic_reset, |
| 687 | .vga_set_state = &r600_vga_set_state, |
696 | .vga_set_state = &r600_vga_set_state, |
| 688 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
697 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 689 | .gart_set_page = &rs600_gart_set_page, |
698 | .gart_set_page = &rs600_gart_set_page, |
| 690 | .ring_test = &r600_ring_test, |
699 | .ring_test = &r600_ring_test, |
| 691 | // .ring_ib_execute = &r600_ring_ib_execute, |
700 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 692 | // .irq_set = &r600_irq_set, |
701 | .irq_set = &evergreen_irq_set, |
| 693 | // .irq_process = &r600_irq_process, |
702 | .irq_process = &evergreen_irq_process, |
| 694 | .fence_ring_emit = &r600_fence_ring_emit, |
703 | .fence_ring_emit = &r600_fence_ring_emit, |
| 695 | // .cs_parse = &r600_cs_parse, |
704 | // .cs_parse = &evergreen_cs_parse, |
| 696 | // .copy_blit = &r600_copy_blit, |
705 | .copy_blit = &evergreen_copy_blit, |
| 697 | // .copy_dma = &r600_copy_blit, |
706 | .copy_dma = &evergreen_copy_blit, |
| 698 | // .copy = &r600_copy_blit, |
707 | .copy = &evergreen_copy_blit, |
| 699 | .get_engine_clock = &radeon_atom_get_engine_clock, |
708 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 700 | .set_engine_clock = &radeon_atom_set_engine_clock, |
709 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 701 | .get_memory_clock = &radeon_atom_get_memory_clock, |
710 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 702 | .set_memory_clock = &radeon_atom_set_memory_clock, |
711 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 703 | .get_pcie_lanes = NULL, |
712 | .get_pcie_lanes = NULL, |
| Line 705... | Line 714... | ||
| 705 | .set_clock_gating = NULL, |
714 | .set_clock_gating = NULL, |
| 706 | .set_surface_reg = r600_set_surface_reg, |
715 | .set_surface_reg = r600_set_surface_reg, |
| 707 | .clear_surface_reg = r600_clear_surface_reg, |
716 | .clear_surface_reg = r600_clear_surface_reg, |
| 708 | .bandwidth_update = &evergreen_bandwidth_update, |
717 | .bandwidth_update = &evergreen_bandwidth_update, |
| 709 | .hpd_init = &evergreen_hpd_init, |
718 | .hpd_init = &evergreen_hpd_init, |
| - | 719 | .hpd_fini = &evergreen_hpd_fini, |
|
| 710 | .hpd_sense = &evergreen_hpd_sense, |
720 | .hpd_sense = &evergreen_hpd_sense, |
| - | 721 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
|
| 711 | }; |
722 | }; |
| Line 712... | Line 723... | ||
| 712 | 723 | ||
| 713 | static struct radeon_asic cayman_asic = { |
724 | static struct radeon_asic cayman_asic = { |
| 714 | .init = &cayman_init, |
725 | .init = &cayman_init, |
| Line 719... | Line 730... | ||
| 719 | .asic_reset = &cayman_asic_reset, |
730 | .asic_reset = &cayman_asic_reset, |
| 720 | .vga_set_state = &r600_vga_set_state, |
731 | .vga_set_state = &r600_vga_set_state, |
| 721 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
732 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 722 | .gart_set_page = &rs600_gart_set_page, |
733 | .gart_set_page = &rs600_gart_set_page, |
| 723 | .ring_test = &r600_ring_test, |
734 | .ring_test = &r600_ring_test, |
| 724 | // .ring_ib_execute = &r600_ring_ib_execute, |
735 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 725 | // .irq_set = &r600_irq_set, |
736 | .irq_set = &evergreen_irq_set, |
| 726 | // .irq_process = &r600_irq_process, |
737 | .irq_process = &evergreen_irq_process, |
| 727 | .fence_ring_emit = &r600_fence_ring_emit, |
738 | .fence_ring_emit = &r600_fence_ring_emit, |
| 728 | // .cs_parse = &r600_cs_parse, |
739 | // .cs_parse = &evergreen_cs_parse, |
| 729 | // .copy_blit = &r600_copy_blit, |
740 | .copy_blit = &evergreen_copy_blit, |
| 730 | // .copy_dma = &r600_copy_blit, |
741 | .copy_dma = &evergreen_copy_blit, |
| 731 | // .copy = &r600_copy_blit, |
742 | .copy = &evergreen_copy_blit, |
| 732 | .get_engine_clock = &radeon_atom_get_engine_clock, |
743 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 733 | .set_engine_clock = &radeon_atom_set_engine_clock, |
744 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 734 | .get_memory_clock = &radeon_atom_get_memory_clock, |
745 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 735 | .set_memory_clock = &radeon_atom_set_memory_clock, |
746 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 736 | .get_pcie_lanes = NULL, |
747 | .get_pcie_lanes = NULL, |
| 737 | .set_pcie_lanes = NULL, |
748 | .set_pcie_lanes = NULL, |
| 738 | .set_clock_gating = NULL, |
749 | .set_clock_gating = NULL, |
| 739 | .set_surface_reg = r600_set_surface_reg, |
750 | .set_surface_reg = r600_set_surface_reg, |
| 740 | .clear_surface_reg = r600_clear_surface_reg, |
751 | .clear_surface_reg = r600_clear_surface_reg, |
| 741 | .bandwidth_update = &evergreen_bandwidth_update, |
752 | .bandwidth_update = &evergreen_bandwidth_update, |
| - | 753 | .hpd_init = &evergreen_hpd_init, |
|
| - | 754 | .hpd_fini = &evergreen_hpd_fini, |
|
| - | 755 | .hpd_sense = &evergreen_hpd_sense, |
|
| - | 756 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
|
| 742 | }; |
757 | }; |
| Line 743... | Line 758... | ||
| 743 | 758 | ||
| 744 | int radeon_asic_init(struct radeon_device *rdev) |
759 | int radeon_asic_init(struct radeon_device *rdev) |
| 745 | { |
760 | { |