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Rev 1990 Rev 2004
Line 516... Line 516...
516 
	.asic_reset = &r600_asic_reset,
 516 
	.asic_reset = &r600_asic_reset,
517 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 517 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
518 
	.gart_set_page = &rs600_gart_set_page,
 518 
	.gart_set_page = &rs600_gart_set_page,
519 
	.ring_test = &r600_ring_test,
 519 
	.ring_test = &r600_ring_test,
520 
//	.ring_ib_execute = &r600_ring_ib_execute,
 520 
//	.ring_ib_execute = &r600_ring_ib_execute,
521 
//	.irq_set = &r600_irq_set,
 521 
	.irq_set = &r600_irq_set,
522 
//	.irq_process = &r600_irq_process,
 522 
	.irq_process = &r600_irq_process,
523 
	.fence_ring_emit = &r600_fence_ring_emit,
 523 
	.fence_ring_emit = &r600_fence_ring_emit,
524 
//	.cs_parse = &r600_cs_parse,
 524 
//	.cs_parse = &r600_cs_parse,
525 
//	.copy_blit = &r600_copy_blit,
 525 
//	.copy_blit = &r600_copy_blit,
526 
//	.copy_dma = &r600_copy_blit,
 526 
//	.copy_dma = &r600_copy_blit,
527 
//	.copy = &r600_copy_blit,
 527 
//	.copy = &r600_copy_blit,
Line 553... Line 553...
553 
	.asic_reset = &r600_asic_reset,
 553 
	.asic_reset = &r600_asic_reset,
554 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 554 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
555 
	.gart_set_page = &rs600_gart_set_page,
 555 
	.gart_set_page = &rs600_gart_set_page,
556 
	.ring_test = &r600_ring_test,
 556 
	.ring_test = &r600_ring_test,
557 
//	.ring_ib_execute = &r600_ring_ib_execute,
 557 
//	.ring_ib_execute = &r600_ring_ib_execute,
558 
//	.irq_set = &r600_irq_set,
 558 
	.irq_set = &r600_irq_set,
559 
//	.irq_process = &r600_irq_process,
 559 
	.irq_process = &r600_irq_process,
560 
	.fence_ring_emit = &r600_fence_ring_emit,
 560 
	.fence_ring_emit = &r600_fence_ring_emit,
561 
//	.cs_parse = &r600_cs_parse,
 561 
//	.cs_parse = &r600_cs_parse,
562 
//	.copy_blit = &r600_copy_blit,
 562 
//	.copy_blit = &r600_copy_blit,
563 
//	.copy_dma = &r600_copy_blit,
 563 
//	.copy_dma = &r600_copy_blit,
564 
//	.copy = &r600_copy_blit,
 564 
//	.copy = &r600_copy_blit,
Line 587... Line 587...
587 
	.asic_reset = &r600_asic_reset,
 587 
	.asic_reset = &r600_asic_reset,
588 
	.vga_set_state = &r600_vga_set_state,
 588 
	.vga_set_state = &r600_vga_set_state,
589 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 589 
	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
590 
	.gart_set_page = &rs600_gart_set_page,
 590 
	.gart_set_page = &rs600_gart_set_page,
591 
	.ring_test = &r600_ring_test,
 591 
	.ring_test = &r600_ring_test,
592 
//	.ring_ib_execute = &r600_ring_ib_execute,
 592 
	.ring_ib_execute = &r600_ring_ib_execute,
593 
//	.irq_set = &r600_irq_set,
 593 
	.irq_set = &r600_irq_set,
594 
//	.irq_process = &r600_irq_process,
 594 
	.irq_process = &r600_irq_process,
595 
	.fence_ring_emit = &r600_fence_ring_emit,
 595 
	.fence_ring_emit = &r600_fence_ring_emit,
596 
//	.cs_parse = &r600_cs_parse,
 596 
//	.cs_parse = &r600_cs_parse,
597 
//	.copy_blit = &r600_copy_blit,
 597 
//	.copy_blit = &r600_copy_blit,
598 
//	.copy_dma = &r600_copy_blit,
 598 
//	.copy_dma = &r600_copy_blit,
599 
//	.copy = &r600_copy_blit,
 599 
//	.copy = &r600_copy_blit,
Line 704... Line 704...
704 
	.set_pcie_lanes = NULL,
 704 
	.set_pcie_lanes = NULL,
705 
	.set_clock_gating = NULL,
 705 
	.set_clock_gating = NULL,
706 
	.set_surface_reg = r600_set_surface_reg,
 706 
	.set_surface_reg = r600_set_surface_reg,
707 
	.clear_surface_reg = r600_clear_surface_reg,
 707 
	.clear_surface_reg = r600_clear_surface_reg,
708 
	.bandwidth_update = &evergreen_bandwidth_update,
 708 
	.bandwidth_update = &evergreen_bandwidth_update,
- 
 
 709 
	.hpd_init = &evergreen_hpd_init,
- 
 
 710 
	.hpd_sense = &evergreen_hpd_sense,
709 
};
 711 
};
Line 710... Line -...
710 
 
 - 
 
711 
 
 - 
 
712 
#if 0
 712 
 
713 
static struct radeon_asic cayman_asic = {
 713 
static struct radeon_asic cayman_asic = {
714 
	.init = &cayman_init,
 714 
	.init = &cayman_init,
715 
	.fini = &cayman_fini,
 715 
//	.fini = &evergreen_fini,
716 
	.suspend = &cayman_suspend,
 716 
//	.suspend = &evergreen_suspend,
717 
	.resume = &cayman_resume,
 717 
//	.resume = &evergreen_resume,
718 
	.cp_commit = &r600_cp_commit,
 - 
 
719 
	.gpu_is_lockup = &cayman_gpu_is_lockup,
 718 
	.cp_commit = &r600_cp_commit,
720 
	.asic_reset = &cayman_asic_reset,
 719 
	.asic_reset = &cayman_asic_reset,
721 
	.vga_set_state = &r600_vga_set_state,
 720 
	.vga_set_state = &r600_vga_set_state,
722 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
 721 
	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
723 
	.gart_set_page = &rs600_gart_set_page,
 722 
	.gart_set_page = &rs600_gart_set_page,
724 
	.ring_test = &r600_ring_test,
 723 
	.ring_test = &r600_ring_test,
725 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 724 
//	.ring_ib_execute = &r600_ring_ib_execute,
726 
	.irq_set = &evergreen_irq_set,
 725 
//	.irq_set = &r600_irq_set,
727 
	.irq_process = &evergreen_irq_process,
 - 
 
728 
	.get_vblank_counter = &evergreen_get_vblank_counter,
 726 
//	.irq_process = &r600_irq_process,
729 
	.fence_ring_emit = &r600_fence_ring_emit,
 727 
	.fence_ring_emit = &r600_fence_ring_emit,
730 
//	.cs_parse = &r600_cs_parse,
 728 
//	.cs_parse = &r600_cs_parse,
731 
//	.copy_blit = &r600_copy_blit,
 729 
//	.copy_blit = &r600_copy_blit,
732 
//	.copy_dma = &r600_copy_blit,
 730 
//	.copy_dma = &r600_copy_blit,
733 
//	.copy = &r600_copy_blit,
 731 
//	.copy = &r600_copy_blit,
734 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 732 
	.get_engine_clock = &radeon_atom_get_engine_clock,
735 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 733 
	.set_engine_clock = &radeon_atom_set_engine_clock,
736 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 734 
	.get_memory_clock = &radeon_atom_get_memory_clock,
- 
 
 735 
	.set_memory_clock = &radeon_atom_set_memory_clock,
737 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 736 
	.get_pcie_lanes = NULL,
738 
	.set_pcie_lanes = NULL,
 737 
	.set_pcie_lanes = NULL,
739 
	.set_clock_gating = NULL,
 738 
	.set_clock_gating = NULL,
740 
	.set_surface_reg = r600_set_surface_reg,
 739 
	.set_surface_reg = r600_set_surface_reg,
741 
	.clear_surface_reg = r600_clear_surface_reg,
 740 
	.clear_surface_reg = r600_clear_surface_reg,
742 
	.bandwidth_update = &evergreen_bandwidth_update,
 - 
 
743 
	.gui_idle = &r600_gui_idle,
 - 
 
744 
	.pm_misc = &evergreen_pm_misc,
 - 
 
745 
	.pm_prepare = &evergreen_pm_prepare,
 - 
 
746 
	.pm_finish = &evergreen_pm_finish,
 - 
 
747 
	.pm_init_profile = &r600_pm_init_profile,
 - 
 
748 
	.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 - 
 
749 
	.pre_page_flip = &evergreen_pre_page_flip,
 - 
 
750 
	.page_flip = &evergreen_page_flip,
 - 
 
751 
	.post_page_flip = &evergreen_post_page_flip,
 741 
	.bandwidth_update = &evergreen_bandwidth_update,
752 
};
 - 
 
Line 753... Line 742...
753 
#endif
 742 
};
754 
 
 743 
 
755 
int radeon_asic_init(struct radeon_device *rdev)
 744 
int radeon_asic_init(struct radeon_device *rdev)
Line 861... Line 850...
861 
			rdev->num_crtc = 4;
 850 
			rdev->num_crtc = 4;
862 
		else
 851 
		else
863 
			rdev->num_crtc = 6;
 852 
			rdev->num_crtc = 6;
864 
		rdev->asic = &btc_asic;
 853 
		rdev->asic = &btc_asic;
865 
		break;
 854 
		break;
- 
 
 855 
	case CHIP_CAYMAN:
- 
 
 856 
		rdev->asic = &cayman_asic;
- 
 
 857 
		/* set num crtcs */
- 
 
 858 
		rdev->num_crtc = 6;
866 
 
 859 
		break;
867 
	default:
 860 
	default:
868 
		/* FIXME: not supported yet */
 861 
		/* FIXME: not supported yet */
869 
		return -EINVAL;
 862 
		return -EINVAL;
870 
	}
 863 
	}