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Rev 1986 Rev 1990
Line 642... Line 642...
642 
	.set_surface_reg = r600_set_surface_reg,
 642 
	.set_surface_reg = r600_set_surface_reg,
643 
	.clear_surface_reg = r600_clear_surface_reg,
 643 
	.clear_surface_reg = r600_clear_surface_reg,
644 
	.bandwidth_update = &evergreen_bandwidth_update,
 644 
	.bandwidth_update = &evergreen_bandwidth_update,
Line 645... Line 645...
645 
 
 645 
 
646 
};
 646 
};
647 
#if 0
 647 
 
648 
static struct radeon_asic sumo_asic = {
 648 
static struct radeon_asic sumo_asic = {
649 
	.init = &evergreen_init,
 649 
	.init = &evergreen_init,
650 
	.fini = &evergreen_fini,
 650 
//	.fini = &evergreen_fini,
651 
	.suspend = &evergreen_suspend,
 651 
//	.suspend = &evergreen_suspend,
652 
	.resume = &evergreen_resume,
 652 
//	.resume = &evergreen_resume,
653 
	.cp_commit = &r600_cp_commit,
 - 
 
654 
	.gpu_is_lockup = &evergreen_gpu_is_lockup,
 653 
	.cp_commit = &r600_cp_commit,
655 
	.asic_reset = &evergreen_asic_reset,
 654 
	.asic_reset = &evergreen_asic_reset,
656 
	.vga_set_state = &r600_vga_set_state,
 655 
	.vga_set_state = &r600_vga_set_state,
657 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 656 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
658 
	.gart_set_page = &rs600_gart_set_page,
 657 
	.gart_set_page = &rs600_gart_set_page,
659 
	.ring_test = &r600_ring_test,
 658 
	.ring_test = &r600_ring_test,
660 
	.ring_ib_execute = &evergreen_ring_ib_execute,
 659 
//	.ring_ib_execute = &r600_ring_ib_execute,
661 
	.irq_set = &evergreen_irq_set,
 660 
//	.irq_set = &r600_irq_set,
662 
	.irq_process = &evergreen_irq_process,
 - 
 
663 
	.get_vblank_counter = &evergreen_get_vblank_counter,
 661 
//	.irq_process = &r600_irq_process,
664 
	.fence_ring_emit = &r600_fence_ring_emit,
 662 
	.fence_ring_emit = &r600_fence_ring_emit,
665 
	.cs_parse = &evergreen_cs_parse,
 663 
//	.cs_parse = &r600_cs_parse,
666 
	.copy_blit = &evergreen_copy_blit,
 664 
//	.copy_blit = &r600_copy_blit,
667 
	.copy_dma = &evergreen_copy_blit,
 665 
//	.copy_dma = &r600_copy_blit,
668 
	.copy = &evergreen_copy_blit,
 666 
//	.copy = &r600_copy_blit,
669 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 667 
	.get_engine_clock = &radeon_atom_get_engine_clock,
670 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 668 
	.set_engine_clock = &radeon_atom_set_engine_clock,
671 
	.get_memory_clock = NULL,
 669 
	.get_memory_clock = NULL,
672 
	.set_memory_clock = NULL,
 670 
	.set_memory_clock = NULL,
673 
	.get_pcie_lanes = NULL,
 671 
	.get_pcie_lanes = NULL,
674 
	.set_pcie_lanes = NULL,
 672 
	.set_pcie_lanes = NULL,
675 
	.set_clock_gating = NULL,
 673 
	.set_clock_gating = NULL,
676 
	.set_surface_reg = r600_set_surface_reg,
 674 
	.set_surface_reg = r600_set_surface_reg,
677 
	.clear_surface_reg = r600_clear_surface_reg,
 675 
	.clear_surface_reg = r600_clear_surface_reg,
678 
	.bandwidth_update = &evergreen_bandwidth_update,
 - 
 
679 
	.gui_idle = &r600_gui_idle,
 - 
 
680 
	.pm_misc = &evergreen_pm_misc,
 - 
 
681 
	.pm_prepare = &evergreen_pm_prepare,
 - 
 
682 
	.pm_finish = &evergreen_pm_finish,
 - 
 
683 
	.pm_init_profile = &rs780_pm_init_profile,
 - 
 
684 
	.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 - 
 
685 
	.pre_page_flip = &evergreen_pre_page_flip,
 - 
 
686 
	.page_flip = &evergreen_page_flip,
 - 
 
687 
	.post_page_flip = &evergreen_post_page_flip,
 676 
	.bandwidth_update = &evergreen_bandwidth_update,
Line -... Line 677...
- 
 
 677 
};
688 
};
 678 
 
689 
 
 679 
 
690 
static struct radeon_asic btc_asic = {
 680 
static struct radeon_asic btc_asic = {
691 
	.init = &evergreen_init,
 681 
	.init = &evergreen_init,
692 
	.fini = &evergreen_fini,
 682 
//	.fini = &evergreen_fini,
693 
	.suspend = &evergreen_suspend,
 683 
//	.suspend = &evergreen_suspend,
694 
	.resume = &evergreen_resume,
 - 
 
695 
	.cp_commit = &r600_cp_commit,
 684 
//	.resume = &evergreen_resume,
696 
	.gpu_is_lockup = &evergreen_gpu_is_lockup,
 685 
	.cp_commit = &r600_cp_commit,
697 
	.asic_reset = &evergreen_asic_reset,
 686 
	.asic_reset = &evergreen_asic_reset,
698 
	.vga_set_state = &r600_vga_set_state,
 687 
	.vga_set_state = &r600_vga_set_state,
699 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 688 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
700 
	.gart_set_page = &rs600_gart_set_page,
 689 
	.gart_set_page = &rs600_gart_set_page,
701 
	.ring_test = NULL,
 690 
	.ring_test = &r600_ring_test,
702 
//	.ring_ib_execute = &r600_ring_ib_execute,
 691 
//	.ring_ib_execute = &r600_ring_ib_execute,
703 
//	.irq_set = &r600_irq_set,
 - 
 
704 
//	.irq_process = &r600_irq_process,
 692 
//	.irq_set = &r600_irq_set,
705 
	.get_vblank_counter = &evergreen_get_vblank_counter,
 693 
//	.irq_process = &r600_irq_process,
706 
	.fence_ring_emit = &r600_fence_ring_emit,
 694 
	.fence_ring_emit = &r600_fence_ring_emit,
707 
	.cs_parse = &evergreen_cs_parse,
 695 
//	.cs_parse = &r600_cs_parse,
708 
	.copy_blit = &evergreen_copy_blit,
 696 
//	.copy_blit = &r600_copy_blit,
709 
	.copy_dma = &evergreen_copy_blit,
 697 
//	.copy_dma = &r600_copy_blit,
710 
	.copy = &evergreen_copy_blit,
 698 
//	.copy = &r600_copy_blit,
711 
	.get_engine_clock = &radeon_atom_get_engine_clock,
 699 
	.get_engine_clock = &radeon_atom_get_engine_clock,
712 
	.set_engine_clock = &radeon_atom_set_engine_clock,
 700 
	.set_engine_clock = &radeon_atom_set_engine_clock,
713 
	.get_memory_clock = &radeon_atom_get_memory_clock,
 701 
	.get_memory_clock = &radeon_atom_get_memory_clock,
714 
	.set_memory_clock = &radeon_atom_set_memory_clock,
 702 
	.set_memory_clock = &radeon_atom_set_memory_clock,
715 
	.get_pcie_lanes = NULL,
 703 
	.get_pcie_lanes = NULL,
716 
	.set_pcie_lanes = NULL,
 704 
	.set_pcie_lanes = NULL,
717 
	.set_clock_gating = NULL,
 705 
	.set_clock_gating = NULL,
718 
	.set_surface_reg = r600_set_surface_reg,
 706 
	.set_surface_reg = r600_set_surface_reg,
719 
	.clear_surface_reg = r600_clear_surface_reg,
 - 
 
720 
	.bandwidth_update = &evergreen_bandwidth_update,
 - 
 
721 
	.gui_idle = &r600_gui_idle,
 - 
 
722 
	.pm_misc = &evergreen_pm_misc,
 - 
 
723 
	.pm_prepare = &evergreen_pm_prepare,
 - 
 
724 
	.pm_finish = &evergreen_pm_finish,
 - 
 
725 
	.pm_init_profile = &r600_pm_init_profile,
 - 
 
726 
	.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 - 
 
727 
	.pre_page_flip = &evergreen_pre_page_flip,
 - 
 
728 
	.page_flip = &evergreen_page_flip,
 707 
	.clear_surface_reg = r600_clear_surface_reg,
Line -... Line 708...
- 
 
 708 
	.bandwidth_update = &evergreen_bandwidth_update,
- 
 
 709 
};
729 
	.post_page_flip = &evergreen_post_page_flip,
 710 
 
730 
};
 711 
 
731 
 
 712 
#if 0
732 
static struct radeon_asic cayman_asic = {
 713 
static struct radeon_asic cayman_asic = {
733 
	.init = &cayman_init,
 714 
	.init = &cayman_init,
Line 865... Line 846...
865 
			rdev->num_crtc = 4;
 846 
			rdev->num_crtc = 4;
866 
		else
 847 
		else
867 
			rdev->num_crtc = 6;
 848 
			rdev->num_crtc = 6;
868 
		rdev->asic = &evergreen_asic;
 849 
		rdev->asic = &evergreen_asic;
869 
		break;
 850 
		break;
- 
 
 851 
	case CHIP_PALM:
- 
 
 852 
	case CHIP_SUMO:
- 
 
 853 
	case CHIP_SUMO2:
- 
 
 854 
		rdev->asic = &sumo_asic;
- 
 
 855 
		break;
- 
 
 856 
	case CHIP_BARTS:
- 
 
 857 
	case CHIP_TURKS:
- 
 
 858 
	case CHIP_CAICOS:
- 
 
 859 
		/* set num crtcs */
- 
 
 860 
		if (rdev->family == CHIP_CAICOS)
- 
 
 861 
			rdev->num_crtc = 4;
- 
 
 862 
		else
- 
 
 863 
			rdev->num_crtc = 6;
- 
 
 864 
		rdev->asic = &btc_asic;
- 
 
 865 
		break;
- 
 
 866 
 
870 
	default:
 867 
	default:
871 
		/* FIXME: not supported yet */
 868 
		/* FIXME: not supported yet */
872 
		return -EINVAL;
 869 
		return -EINVAL;
873 
	}
 870 
	}