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| Rev 1963 | Rev 1986 | ||
|---|---|---|---|
| Line 610... | Line 610... | ||
| 610 | .hpd_init = &r600_hpd_init, |
610 | .hpd_init = &r600_hpd_init, |
| 611 | .hpd_fini = &r600_hpd_fini, |
611 | .hpd_fini = &r600_hpd_fini, |
| 612 | .hpd_sense = &r600_hpd_sense, |
612 | .hpd_sense = &r600_hpd_sense, |
| 613 | .hpd_set_polarity = &r600_hpd_set_polarity, |
613 | .hpd_set_polarity = &r600_hpd_set_polarity, |
| 614 | }; |
614 | }; |
| 615 | #if 0 |
615 | |
| 616 | static struct radeon_asic evergreen_asic = { |
616 | static struct radeon_asic evergreen_asic = { |
| 617 | .init = &evergreen_init, |
617 | .init = &evergreen_init, |
| 618 | // .fini = &evergreen_fini, |
618 | // .fini = &evergreen_fini, |
| 619 | // .suspend = &evergreen_suspend, |
619 | // .suspend = &evergreen_suspend, |
| 620 | // .resume = &evergreen_resume, |
620 | // .resume = &evergreen_resume, |
| - | 621 | .cp_commit = &r600_cp_commit, |
|
| - | 622 | .asic_reset = &evergreen_asic_reset, |
|
| - | 623 | .vga_set_state = &r600_vga_set_state, |
|
| - | 624 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
|
| - | 625 | .gart_set_page = &rs600_gart_set_page, |
|
| - | 626 | .ring_test = &r600_ring_test, |
|
| - | 627 | // .ring_ib_execute = &r600_ring_ib_execute, |
|
| - | 628 | // .irq_set = &r600_irq_set, |
|
| - | 629 | // .irq_process = &r600_irq_process, |
|
| - | 630 | .fence_ring_emit = &r600_fence_ring_emit, |
|
| - | 631 | // .cs_parse = &r600_cs_parse, |
|
| - | 632 | // .copy_blit = &r600_copy_blit, |
|
| - | 633 | // .copy_dma = &r600_copy_blit, |
|
| - | 634 | // .copy = &r600_copy_blit, |
|
| - | 635 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| - | 636 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
| - | 637 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| - | 638 | .set_memory_clock = &radeon_atom_set_memory_clock, |
|
| - | 639 | .get_pcie_lanes = &r600_get_pcie_lanes, |
|
| - | 640 | .set_pcie_lanes = &r600_set_pcie_lanes, |
|
| - | 641 | .set_clock_gating = NULL, |
|
| - | 642 | .set_surface_reg = r600_set_surface_reg, |
|
| - | 643 | .clear_surface_reg = r600_clear_surface_reg, |
|
| - | 644 | .bandwidth_update = &evergreen_bandwidth_update, |
|
| - | 645 | ||
| - | 646 | }; |
|
| - | 647 | #if 0 |
|
| - | 648 | static struct radeon_asic sumo_asic = { |
|
| - | 649 | .init = &evergreen_init, |
|
| - | 650 | .fini = &evergreen_fini, |
|
| - | 651 | .suspend = &evergreen_suspend, |
|
| - | 652 | .resume = &evergreen_resume, |
|
| - | 653 | .cp_commit = &r600_cp_commit, |
|
| - | 654 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
|
| - | 655 | .asic_reset = &evergreen_asic_reset, |
|
| - | 656 | .vga_set_state = &r600_vga_set_state, |
|
| - | 657 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
|
| - | 658 | .gart_set_page = &rs600_gart_set_page, |
|
| - | 659 | .ring_test = &r600_ring_test, |
|
| - | 660 | .ring_ib_execute = &evergreen_ring_ib_execute, |
|
| - | 661 | .irq_set = &evergreen_irq_set, |
|
| - | 662 | .irq_process = &evergreen_irq_process, |
|
| - | 663 | .get_vblank_counter = &evergreen_get_vblank_counter, |
|
| - | 664 | .fence_ring_emit = &r600_fence_ring_emit, |
|
| - | 665 | .cs_parse = &evergreen_cs_parse, |
|
| - | 666 | .copy_blit = &evergreen_copy_blit, |
|
| - | 667 | .copy_dma = &evergreen_copy_blit, |
|
| - | 668 | .copy = &evergreen_copy_blit, |
|
| - | 669 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| - | 670 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
| - | 671 | .get_memory_clock = NULL, |
|
| - | 672 | .set_memory_clock = NULL, |
|
| - | 673 | .get_pcie_lanes = NULL, |
|
| - | 674 | .set_pcie_lanes = NULL, |
|
| 621 | .cp_commit = NULL, |
675 | .set_clock_gating = NULL, |
| - | 676 | .set_surface_reg = r600_set_surface_reg, |
|
| - | 677 | .clear_surface_reg = r600_clear_surface_reg, |
|
| - | 678 | .bandwidth_update = &evergreen_bandwidth_update, |
|
| - | 679 | .gui_idle = &r600_gui_idle, |
|
| - | 680 | .pm_misc = &evergreen_pm_misc, |
|
| - | 681 | .pm_prepare = &evergreen_pm_prepare, |
|
| - | 682 | .pm_finish = &evergreen_pm_finish, |
|
| - | 683 | .pm_init_profile = &rs780_pm_init_profile, |
|
| - | 684 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
|
| - | 685 | .pre_page_flip = &evergreen_pre_page_flip, |
|
| - | 686 | .page_flip = &evergreen_page_flip, |
|
| - | 687 | .post_page_flip = &evergreen_post_page_flip, |
|
| - | 688 | }; |
|
| - | 689 | ||
| - | 690 | static struct radeon_asic btc_asic = { |
|
| - | 691 | .init = &evergreen_init, |
|
| - | 692 | .fini = &evergreen_fini, |
|
| - | 693 | .suspend = &evergreen_suspend, |
|
| - | 694 | .resume = &evergreen_resume, |
|
| - | 695 | .cp_commit = &r600_cp_commit, |
|
| - | 696 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
|
| 622 | .asic_reset = &evergreen_asic_reset, |
697 | .asic_reset = &evergreen_asic_reset, |
| 623 | .vga_set_state = &r600_vga_set_state, |
698 | .vga_set_state = &r600_vga_set_state, |
| 624 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
699 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 625 | .gart_set_page = &rs600_gart_set_page, |
700 | .gart_set_page = &rs600_gart_set_page, |
| 626 | .ring_test = NULL, |
701 | .ring_test = NULL, |
| 627 | // .ring_ib_execute = &r600_ring_ib_execute, |
702 | // .ring_ib_execute = &r600_ring_ib_execute, |
| 628 | // .irq_set = &r600_irq_set, |
703 | // .irq_set = &r600_irq_set, |
| 629 | // .irq_process = &r600_irq_process, |
704 | // .irq_process = &r600_irq_process, |
| - | 705 | .get_vblank_counter = &evergreen_get_vblank_counter, |
|
| - | 706 | .fence_ring_emit = &r600_fence_ring_emit, |
|
| - | 707 | .cs_parse = &evergreen_cs_parse, |
|
| - | 708 | .copy_blit = &evergreen_copy_blit, |
|
| - | 709 | .copy_dma = &evergreen_copy_blit, |
|
| - | 710 | .copy = &evergreen_copy_blit, |
|
| - | 711 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
| - | 712 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
| - | 713 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
| - | 714 | .set_memory_clock = &radeon_atom_set_memory_clock, |
|
| - | 715 | .get_pcie_lanes = NULL, |
|
| - | 716 | .set_pcie_lanes = NULL, |
|
| - | 717 | .set_clock_gating = NULL, |
|
| - | 718 | .set_surface_reg = r600_set_surface_reg, |
|
| - | 719 | .clear_surface_reg = r600_clear_surface_reg, |
|
| - | 720 | .bandwidth_update = &evergreen_bandwidth_update, |
|
| - | 721 | .gui_idle = &r600_gui_idle, |
|
| - | 722 | .pm_misc = &evergreen_pm_misc, |
|
| - | 723 | .pm_prepare = &evergreen_pm_prepare, |
|
| - | 724 | .pm_finish = &evergreen_pm_finish, |
|
| - | 725 | .pm_init_profile = &r600_pm_init_profile, |
|
| - | 726 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
|
| - | 727 | .pre_page_flip = &evergreen_pre_page_flip, |
|
| - | 728 | .page_flip = &evergreen_page_flip, |
|
| - | 729 | .post_page_flip = &evergreen_post_page_flip, |
|
| - | 730 | }; |
|
| - | 731 | ||
| - | 732 | static struct radeon_asic cayman_asic = { |
|
| - | 733 | .init = &cayman_init, |
|
| - | 734 | .fini = &cayman_fini, |
|
| - | 735 | .suspend = &cayman_suspend, |
|
| - | 736 | .resume = &cayman_resume, |
|
| - | 737 | .cp_commit = &r600_cp_commit, |
|
| - | 738 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
|
| - | 739 | .asic_reset = &cayman_asic_reset, |
|
| - | 740 | .vga_set_state = &r600_vga_set_state, |
|
| - | 741 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
|
| - | 742 | .gart_set_page = &rs600_gart_set_page, |
|
| - | 743 | .ring_test = &r600_ring_test, |
|
| - | 744 | .ring_ib_execute = &evergreen_ring_ib_execute, |
|
| - | 745 | .irq_set = &evergreen_irq_set, |
|
| - | 746 | .irq_process = &evergreen_irq_process, |
|
| - | 747 | .get_vblank_counter = &evergreen_get_vblank_counter, |
|
| 630 | .fence_ring_emit = &r600_fence_ring_emit, |
748 | .fence_ring_emit = &r600_fence_ring_emit, |
| 631 | // .cs_parse = &r600_cs_parse, |
749 | // .cs_parse = &r600_cs_parse, |
| 632 | // .copy_blit = &r600_copy_blit, |
750 | // .copy_blit = &r600_copy_blit, |
| 633 | // .copy_dma = &r600_copy_blit, |
751 | // .copy_dma = &r600_copy_blit, |
| 634 | // .copy = &r600_copy_blit, |
752 | // .copy = &r600_copy_blit, |
| Line 639... | Line 757... | ||
| 639 | .set_pcie_lanes = NULL, |
757 | .set_pcie_lanes = NULL, |
| 640 | .set_clock_gating = NULL, |
758 | .set_clock_gating = NULL, |
| 641 | .set_surface_reg = r600_set_surface_reg, |
759 | .set_surface_reg = r600_set_surface_reg, |
| 642 | .clear_surface_reg = r600_clear_surface_reg, |
760 | .clear_surface_reg = r600_clear_surface_reg, |
| 643 | .bandwidth_update = &evergreen_bandwidth_update, |
761 | .bandwidth_update = &evergreen_bandwidth_update, |
| - | 762 | .gui_idle = &r600_gui_idle, |
|
| 644 | .hpd_init = &evergreen_hpd_init, |
763 | .pm_misc = &evergreen_pm_misc, |
| - | 764 | .pm_prepare = &evergreen_pm_prepare, |
|
| 645 | .hpd_fini = &evergreen_hpd_fini, |
765 | .pm_finish = &evergreen_pm_finish, |
| - | 766 | .pm_init_profile = &r600_pm_init_profile, |
|
| - | 767 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
|
| - | 768 | .pre_page_flip = &evergreen_pre_page_flip, |
|
| 646 | .hpd_sense = &evergreen_hpd_sense, |
769 | .page_flip = &evergreen_page_flip, |
| 647 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
770 | .post_page_flip = &evergreen_post_page_flip, |
| 648 | }; |
771 | }; |
| 649 | #endif |
772 | #endif |
| Line 650... | Line 773... | ||
| 650 | 773 | ||
| 651 | int radeon_asic_init(struct radeon_device *rdev) |
774 | int radeon_asic_init(struct radeon_device *rdev) |
| 652 | { |
775 | { |
| - | 776 | radeon_register_accessor_init(rdev); |
|
| - | 777 | ||
| - | 778 | /* set the number of crtcs */ |
|
| - | 779 | if (rdev->flags & RADEON_SINGLE_CRTC) |
|
| - | 780 | rdev->num_crtc = 1; |
|
| - | 781 | else |
|
| - | 782 | rdev->num_crtc = 2; |
|
| 653 | radeon_register_accessor_init(rdev); |
783 | |
| 654 | switch (rdev->family) { |
784 | switch (rdev->family) { |
| 655 | case CHIP_R100: |
785 | case CHIP_R100: |
| 656 | case CHIP_RV100: |
786 | case CHIP_RV100: |
| 657 | case CHIP_RS100: |
787 | case CHIP_RS100: |
| Line 723... | Line 853... | ||
| 723 | case CHIP_RV730: |
853 | case CHIP_RV730: |
| 724 | case CHIP_RV710: |
854 | case CHIP_RV710: |
| 725 | case CHIP_RV740: |
855 | case CHIP_RV740: |
| 726 | rdev->asic = &rv770_asic; |
856 | rdev->asic = &rv770_asic; |
| 727 | break; |
857 | break; |
| - | 858 | case CHIP_CEDAR: |
|
| - | 859 | case CHIP_REDWOOD: |
|
| - | 860 | case CHIP_JUNIPER: |
|
| - | 861 | case CHIP_CYPRESS: |
|
| - | 862 | case CHIP_HEMLOCK: |
|
| - | 863 | /* set num crtcs */ |
|
| - | 864 | if (rdev->family == CHIP_CEDAR) |
|
| - | 865 | rdev->num_crtc = 4; |
|
| - | 866 | else |
|
| - | 867 | rdev->num_crtc = 6; |
|
| - | 868 | rdev->asic = &evergreen_asic; |
|
| - | 869 | break; |
|
| 728 | default: |
870 | default: |
| 729 | /* FIXME: not supported yet */ |
871 | /* FIXME: not supported yet */ |
| 730 | return -EINVAL; |
872 | return -EINVAL; |
| 731 | } |
873 | } |
| Line 732... | Line 874... | ||
| 732 | 874 | ||
| 733 | if (rdev->flags & RADEON_IS_IGP) { |
875 | if (rdev->flags & RADEON_IS_IGP) { |
| 734 | rdev->asic->get_memory_clock = NULL; |
876 | rdev->asic->get_memory_clock = NULL; |
| 735 | rdev->asic->set_memory_clock = NULL; |
877 | rdev->asic->set_memory_clock = NULL; |
| Line 736... | Line -... | ||
| 736 | } |
- | |
| 737 | - | ||
| 738 | /* set the number of crtcs */ |
- | |
| 739 | if (rdev->flags & RADEON_SINGLE_CRTC) |
- | |
| 740 | rdev->num_crtc = 1; |
- | |
| 741 | else { |
- | |
| 742 | if (ASIC_IS_DCE41(rdev)) |
- | |
| 743 | rdev->num_crtc = 2; |
- | |
| 744 | else if (ASIC_IS_DCE4(rdev)) |
- | |
| 745 | rdev->num_crtc = 6; |
- | |
| 746 | else |
- | |
| 747 | rdev->num_crtc = 2; |
- | |
| 748 | } |
878 | } |
| 749 | 879 | ||