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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __RADEON_H__ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | 30 | ||
31 | /* TODO: Here are things that needs to be done : |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
34 | * related to surface |
34 | * related to surface |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
36 | * - Vblank : look at Jesse's rework and what we should do |
36 | * - Vblank : look at Jesse's rework and what we should do |
37 | * - r600/r700: gart & cp |
37 | * - r600/r700: gart & cp |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
39 | * - power management stuff |
39 | * - power management stuff |
40 | * - Barrier in gart code |
40 | * - Barrier in gart code |
41 | * - Unmappabled vram ? |
41 | * - Unmappabled vram ? |
42 | * - TESTING, TESTING, TESTING |
42 | * - TESTING, TESTING, TESTING |
43 | */ |
43 | */ |
44 | 44 | ||
45 | /* Initialization path: |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
46 | * We expect that acceleration initialization might fail for various |
47 | * reasons even thought we work hard to make it works on most |
47 | * reasons even thought we work hard to make it works on most |
48 | * configurations. In order to still have a working userspace in such |
48 | * configurations. In order to still have a working userspace in such |
49 | * situation the init path must succeed up to the memory controller |
49 | * situation the init path must succeed up to the memory controller |
50 | * initialization point. Failure before this point are considered as |
50 | * initialization point. Failure before this point are considered as |
51 | * fatal error. Here is the init callchain : |
51 | * fatal error. Here is the init callchain : |
52 | * radeon_device_init perform common structure, mutex initialization |
52 | * radeon_device_init perform common structure, mutex initialization |
53 | * asic_init setup the GPU memory layout and perform all |
53 | * asic_init setup the GPU memory layout and perform all |
54 | * one time initialization (failure in this |
54 | * one time initialization (failure in this |
55 | * function are considered fatal) |
55 | * function are considered fatal) |
56 | * asic_startup setup the GPU acceleration, in order to |
56 | * asic_startup setup the GPU acceleration, in order to |
57 | * follow guideline the first thing this |
57 | * follow guideline the first thing this |
58 | * function should do is setting the GPU |
58 | * function should do is setting the GPU |
59 | * memory controller (only MC setup failure |
59 | * memory controller (only MC setup failure |
60 | * are considered as fatal) |
60 | * are considered as fatal) |
61 | */ |
61 | */ |
62 | 62 | ||
63 | #include |
63 | #include |
64 | #include |
64 | #include |
65 | #include |
65 | #include |
66 | #include |
66 | #include |
67 | #include |
67 | #include |
68 | #include |
68 | #include |
69 | 69 | ||
70 | #include |
70 | #include |
71 | #include |
71 | #include |
72 | #include |
72 | #include |
73 | //#include |
73 | //#include |
74 | #include |
74 | #include |
75 | 75 | ||
76 | #include |
76 | #include |
77 | #include |
77 | #include |
78 | 78 | ||
79 | #include |
79 | #include |
80 | 80 | ||
81 | #include "radeon_family.h" |
81 | #include "radeon_family.h" |
82 | #include "radeon_mode.h" |
82 | #include "radeon_mode.h" |
83 | #include "radeon_reg.h" |
83 | #include "radeon_reg.h" |
84 | 84 | ||
85 | #include |
85 | #include |
86 | 86 | ||
87 | /* |
87 | /* |
88 | * Modules parameters. |
88 | * Modules parameters. |
89 | */ |
89 | */ |
90 | extern int radeon_no_wb; |
90 | extern int radeon_no_wb; |
91 | extern int radeon_modeset; |
91 | extern int radeon_modeset; |
92 | extern int radeon_dynclks; |
92 | extern int radeon_dynclks; |
93 | extern int radeon_r4xx_atom; |
93 | extern int radeon_r4xx_atom; |
94 | extern int radeon_agpmode; |
94 | extern int radeon_agpmode; |
95 | extern int radeon_vram_limit; |
95 | extern int radeon_vram_limit; |
96 | extern int radeon_gart_size; |
96 | extern int radeon_gart_size; |
97 | extern int radeon_benchmarking; |
97 | extern int radeon_benchmarking; |
98 | extern int radeon_testing; |
98 | extern int radeon_testing; |
99 | extern int radeon_connector_table; |
99 | extern int radeon_connector_table; |
100 | extern int radeon_tv; |
100 | extern int radeon_tv; |
101 | extern int radeon_audio; |
101 | extern int radeon_audio; |
102 | extern int radeon_disp_priority; |
102 | extern int radeon_disp_priority; |
103 | extern int radeon_hw_i2c; |
103 | extern int radeon_hw_i2c; |
104 | extern int radeon_pcie_gen2; |
104 | extern int radeon_pcie_gen2; |
105 | extern int radeon_msi; |
105 | extern int radeon_msi; |
106 | extern int radeon_lockup_timeout; |
106 | extern int radeon_lockup_timeout; |
107 | extern int radeon_fastfb; |
107 | extern int radeon_fastfb; |
108 | extern int radeon_dpm; |
108 | extern int radeon_dpm; |
109 | extern int radeon_aspm; |
109 | extern int radeon_aspm; |
110 | extern int radeon_runtime_pm; |
110 | extern int radeon_runtime_pm; |
111 | extern int radeon_hard_reset; |
111 | extern int radeon_hard_reset; |
112 | extern int radeon_vm_size; |
112 | extern int radeon_vm_size; |
113 | extern int radeon_vm_block_size; |
113 | extern int radeon_vm_block_size; |
114 | extern int radeon_deep_color; |
114 | extern int radeon_deep_color; |
115 | extern int radeon_use_pflipirq; |
115 | extern int radeon_use_pflipirq; |
116 | extern int radeon_bapm; |
116 | extern int radeon_bapm; |
- | 117 | extern int radeon_backlight; |
|
117 | 118 | ||
118 | 119 | ||
119 | typedef struct pm_message { |
120 | typedef struct pm_message { |
120 | int event; |
121 | int event; |
121 | } pm_message_t; |
122 | } pm_message_t; |
122 | 123 | ||
123 | typedef struct |
124 | typedef struct |
124 | { |
125 | { |
125 | int width; |
126 | int width; |
126 | int height; |
127 | int height; |
127 | int bpp; |
128 | int bpp; |
128 | int freq; |
129 | int freq; |
129 | }videomode_t; |
130 | }videomode_t; |
130 | 131 | ||
131 | 132 | ||
132 | 133 | ||
133 | static inline u32 ioread32(const volatile void __iomem *addr) |
134 | static inline u32 ioread32(const volatile void __iomem *addr) |
134 | { |
135 | { |
135 | return in32((u32)addr); |
136 | return in32((u32)addr); |
136 | } |
137 | } |
137 | 138 | ||
138 | //static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
139 | //static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
139 | //{ |
140 | //{ |
140 | // out32((u32)addr, b); |
141 | // out32((u32)addr, b); |
141 | //} |
142 | //} |
142 | 143 | ||
143 | 144 | ||
144 | /* |
145 | /* |
145 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
146 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
146 | * symbol; |
147 | * symbol; |
147 | */ |
148 | */ |
148 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
149 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
149 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
150 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
150 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
151 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
151 | #define RADEON_IB_POOL_SIZE 16 |
152 | #define RADEON_IB_POOL_SIZE 16 |
152 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
153 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
153 | #define RADEONFB_CONN_LIMIT 4 |
154 | #define RADEONFB_CONN_LIMIT 4 |
154 | #define RADEON_BIOS_NUM_SCRATCH 8 |
155 | #define RADEON_BIOS_NUM_SCRATCH 8 |
155 | 156 | ||
156 | /* fence seq are set to this number when signaled */ |
157 | /* fence seq are set to this number when signaled */ |
157 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
158 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
158 | 159 | ||
159 | /* internal ring indices */ |
160 | /* internal ring indices */ |
160 | /* r1xx+ has gfx CP ring */ |
161 | /* r1xx+ has gfx CP ring */ |
161 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
162 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
162 | 163 | ||
163 | /* cayman has 2 compute CP rings */ |
164 | /* cayman has 2 compute CP rings */ |
164 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
165 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
165 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
166 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
166 | 167 | ||
167 | /* R600+ has an async dma ring */ |
168 | /* R600+ has an async dma ring */ |
168 | #define R600_RING_TYPE_DMA_INDEX 3 |
169 | #define R600_RING_TYPE_DMA_INDEX 3 |
169 | /* cayman add a second async dma ring */ |
170 | /* cayman add a second async dma ring */ |
170 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
171 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
171 | 172 | ||
172 | /* R600+ */ |
173 | /* R600+ */ |
173 | #define R600_RING_TYPE_UVD_INDEX 5 |
174 | #define R600_RING_TYPE_UVD_INDEX 5 |
174 | 175 | ||
175 | /* TN+ */ |
176 | /* TN+ */ |
176 | #define TN_RING_TYPE_VCE1_INDEX 6 |
177 | #define TN_RING_TYPE_VCE1_INDEX 6 |
177 | #define TN_RING_TYPE_VCE2_INDEX 7 |
178 | #define TN_RING_TYPE_VCE2_INDEX 7 |
178 | 179 | ||
179 | /* max number of rings */ |
180 | /* max number of rings */ |
180 | #define RADEON_NUM_RINGS 8 |
181 | #define RADEON_NUM_RINGS 8 |
181 | 182 | ||
182 | /* number of hw syncs before falling back on blocking */ |
183 | /* number of hw syncs before falling back on blocking */ |
183 | #define RADEON_NUM_SYNCS 4 |
184 | #define RADEON_NUM_SYNCS 4 |
184 | 185 | ||
185 | /* number of hw syncs before falling back on blocking */ |
186 | /* number of hw syncs before falling back on blocking */ |
186 | #define RADEON_NUM_SYNCS 4 |
187 | #define RADEON_NUM_SYNCS 4 |
187 | 188 | ||
188 | /* hardcode those limit for now */ |
189 | /* hardcode those limit for now */ |
189 | #define RADEON_VA_IB_OFFSET (1 << 20) |
190 | #define RADEON_VA_IB_OFFSET (1 << 20) |
190 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
191 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
191 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
192 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
192 | 193 | ||
193 | /* hard reset data */ |
194 | /* hard reset data */ |
194 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
195 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
195 | 196 | ||
196 | /* reset flags */ |
197 | /* reset flags */ |
197 | #define RADEON_RESET_GFX (1 << 0) |
198 | #define RADEON_RESET_GFX (1 << 0) |
198 | #define RADEON_RESET_COMPUTE (1 << 1) |
199 | #define RADEON_RESET_COMPUTE (1 << 1) |
199 | #define RADEON_RESET_DMA (1 << 2) |
200 | #define RADEON_RESET_DMA (1 << 2) |
200 | #define RADEON_RESET_CP (1 << 3) |
201 | #define RADEON_RESET_CP (1 << 3) |
201 | #define RADEON_RESET_GRBM (1 << 4) |
202 | #define RADEON_RESET_GRBM (1 << 4) |
202 | #define RADEON_RESET_DMA1 (1 << 5) |
203 | #define RADEON_RESET_DMA1 (1 << 5) |
203 | #define RADEON_RESET_RLC (1 << 6) |
204 | #define RADEON_RESET_RLC (1 << 6) |
204 | #define RADEON_RESET_SEM (1 << 7) |
205 | #define RADEON_RESET_SEM (1 << 7) |
205 | #define RADEON_RESET_IH (1 << 8) |
206 | #define RADEON_RESET_IH (1 << 8) |
206 | #define RADEON_RESET_VMC (1 << 9) |
207 | #define RADEON_RESET_VMC (1 << 9) |
207 | #define RADEON_RESET_MC (1 << 10) |
208 | #define RADEON_RESET_MC (1 << 10) |
208 | #define RADEON_RESET_DISPLAY (1 << 11) |
209 | #define RADEON_RESET_DISPLAY (1 << 11) |
209 | 210 | ||
210 | /* CG block flags */ |
211 | /* CG block flags */ |
211 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
212 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
212 | #define RADEON_CG_BLOCK_MC (1 << 1) |
213 | #define RADEON_CG_BLOCK_MC (1 << 1) |
213 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
214 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
214 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
215 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
215 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
216 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
216 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
217 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
217 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
218 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
218 | 219 | ||
219 | /* CG flags */ |
220 | /* CG flags */ |
220 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
221 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
221 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
222 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
222 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
223 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
223 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
224 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
224 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
225 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
225 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
226 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
226 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
227 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
227 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
228 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
228 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
229 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
229 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
230 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
230 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
231 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
231 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
232 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
232 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
233 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
233 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
234 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
234 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
235 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
235 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
236 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
236 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
237 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
237 | 238 | ||
238 | /* PG flags */ |
239 | /* PG flags */ |
239 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
240 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
240 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
241 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
241 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
242 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
242 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
243 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
243 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
244 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
244 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
245 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
245 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
246 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
246 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
247 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
247 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
248 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
248 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
249 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
249 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
250 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
250 | 251 | ||
251 | /* max cursor sizes (in pixels) */ |
252 | /* max cursor sizes (in pixels) */ |
252 | #define CURSOR_WIDTH 64 |
253 | #define CURSOR_WIDTH 64 |
253 | #define CURSOR_HEIGHT 64 |
254 | #define CURSOR_HEIGHT 64 |
254 | 255 | ||
255 | #define CIK_CURSOR_WIDTH 128 |
256 | #define CIK_CURSOR_WIDTH 128 |
256 | #define CIK_CURSOR_HEIGHT 128 |
257 | #define CIK_CURSOR_HEIGHT 128 |
257 | 258 | ||
258 | /* |
259 | /* |
259 | * Errata workarounds. |
260 | * Errata workarounds. |
260 | */ |
261 | */ |
261 | enum radeon_pll_errata { |
262 | enum radeon_pll_errata { |
262 | CHIP_ERRATA_R300_CG = 0x00000001, |
263 | CHIP_ERRATA_R300_CG = 0x00000001, |
263 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
264 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
264 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
265 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
265 | }; |
266 | }; |
266 | 267 | ||
267 | 268 | ||
268 | struct radeon_device; |
269 | struct radeon_device; |
269 | 270 | ||
270 | 271 | ||
271 | /* |
272 | /* |
272 | * BIOS. |
273 | * BIOS. |
273 | */ |
274 | */ |
274 | bool radeon_get_bios(struct radeon_device *rdev); |
275 | bool radeon_get_bios(struct radeon_device *rdev); |
275 | 276 | ||
276 | /* |
277 | /* |
277 | * Dummy page |
278 | * Dummy page |
278 | */ |
279 | */ |
279 | struct radeon_dummy_page { |
280 | struct radeon_dummy_page { |
280 | struct page *page; |
281 | struct page *page; |
281 | dma_addr_t addr; |
282 | dma_addr_t addr; |
282 | }; |
283 | }; |
283 | int radeon_dummy_page_init(struct radeon_device *rdev); |
284 | int radeon_dummy_page_init(struct radeon_device *rdev); |
284 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
285 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
285 | 286 | ||
286 | 287 | ||
287 | /* |
288 | /* |
288 | * Clocks |
289 | * Clocks |
289 | */ |
290 | */ |
290 | struct radeon_clock { |
291 | struct radeon_clock { |
291 | struct radeon_pll p1pll; |
292 | struct radeon_pll p1pll; |
292 | struct radeon_pll p2pll; |
293 | struct radeon_pll p2pll; |
293 | struct radeon_pll dcpll; |
294 | struct radeon_pll dcpll; |
294 | struct radeon_pll spll; |
295 | struct radeon_pll spll; |
295 | struct radeon_pll mpll; |
296 | struct radeon_pll mpll; |
296 | /* 10 Khz units */ |
297 | /* 10 Khz units */ |
297 | uint32_t default_mclk; |
298 | uint32_t default_mclk; |
298 | uint32_t default_sclk; |
299 | uint32_t default_sclk; |
299 | uint32_t default_dispclk; |
300 | uint32_t default_dispclk; |
300 | uint32_t current_dispclk; |
301 | uint32_t current_dispclk; |
301 | uint32_t dp_extclk; |
302 | uint32_t dp_extclk; |
302 | uint32_t max_pixel_clock; |
303 | uint32_t max_pixel_clock; |
303 | }; |
304 | }; |
304 | 305 | ||
305 | /* |
306 | /* |
306 | * Power management |
307 | * Power management |
307 | */ |
308 | */ |
308 | int radeon_pm_init(struct radeon_device *rdev); |
309 | int radeon_pm_init(struct radeon_device *rdev); |
309 | int radeon_pm_late_init(struct radeon_device *rdev); |
310 | int radeon_pm_late_init(struct radeon_device *rdev); |
310 | void radeon_pm_fini(struct radeon_device *rdev); |
311 | void radeon_pm_fini(struct radeon_device *rdev); |
311 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
312 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
312 | void radeon_pm_suspend(struct radeon_device *rdev); |
313 | void radeon_pm_suspend(struct radeon_device *rdev); |
313 | void radeon_pm_resume(struct radeon_device *rdev); |
314 | void radeon_pm_resume(struct radeon_device *rdev); |
314 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
315 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
315 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
316 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
316 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
317 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
317 | u8 clock_type, |
318 | u8 clock_type, |
318 | u32 clock, |
319 | u32 clock, |
319 | bool strobe_mode, |
320 | bool strobe_mode, |
320 | struct atom_clock_dividers *dividers); |
321 | struct atom_clock_dividers *dividers); |
321 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
322 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
322 | u32 clock, |
323 | u32 clock, |
323 | bool strobe_mode, |
324 | bool strobe_mode, |
324 | struct atom_mpll_param *mpll_param); |
325 | struct atom_mpll_param *mpll_param); |
325 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
326 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
326 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
327 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
327 | u16 voltage_level, u8 voltage_type, |
328 | u16 voltage_level, u8 voltage_type, |
328 | u32 *gpio_value, u32 *gpio_mask); |
329 | u32 *gpio_value, u32 *gpio_mask); |
329 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
330 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
330 | u32 eng_clock, u32 mem_clock); |
331 | u32 eng_clock, u32 mem_clock); |
331 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
332 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
332 | u8 voltage_type, u16 *voltage_step); |
333 | u8 voltage_type, u16 *voltage_step); |
333 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
334 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
334 | u16 voltage_id, u16 *voltage); |
335 | u16 voltage_id, u16 *voltage); |
335 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
336 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
336 | u16 *voltage, |
337 | u16 *voltage, |
337 | u16 leakage_idx); |
338 | u16 leakage_idx); |
338 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
339 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
339 | u16 *leakage_id); |
340 | u16 *leakage_id); |
340 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
341 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
341 | u16 *vddc, u16 *vddci, |
342 | u16 *vddc, u16 *vddci, |
342 | u16 virtual_voltage_id, |
343 | u16 virtual_voltage_id, |
343 | u16 vbios_voltage_id); |
344 | u16 vbios_voltage_id); |
344 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
345 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
345 | u16 virtual_voltage_id, |
346 | u16 virtual_voltage_id, |
346 | u16 *voltage); |
347 | u16 *voltage); |
347 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
348 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
348 | u8 voltage_type, |
349 | u8 voltage_type, |
349 | u16 nominal_voltage, |
350 | u16 nominal_voltage, |
350 | u16 *true_voltage); |
351 | u16 *true_voltage); |
351 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
352 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
352 | u8 voltage_type, u16 *min_voltage); |
353 | u8 voltage_type, u16 *min_voltage); |
353 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
354 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
354 | u8 voltage_type, u16 *max_voltage); |
355 | u8 voltage_type, u16 *max_voltage); |
355 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
356 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
356 | u8 voltage_type, u8 voltage_mode, |
357 | u8 voltage_type, u8 voltage_mode, |
357 | struct atom_voltage_table *voltage_table); |
358 | struct atom_voltage_table *voltage_table); |
358 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
359 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
359 | u8 voltage_type, u8 voltage_mode); |
360 | u8 voltage_type, u8 voltage_mode); |
360 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
361 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
361 | u8 voltage_type, |
362 | u8 voltage_type, |
362 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
363 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
363 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
364 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
364 | u32 mem_clock); |
365 | u32 mem_clock); |
365 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
366 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
366 | u32 mem_clock); |
367 | u32 mem_clock); |
367 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
368 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
368 | u8 module_index, |
369 | u8 module_index, |
369 | struct atom_mc_reg_table *reg_table); |
370 | struct atom_mc_reg_table *reg_table); |
370 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
371 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
371 | u8 module_index, struct atom_memory_info *mem_info); |
372 | u8 module_index, struct atom_memory_info *mem_info); |
372 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
373 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
373 | bool gddr5, u8 module_index, |
374 | bool gddr5, u8 module_index, |
374 | struct atom_memory_clock_range_table *mclk_range_table); |
375 | struct atom_memory_clock_range_table *mclk_range_table); |
375 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
376 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
376 | u16 voltage_id, u16 *voltage); |
377 | u16 voltage_id, u16 *voltage); |
377 | void rs690_pm_info(struct radeon_device *rdev); |
378 | void rs690_pm_info(struct radeon_device *rdev); |
378 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
379 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
379 | unsigned *bankh, unsigned *mtaspect, |
380 | unsigned *bankh, unsigned *mtaspect, |
380 | unsigned *tile_split); |
381 | unsigned *tile_split); |
381 | 382 | ||
382 | /* |
383 | /* |
383 | * Fences. |
384 | * Fences. |
384 | */ |
385 | */ |
385 | struct radeon_fence_driver { |
386 | struct radeon_fence_driver { |
386 | uint32_t scratch_reg; |
387 | uint32_t scratch_reg; |
387 | uint64_t gpu_addr; |
388 | uint64_t gpu_addr; |
388 | volatile uint32_t *cpu_addr; |
389 | volatile uint32_t *cpu_addr; |
389 | /* sync_seq is protected by ring emission lock */ |
390 | /* sync_seq is protected by ring emission lock */ |
390 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
391 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
391 | atomic64_t last_seq; |
392 | atomic64_t last_seq; |
392 | bool initialized; |
393 | bool initialized; |
393 | }; |
394 | }; |
394 | 395 | ||
395 | struct radeon_fence { |
396 | struct radeon_fence { |
396 | struct radeon_device *rdev; |
397 | struct radeon_device *rdev; |
397 | struct kref kref; |
398 | struct kref kref; |
398 | /* protected by radeon_fence.lock */ |
399 | /* protected by radeon_fence.lock */ |
399 | uint64_t seq; |
400 | uint64_t seq; |
400 | /* RB, DMA, etc. */ |
401 | /* RB, DMA, etc. */ |
401 | unsigned ring; |
402 | unsigned ring; |
402 | }; |
403 | }; |
403 | 404 | ||
404 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
405 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
405 | int radeon_fence_driver_init(struct radeon_device *rdev); |
406 | int radeon_fence_driver_init(struct radeon_device *rdev); |
406 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
407 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
407 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
408 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
408 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
409 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
409 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
410 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
410 | bool radeon_fence_signaled(struct radeon_fence *fence); |
411 | bool radeon_fence_signaled(struct radeon_fence *fence); |
411 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
412 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
412 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
413 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
413 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
414 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
414 | int radeon_fence_wait_any(struct radeon_device *rdev, |
415 | int radeon_fence_wait_any(struct radeon_device *rdev, |
415 | struct radeon_fence **fences, |
416 | struct radeon_fence **fences, |
416 | bool intr); |
417 | bool intr); |
417 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
418 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
418 | void radeon_fence_unref(struct radeon_fence **fence); |
419 | void radeon_fence_unref(struct radeon_fence **fence); |
419 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
420 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
420 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
421 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
421 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
422 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
422 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
423 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
423 | struct radeon_fence *b) |
424 | struct radeon_fence *b) |
424 | { |
425 | { |
425 | if (!a) { |
426 | if (!a) { |
426 | return b; |
427 | return b; |
427 | } |
428 | } |
428 | 429 | ||
429 | if (!b) { |
430 | if (!b) { |
430 | return a; |
431 | return a; |
431 | } |
432 | } |
432 | 433 | ||
433 | BUG_ON(a->ring != b->ring); |
434 | BUG_ON(a->ring != b->ring); |
434 | 435 | ||
435 | if (a->seq > b->seq) { |
436 | if (a->seq > b->seq) { |
436 | return a; |
437 | return a; |
437 | } else { |
438 | } else { |
438 | return b; |
439 | return b; |
439 | } |
440 | } |
440 | } |
441 | } |
441 | 442 | ||
442 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
443 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
443 | struct radeon_fence *b) |
444 | struct radeon_fence *b) |
444 | { |
445 | { |
445 | if (!a) { |
446 | if (!a) { |
446 | return false; |
447 | return false; |
447 | } |
448 | } |
448 | 449 | ||
449 | if (!b) { |
450 | if (!b) { |
450 | return true; |
451 | return true; |
451 | } |
452 | } |
452 | 453 | ||
453 | BUG_ON(a->ring != b->ring); |
454 | BUG_ON(a->ring != b->ring); |
454 | 455 | ||
455 | return a->seq < b->seq; |
456 | return a->seq < b->seq; |
456 | } |
457 | } |
457 | 458 | ||
458 | /* |
459 | /* |
459 | * Tiling registers |
460 | * Tiling registers |
460 | */ |
461 | */ |
461 | struct radeon_surface_reg { |
462 | struct radeon_surface_reg { |
462 | struct radeon_bo *bo; |
463 | struct radeon_bo *bo; |
463 | }; |
464 | }; |
464 | 465 | ||
465 | #define RADEON_GEM_MAX_SURFACES 8 |
466 | #define RADEON_GEM_MAX_SURFACES 8 |
466 | 467 | ||
467 | /* |
468 | /* |
468 | * TTM. |
469 | * TTM. |
469 | */ |
470 | */ |
470 | struct radeon_mman { |
471 | struct radeon_mman { |
471 | struct ttm_bo_global_ref bo_global_ref; |
472 | struct ttm_bo_global_ref bo_global_ref; |
472 | struct drm_global_reference mem_global_ref; |
473 | struct drm_global_reference mem_global_ref; |
473 | struct ttm_bo_device bdev; |
474 | struct ttm_bo_device bdev; |
474 | bool mem_global_referenced; |
475 | bool mem_global_referenced; |
475 | bool initialized; |
476 | bool initialized; |
476 | 477 | ||
477 | #if defined(CONFIG_DEBUG_FS) |
478 | #if defined(CONFIG_DEBUG_FS) |
478 | struct dentry *vram; |
479 | struct dentry *vram; |
479 | struct dentry *gtt; |
480 | struct dentry *gtt; |
480 | #endif |
481 | #endif |
481 | }; |
482 | }; |
482 | 483 | ||
483 | /* bo virtual address in a specific vm */ |
484 | /* bo virtual address in a specific vm */ |
484 | struct radeon_bo_va { |
485 | struct radeon_bo_va { |
485 | /* protected by bo being reserved */ |
486 | /* protected by bo being reserved */ |
486 | struct list_head bo_list; |
487 | struct list_head bo_list; |
487 | uint32_t flags; |
488 | uint32_t flags; |
488 | uint64_t addr; |
489 | uint64_t addr; |
489 | unsigned ref_count; |
490 | unsigned ref_count; |
490 | 491 | ||
491 | /* protected by vm mutex */ |
492 | /* protected by vm mutex */ |
492 | struct interval_tree_node it; |
493 | struct interval_tree_node it; |
493 | struct list_head vm_status; |
494 | struct list_head vm_status; |
494 | 495 | ||
495 | /* constant after initialization */ |
496 | /* constant after initialization */ |
496 | struct radeon_vm *vm; |
497 | struct radeon_vm *vm; |
497 | struct radeon_bo *bo; |
498 | struct radeon_bo *bo; |
498 | }; |
499 | }; |
499 | 500 | ||
500 | struct radeon_bo { |
501 | struct radeon_bo { |
501 | /* Protected by gem.mutex */ |
502 | /* Protected by gem.mutex */ |
502 | struct list_head list; |
503 | struct list_head list; |
503 | /* Protected by tbo.reserved */ |
504 | /* Protected by tbo.reserved */ |
504 | u32 initial_domain; |
505 | u32 initial_domain; |
505 | u32 placements[3]; |
506 | u32 placements[3]; |
506 | struct ttm_placement placement; |
507 | struct ttm_placement placement; |
507 | struct ttm_buffer_object tbo; |
508 | struct ttm_buffer_object tbo; |
508 | struct ttm_bo_kmap_obj kmap; |
509 | struct ttm_bo_kmap_obj kmap; |
509 | u32 flags; |
510 | u32 flags; |
510 | unsigned pin_count; |
511 | unsigned pin_count; |
511 | void *kptr; |
512 | void *kptr; |
512 | u32 tiling_flags; |
513 | u32 tiling_flags; |
513 | u32 pitch; |
514 | u32 pitch; |
514 | int surface_reg; |
515 | int surface_reg; |
515 | /* list of all virtual address to which this bo |
516 | /* list of all virtual address to which this bo |
516 | * is associated to |
517 | * is associated to |
517 | */ |
518 | */ |
518 | struct list_head va; |
519 | struct list_head va; |
519 | /* Constant after initialization */ |
520 | /* Constant after initialization */ |
520 | struct radeon_device *rdev; |
521 | struct radeon_device *rdev; |
521 | struct drm_gem_object gem_base; |
522 | struct drm_gem_object gem_base; |
522 | 523 | ||
523 | pid_t pid; |
524 | pid_t pid; |
524 | }; |
525 | }; |
525 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
526 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
526 | 527 | ||
527 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
528 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
528 | 529 | ||
529 | /* sub-allocation manager, it has to be protected by another lock. |
530 | /* sub-allocation manager, it has to be protected by another lock. |
530 | * By conception this is an helper for other part of the driver |
531 | * By conception this is an helper for other part of the driver |
531 | * like the indirect buffer or semaphore, which both have their |
532 | * like the indirect buffer or semaphore, which both have their |
532 | * locking. |
533 | * locking. |
533 | * |
534 | * |
534 | * Principe is simple, we keep a list of sub allocation in offset |
535 | * Principe is simple, we keep a list of sub allocation in offset |
535 | * order (first entry has offset == 0, last entry has the highest |
536 | * order (first entry has offset == 0, last entry has the highest |
536 | * offset). |
537 | * offset). |
537 | * |
538 | * |
538 | * When allocating new object we first check if there is room at |
539 | * When allocating new object we first check if there is room at |
539 | * the end total_size - (last_object_offset + last_object_size) >= |
540 | * the end total_size - (last_object_offset + last_object_size) >= |
540 | * alloc_size. If so we allocate new object there. |
541 | * alloc_size. If so we allocate new object there. |
541 | * |
542 | * |
542 | * When there is not enough room at the end, we start waiting for |
543 | * When there is not enough room at the end, we start waiting for |
543 | * each sub object until we reach object_offset+object_size >= |
544 | * each sub object until we reach object_offset+object_size >= |
544 | * alloc_size, this object then become the sub object we return. |
545 | * alloc_size, this object then become the sub object we return. |
545 | * |
546 | * |
546 | * Alignment can't be bigger than page size. |
547 | * Alignment can't be bigger than page size. |
547 | * |
548 | * |
548 | * Hole are not considered for allocation to keep things simple. |
549 | * Hole are not considered for allocation to keep things simple. |
549 | * Assumption is that there won't be hole (all object on same |
550 | * Assumption is that there won't be hole (all object on same |
550 | * alignment). |
551 | * alignment). |
551 | */ |
552 | */ |
552 | struct radeon_sa_manager { |
553 | struct radeon_sa_manager { |
553 | wait_queue_head_t wq; |
554 | wait_queue_head_t wq; |
554 | struct radeon_bo *bo; |
555 | struct radeon_bo *bo; |
555 | struct list_head *hole; |
556 | struct list_head *hole; |
556 | struct list_head flist[RADEON_NUM_RINGS]; |
557 | struct list_head flist[RADEON_NUM_RINGS]; |
557 | struct list_head olist; |
558 | struct list_head olist; |
558 | unsigned size; |
559 | unsigned size; |
559 | uint64_t gpu_addr; |
560 | uint64_t gpu_addr; |
560 | void *cpu_ptr; |
561 | void *cpu_ptr; |
561 | uint32_t domain; |
562 | uint32_t domain; |
562 | uint32_t align; |
563 | uint32_t align; |
563 | }; |
564 | }; |
564 | 565 | ||
565 | struct radeon_sa_bo; |
566 | struct radeon_sa_bo; |
566 | 567 | ||
567 | /* sub-allocation buffer */ |
568 | /* sub-allocation buffer */ |
568 | struct radeon_sa_bo { |
569 | struct radeon_sa_bo { |
569 | struct list_head olist; |
570 | struct list_head olist; |
570 | struct list_head flist; |
571 | struct list_head flist; |
571 | struct radeon_sa_manager *manager; |
572 | struct radeon_sa_manager *manager; |
572 | unsigned soffset; |
573 | unsigned soffset; |
573 | unsigned eoffset; |
574 | unsigned eoffset; |
574 | struct radeon_fence *fence; |
575 | struct radeon_fence *fence; |
575 | }; |
576 | }; |
576 | 577 | ||
577 | /* |
578 | /* |
578 | * GEM objects. |
579 | * GEM objects. |
579 | */ |
580 | */ |
580 | struct radeon_gem { |
581 | struct radeon_gem { |
581 | struct mutex mutex; |
582 | struct mutex mutex; |
582 | struct list_head objects; |
583 | struct list_head objects; |
583 | }; |
584 | }; |
584 | 585 | ||
585 | int radeon_gem_init(struct radeon_device *rdev); |
586 | int radeon_gem_init(struct radeon_device *rdev); |
586 | void radeon_gem_fini(struct radeon_device *rdev); |
587 | void radeon_gem_fini(struct radeon_device *rdev); |
587 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
588 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
588 | int alignment, int initial_domain, |
589 | int alignment, int initial_domain, |
589 | u32 flags, bool kernel, |
590 | u32 flags, bool kernel, |
590 | struct drm_gem_object **obj); |
591 | struct drm_gem_object **obj); |
591 | 592 | ||
592 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
593 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
593 | struct drm_device *dev, |
594 | struct drm_device *dev, |
594 | struct drm_mode_create_dumb *args); |
595 | struct drm_mode_create_dumb *args); |
595 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
596 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
596 | struct drm_device *dev, |
597 | struct drm_device *dev, |
597 | uint32_t handle, uint64_t *offset_p); |
598 | uint32_t handle, uint64_t *offset_p); |
598 | 599 | ||
599 | /* |
600 | /* |
600 | * Semaphores. |
601 | * Semaphores. |
601 | */ |
602 | */ |
602 | struct radeon_semaphore { |
603 | struct radeon_semaphore { |
603 | struct radeon_sa_bo *sa_bo; |
604 | struct radeon_sa_bo *sa_bo; |
604 | signed waiters; |
605 | signed waiters; |
605 | uint64_t gpu_addr; |
606 | uint64_t gpu_addr; |
606 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
607 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
607 | }; |
608 | }; |
608 | 609 | ||
609 | int radeon_semaphore_create(struct radeon_device *rdev, |
610 | int radeon_semaphore_create(struct radeon_device *rdev, |
610 | struct radeon_semaphore **semaphore); |
611 | struct radeon_semaphore **semaphore); |
611 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
612 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
612 | struct radeon_semaphore *semaphore); |
613 | struct radeon_semaphore *semaphore); |
613 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
614 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
614 | struct radeon_semaphore *semaphore); |
615 | struct radeon_semaphore *semaphore); |
615 | void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, |
616 | void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, |
616 | struct radeon_fence *fence); |
617 | struct radeon_fence *fence); |
617 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
618 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
618 | struct radeon_semaphore *semaphore, |
619 | struct radeon_semaphore *semaphore, |
619 | int waiting_ring); |
620 | int waiting_ring); |
620 | void radeon_semaphore_free(struct radeon_device *rdev, |
621 | void radeon_semaphore_free(struct radeon_device *rdev, |
621 | struct radeon_semaphore **semaphore, |
622 | struct radeon_semaphore **semaphore, |
622 | struct radeon_fence *fence); |
623 | struct radeon_fence *fence); |
623 | 624 | ||
624 | /* |
625 | /* |
625 | * GART structures, functions & helpers |
626 | * GART structures, functions & helpers |
626 | */ |
627 | */ |
627 | struct radeon_mc; |
628 | struct radeon_mc; |
628 | 629 | ||
629 | #define RADEON_GPU_PAGE_SIZE 4096 |
630 | #define RADEON_GPU_PAGE_SIZE 4096 |
630 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
631 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
631 | #define RADEON_GPU_PAGE_SHIFT 12 |
632 | #define RADEON_GPU_PAGE_SHIFT 12 |
632 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
633 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
633 | 634 | ||
634 | #define RADEON_GART_PAGE_DUMMY 0 |
635 | #define RADEON_GART_PAGE_DUMMY 0 |
635 | #define RADEON_GART_PAGE_VALID (1 << 0) |
636 | #define RADEON_GART_PAGE_VALID (1 << 0) |
636 | #define RADEON_GART_PAGE_READ (1 << 1) |
637 | #define RADEON_GART_PAGE_READ (1 << 1) |
637 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
638 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
638 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
639 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
639 | 640 | ||
640 | struct radeon_gart { |
641 | struct radeon_gart { |
641 | dma_addr_t table_addr; |
642 | dma_addr_t table_addr; |
642 | struct radeon_bo *robj; |
643 | struct radeon_bo *robj; |
643 | void *ptr; |
644 | void *ptr; |
644 | unsigned num_gpu_pages; |
645 | unsigned num_gpu_pages; |
645 | unsigned num_cpu_pages; |
646 | unsigned num_cpu_pages; |
646 | unsigned table_size; |
647 | unsigned table_size; |
647 | struct page **pages; |
648 | struct page **pages; |
648 | dma_addr_t *pages_addr; |
649 | dma_addr_t *pages_addr; |
649 | bool ready; |
650 | bool ready; |
650 | }; |
651 | }; |
651 | 652 | ||
652 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
653 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
653 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
654 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
654 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
655 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
655 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
656 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
656 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
657 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
657 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
658 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
658 | int radeon_gart_init(struct radeon_device *rdev); |
659 | int radeon_gart_init(struct radeon_device *rdev); |
659 | void radeon_gart_fini(struct radeon_device *rdev); |
660 | void radeon_gart_fini(struct radeon_device *rdev); |
660 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
661 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
661 | int pages); |
662 | int pages); |
662 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
663 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
663 | int pages, struct page **pagelist, |
664 | int pages, struct page **pagelist, |
664 | dma_addr_t *dma_addr, uint32_t flags); |
665 | dma_addr_t *dma_addr, uint32_t flags); |
665 | 666 | ||
666 | 667 | ||
667 | /* |
668 | /* |
668 | * GPU MC structures, functions & helpers |
669 | * GPU MC structures, functions & helpers |
669 | */ |
670 | */ |
670 | struct radeon_mc { |
671 | struct radeon_mc { |
671 | resource_size_t aper_size; |
672 | resource_size_t aper_size; |
672 | resource_size_t aper_base; |
673 | resource_size_t aper_base; |
673 | resource_size_t agp_base; |
674 | resource_size_t agp_base; |
674 | /* for some chips with <= 32MB we need to lie |
675 | /* for some chips with <= 32MB we need to lie |
675 | * about vram size near mc fb location */ |
676 | * about vram size near mc fb location */ |
676 | u64 mc_vram_size; |
677 | u64 mc_vram_size; |
677 | u64 visible_vram_size; |
678 | u64 visible_vram_size; |
678 | u64 gtt_size; |
679 | u64 gtt_size; |
679 | u64 gtt_start; |
680 | u64 gtt_start; |
680 | u64 gtt_end; |
681 | u64 gtt_end; |
681 | u64 vram_start; |
682 | u64 vram_start; |
682 | u64 vram_end; |
683 | u64 vram_end; |
683 | unsigned vram_width; |
684 | unsigned vram_width; |
684 | u64 real_vram_size; |
685 | u64 real_vram_size; |
685 | int vram_mtrr; |
686 | int vram_mtrr; |
686 | bool vram_is_ddr; |
687 | bool vram_is_ddr; |
687 | bool igp_sideport_enabled; |
688 | bool igp_sideport_enabled; |
688 | u64 gtt_base_align; |
689 | u64 gtt_base_align; |
689 | u64 mc_mask; |
690 | u64 mc_mask; |
690 | }; |
691 | }; |
691 | 692 | ||
692 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
693 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
693 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
694 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
694 | 695 | ||
695 | /* |
696 | /* |
696 | * GPU scratch registers structures, functions & helpers |
697 | * GPU scratch registers structures, functions & helpers |
697 | */ |
698 | */ |
698 | struct radeon_scratch { |
699 | struct radeon_scratch { |
699 | unsigned num_reg; |
700 | unsigned num_reg; |
700 | uint32_t reg_base; |
701 | uint32_t reg_base; |
701 | bool free[32]; |
702 | bool free[32]; |
702 | uint32_t reg[32]; |
703 | uint32_t reg[32]; |
703 | }; |
704 | }; |
704 | 705 | ||
705 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
706 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
706 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
707 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
707 | 708 | ||
708 | /* |
709 | /* |
709 | * GPU doorbell structures, functions & helpers |
710 | * GPU doorbell structures, functions & helpers |
710 | */ |
711 | */ |
711 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
712 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
712 | 713 | ||
713 | struct radeon_doorbell { |
714 | struct radeon_doorbell { |
714 | /* doorbell mmio */ |
715 | /* doorbell mmio */ |
715 | resource_size_t base; |
716 | resource_size_t base; |
716 | resource_size_t size; |
717 | resource_size_t size; |
717 | u32 __iomem *ptr; |
718 | u32 __iomem *ptr; |
718 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
719 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
719 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; |
720 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; |
720 | }; |
721 | }; |
721 | 722 | ||
722 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
723 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
723 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
724 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
724 | 725 | ||
725 | /* |
726 | /* |
726 | * IRQS. |
727 | * IRQS. |
727 | */ |
728 | */ |
728 | struct r500_irq_stat_regs { |
729 | struct r500_irq_stat_regs { |
729 | u32 disp_int; |
730 | u32 disp_int; |
730 | u32 hdmi0_status; |
731 | u32 hdmi0_status; |
731 | }; |
732 | }; |
732 | 733 | ||
733 | struct r600_irq_stat_regs { |
734 | struct r600_irq_stat_regs { |
734 | u32 disp_int; |
735 | u32 disp_int; |
735 | u32 disp_int_cont; |
736 | u32 disp_int_cont; |
736 | u32 disp_int_cont2; |
737 | u32 disp_int_cont2; |
737 | u32 d1grph_int; |
738 | u32 d1grph_int; |
738 | u32 d2grph_int; |
739 | u32 d2grph_int; |
739 | u32 hdmi0_status; |
740 | u32 hdmi0_status; |
740 | u32 hdmi1_status; |
741 | u32 hdmi1_status; |
741 | }; |
742 | }; |
742 | 743 | ||
743 | struct evergreen_irq_stat_regs { |
744 | struct evergreen_irq_stat_regs { |
744 | u32 disp_int; |
745 | u32 disp_int; |
745 | u32 disp_int_cont; |
746 | u32 disp_int_cont; |
746 | u32 disp_int_cont2; |
747 | u32 disp_int_cont2; |
747 | u32 disp_int_cont3; |
748 | u32 disp_int_cont3; |
748 | u32 disp_int_cont4; |
749 | u32 disp_int_cont4; |
749 | u32 disp_int_cont5; |
750 | u32 disp_int_cont5; |
750 | u32 d1grph_int; |
751 | u32 d1grph_int; |
751 | u32 d2grph_int; |
752 | u32 d2grph_int; |
752 | u32 d3grph_int; |
753 | u32 d3grph_int; |
753 | u32 d4grph_int; |
754 | u32 d4grph_int; |
754 | u32 d5grph_int; |
755 | u32 d5grph_int; |
755 | u32 d6grph_int; |
756 | u32 d6grph_int; |
756 | u32 afmt_status1; |
757 | u32 afmt_status1; |
757 | u32 afmt_status2; |
758 | u32 afmt_status2; |
758 | u32 afmt_status3; |
759 | u32 afmt_status3; |
759 | u32 afmt_status4; |
760 | u32 afmt_status4; |
760 | u32 afmt_status5; |
761 | u32 afmt_status5; |
761 | u32 afmt_status6; |
762 | u32 afmt_status6; |
762 | }; |
763 | }; |
763 | 764 | ||
764 | struct cik_irq_stat_regs { |
765 | struct cik_irq_stat_regs { |
765 | u32 disp_int; |
766 | u32 disp_int; |
766 | u32 disp_int_cont; |
767 | u32 disp_int_cont; |
767 | u32 disp_int_cont2; |
768 | u32 disp_int_cont2; |
768 | u32 disp_int_cont3; |
769 | u32 disp_int_cont3; |
769 | u32 disp_int_cont4; |
770 | u32 disp_int_cont4; |
770 | u32 disp_int_cont5; |
771 | u32 disp_int_cont5; |
771 | u32 disp_int_cont6; |
772 | u32 disp_int_cont6; |
772 | u32 d1grph_int; |
773 | u32 d1grph_int; |
773 | u32 d2grph_int; |
774 | u32 d2grph_int; |
774 | u32 d3grph_int; |
775 | u32 d3grph_int; |
775 | u32 d4grph_int; |
776 | u32 d4grph_int; |
776 | u32 d5grph_int; |
777 | u32 d5grph_int; |
777 | u32 d6grph_int; |
778 | u32 d6grph_int; |
778 | }; |
779 | }; |
779 | 780 | ||
780 | union radeon_irq_stat_regs { |
781 | union radeon_irq_stat_regs { |
781 | struct r500_irq_stat_regs r500; |
782 | struct r500_irq_stat_regs r500; |
782 | struct r600_irq_stat_regs r600; |
783 | struct r600_irq_stat_regs r600; |
783 | struct evergreen_irq_stat_regs evergreen; |
784 | struct evergreen_irq_stat_regs evergreen; |
784 | struct cik_irq_stat_regs cik; |
785 | struct cik_irq_stat_regs cik; |
785 | }; |
786 | }; |
786 | 787 | ||
787 | struct radeon_irq { |
788 | struct radeon_irq { |
788 | bool installed; |
789 | bool installed; |
789 | spinlock_t lock; |
790 | spinlock_t lock; |
790 | atomic_t ring_int[RADEON_NUM_RINGS]; |
791 | atomic_t ring_int[RADEON_NUM_RINGS]; |
791 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
792 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
792 | atomic_t pflip[RADEON_MAX_CRTCS]; |
793 | atomic_t pflip[RADEON_MAX_CRTCS]; |
793 | wait_queue_head_t vblank_queue; |
794 | wait_queue_head_t vblank_queue; |
794 | bool hpd[RADEON_MAX_HPD_PINS]; |
795 | bool hpd[RADEON_MAX_HPD_PINS]; |
795 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
796 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
796 | union radeon_irq_stat_regs stat_regs; |
797 | union radeon_irq_stat_regs stat_regs; |
797 | bool dpm_thermal; |
798 | bool dpm_thermal; |
798 | }; |
799 | }; |
799 | 800 | ||
800 | int radeon_irq_kms_init(struct radeon_device *rdev); |
801 | int radeon_irq_kms_init(struct radeon_device *rdev); |
801 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
802 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
802 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
803 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
803 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
804 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
804 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
805 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
805 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
806 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
806 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
807 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
807 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
808 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
808 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
809 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
809 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
810 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
810 | 811 | ||
811 | /* |
812 | /* |
812 | * CP & rings. |
813 | * CP & rings. |
813 | */ |
814 | */ |
814 | 815 | ||
815 | struct radeon_ib { |
816 | struct radeon_ib { |
816 | struct radeon_sa_bo *sa_bo; |
817 | struct radeon_sa_bo *sa_bo; |
817 | uint32_t length_dw; |
818 | uint32_t length_dw; |
818 | uint64_t gpu_addr; |
819 | uint64_t gpu_addr; |
819 | uint32_t *ptr; |
820 | uint32_t *ptr; |
820 | int ring; |
821 | int ring; |
821 | struct radeon_fence *fence; |
822 | struct radeon_fence *fence; |
822 | struct radeon_vm *vm; |
823 | struct radeon_vm *vm; |
823 | bool is_const_ib; |
824 | bool is_const_ib; |
824 | struct radeon_semaphore *semaphore; |
825 | struct radeon_semaphore *semaphore; |
825 | }; |
826 | }; |
826 | 827 | ||
827 | struct radeon_ring { |
828 | struct radeon_ring { |
828 | struct radeon_bo *ring_obj; |
829 | struct radeon_bo *ring_obj; |
829 | volatile uint32_t *ring; |
830 | volatile uint32_t *ring; |
830 | unsigned rptr_offs; |
831 | unsigned rptr_offs; |
831 | unsigned rptr_save_reg; |
832 | unsigned rptr_save_reg; |
832 | u64 next_rptr_gpu_addr; |
833 | u64 next_rptr_gpu_addr; |
833 | volatile u32 *next_rptr_cpu_addr; |
834 | volatile u32 *next_rptr_cpu_addr; |
834 | unsigned wptr; |
835 | unsigned wptr; |
835 | unsigned wptr_old; |
836 | unsigned wptr_old; |
836 | unsigned ring_size; |
837 | unsigned ring_size; |
837 | unsigned ring_free_dw; |
838 | unsigned ring_free_dw; |
838 | int count_dw; |
839 | int count_dw; |
839 | atomic_t last_rptr; |
840 | atomic_t last_rptr; |
840 | atomic64_t last_activity; |
841 | atomic64_t last_activity; |
841 | uint64_t gpu_addr; |
842 | uint64_t gpu_addr; |
842 | uint32_t align_mask; |
843 | uint32_t align_mask; |
843 | uint32_t ptr_mask; |
844 | uint32_t ptr_mask; |
844 | bool ready; |
845 | bool ready; |
845 | u32 nop; |
846 | u32 nop; |
846 | u32 idx; |
847 | u32 idx; |
847 | u64 last_semaphore_signal_addr; |
848 | u64 last_semaphore_signal_addr; |
848 | u64 last_semaphore_wait_addr; |
849 | u64 last_semaphore_wait_addr; |
849 | /* for CIK queues */ |
850 | /* for CIK queues */ |
850 | u32 me; |
851 | u32 me; |
851 | u32 pipe; |
852 | u32 pipe; |
852 | u32 queue; |
853 | u32 queue; |
853 | struct radeon_bo *mqd_obj; |
854 | struct radeon_bo *mqd_obj; |
854 | u32 doorbell_index; |
855 | u32 doorbell_index; |
855 | unsigned wptr_offs; |
856 | unsigned wptr_offs; |
856 | }; |
857 | }; |
857 | 858 | ||
858 | struct radeon_mec { |
859 | struct radeon_mec { |
859 | struct radeon_bo *hpd_eop_obj; |
860 | struct radeon_bo *hpd_eop_obj; |
860 | u64 hpd_eop_gpu_addr; |
861 | u64 hpd_eop_gpu_addr; |
861 | u32 num_pipe; |
862 | u32 num_pipe; |
862 | u32 num_mec; |
863 | u32 num_mec; |
863 | u32 num_queue; |
864 | u32 num_queue; |
864 | }; |
865 | }; |
865 | 866 | ||
866 | /* |
867 | /* |
867 | * VM |
868 | * VM |
868 | */ |
869 | */ |
869 | 870 | ||
870 | /* maximum number of VMIDs */ |
871 | /* maximum number of VMIDs */ |
871 | #define RADEON_NUM_VM 16 |
872 | #define RADEON_NUM_VM 16 |
872 | 873 | ||
873 | /* number of entries in page table */ |
874 | /* number of entries in page table */ |
874 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
875 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
875 | 876 | ||
876 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
877 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
877 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
878 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
878 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
879 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
879 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
880 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
880 | 881 | ||
881 | #define R600_PTE_VALID (1 << 0) |
882 | #define R600_PTE_VALID (1 << 0) |
882 | #define R600_PTE_SYSTEM (1 << 1) |
883 | #define R600_PTE_SYSTEM (1 << 1) |
883 | #define R600_PTE_SNOOPED (1 << 2) |
884 | #define R600_PTE_SNOOPED (1 << 2) |
884 | #define R600_PTE_READABLE (1 << 5) |
885 | #define R600_PTE_READABLE (1 << 5) |
885 | #define R600_PTE_WRITEABLE (1 << 6) |
886 | #define R600_PTE_WRITEABLE (1 << 6) |
886 | 887 | ||
887 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
888 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
888 | #define R600_PTE_FRAG_4KB (0 << 7) |
889 | #define R600_PTE_FRAG_4KB (0 << 7) |
889 | #define R600_PTE_FRAG_64KB (4 << 7) |
890 | #define R600_PTE_FRAG_64KB (4 << 7) |
890 | #define R600_PTE_FRAG_256KB (6 << 7) |
891 | #define R600_PTE_FRAG_256KB (6 << 7) |
891 | 892 | ||
892 | /* flags needed to be set so we can copy directly from the GART table */ |
893 | /* flags needed to be set so we can copy directly from the GART table */ |
893 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
894 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
894 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
895 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
895 | 896 | ||
896 | struct radeon_vm_pt { |
897 | struct radeon_vm_pt { |
897 | struct radeon_bo *bo; |
898 | struct radeon_bo *bo; |
898 | uint64_t addr; |
899 | uint64_t addr; |
899 | }; |
900 | }; |
900 | 901 | ||
901 | struct radeon_vm { |
902 | struct radeon_vm { |
902 | struct rb_root va; |
903 | struct rb_root va; |
903 | unsigned id; |
904 | unsigned id; |
904 | 905 | ||
905 | /* BOs moved, but not yet updated in the PT */ |
906 | /* BOs moved, but not yet updated in the PT */ |
906 | struct list_head invalidated; |
907 | struct list_head invalidated; |
907 | 908 | ||
908 | /* BOs freed, but not yet updated in the PT */ |
909 | /* BOs freed, but not yet updated in the PT */ |
909 | struct list_head freed; |
910 | struct list_head freed; |
910 | 911 | ||
911 | /* contains the page directory */ |
912 | /* contains the page directory */ |
912 | struct radeon_bo *page_directory; |
913 | struct radeon_bo *page_directory; |
913 | uint64_t pd_gpu_addr; |
914 | uint64_t pd_gpu_addr; |
914 | unsigned max_pde_used; |
915 | unsigned max_pde_used; |
915 | 916 | ||
916 | /* array of page tables, one for each page directory entry */ |
917 | /* array of page tables, one for each page directory entry */ |
917 | struct radeon_vm_pt *page_tables; |
918 | struct radeon_vm_pt *page_tables; |
918 | 919 | ||
919 | struct radeon_bo_va *ib_bo_va; |
920 | struct radeon_bo_va *ib_bo_va; |
920 | 921 | ||
921 | struct mutex mutex; |
922 | struct mutex mutex; |
922 | /* last fence for cs using this vm */ |
923 | /* last fence for cs using this vm */ |
923 | struct radeon_fence *fence; |
924 | struct radeon_fence *fence; |
924 | /* last flush or NULL if we still need to flush */ |
925 | /* last flush or NULL if we still need to flush */ |
925 | struct radeon_fence *last_flush; |
926 | struct radeon_fence *last_flush; |
926 | /* last use of vmid */ |
927 | /* last use of vmid */ |
927 | struct radeon_fence *last_id_use; |
928 | struct radeon_fence *last_id_use; |
928 | }; |
929 | }; |
929 | 930 | ||
930 | struct radeon_vm_manager { |
931 | struct radeon_vm_manager { |
931 | struct radeon_fence *active[RADEON_NUM_VM]; |
932 | struct radeon_fence *active[RADEON_NUM_VM]; |
932 | uint32_t max_pfn; |
933 | uint32_t max_pfn; |
933 | /* number of VMIDs */ |
934 | /* number of VMIDs */ |
934 | unsigned nvm; |
935 | unsigned nvm; |
935 | /* vram base address for page table entry */ |
936 | /* vram base address for page table entry */ |
936 | u64 vram_base_offset; |
937 | u64 vram_base_offset; |
937 | /* is vm enabled? */ |
938 | /* is vm enabled? */ |
938 | bool enabled; |
939 | bool enabled; |
939 | /* for hw to save the PD addr on suspend/resume */ |
940 | /* for hw to save the PD addr on suspend/resume */ |
940 | uint32_t saved_table_addr[RADEON_NUM_VM]; |
941 | uint32_t saved_table_addr[RADEON_NUM_VM]; |
941 | }; |
942 | }; |
942 | 943 | ||
943 | /* |
944 | /* |
944 | * file private structure |
945 | * file private structure |
945 | */ |
946 | */ |
946 | struct radeon_fpriv { |
947 | struct radeon_fpriv { |
947 | struct radeon_vm vm; |
948 | struct radeon_vm vm; |
948 | }; |
949 | }; |
949 | 950 | ||
950 | /* |
951 | /* |
951 | * R6xx+ IH ring |
952 | * R6xx+ IH ring |
952 | */ |
953 | */ |
953 | struct r600_ih { |
954 | struct r600_ih { |
954 | struct radeon_bo *ring_obj; |
955 | struct radeon_bo *ring_obj; |
955 | volatile uint32_t *ring; |
956 | volatile uint32_t *ring; |
956 | unsigned rptr; |
957 | unsigned rptr; |
957 | unsigned ring_size; |
958 | unsigned ring_size; |
958 | uint64_t gpu_addr; |
959 | uint64_t gpu_addr; |
959 | uint32_t ptr_mask; |
960 | uint32_t ptr_mask; |
960 | atomic_t lock; |
961 | atomic_t lock; |
961 | bool enabled; |
962 | bool enabled; |
962 | }; |
963 | }; |
963 | 964 | ||
964 | /* |
965 | /* |
965 | * RLC stuff |
966 | * RLC stuff |
966 | */ |
967 | */ |
967 | #include "clearstate_defs.h" |
968 | #include "clearstate_defs.h" |
968 | 969 | ||
969 | struct radeon_rlc { |
970 | struct radeon_rlc { |
970 | /* for power gating */ |
971 | /* for power gating */ |
971 | struct radeon_bo *save_restore_obj; |
972 | struct radeon_bo *save_restore_obj; |
972 | uint64_t save_restore_gpu_addr; |
973 | uint64_t save_restore_gpu_addr; |
973 | volatile uint32_t *sr_ptr; |
974 | volatile uint32_t *sr_ptr; |
974 | const u32 *reg_list; |
975 | const u32 *reg_list; |
975 | u32 reg_list_size; |
976 | u32 reg_list_size; |
976 | /* for clear state */ |
977 | /* for clear state */ |
977 | struct radeon_bo *clear_state_obj; |
978 | struct radeon_bo *clear_state_obj; |
978 | uint64_t clear_state_gpu_addr; |
979 | uint64_t clear_state_gpu_addr; |
979 | volatile uint32_t *cs_ptr; |
980 | volatile uint32_t *cs_ptr; |
980 | const struct cs_section_def *cs_data; |
981 | const struct cs_section_def *cs_data; |
981 | u32 clear_state_size; |
982 | u32 clear_state_size; |
982 | /* for cp tables */ |
983 | /* for cp tables */ |
983 | struct radeon_bo *cp_table_obj; |
984 | struct radeon_bo *cp_table_obj; |
984 | uint64_t cp_table_gpu_addr; |
985 | uint64_t cp_table_gpu_addr; |
985 | volatile uint32_t *cp_table_ptr; |
986 | volatile uint32_t *cp_table_ptr; |
986 | u32 cp_table_size; |
987 | u32 cp_table_size; |
987 | }; |
988 | }; |
988 | 989 | ||
989 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
990 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
990 | struct radeon_ib *ib, struct radeon_vm *vm, |
991 | struct radeon_ib *ib, struct radeon_vm *vm, |
991 | unsigned size); |
992 | unsigned size); |
992 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
993 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
993 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
994 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
994 | struct radeon_ib *const_ib, bool hdp_flush); |
995 | struct radeon_ib *const_ib, bool hdp_flush); |
995 | int radeon_ib_pool_init(struct radeon_device *rdev); |
996 | int radeon_ib_pool_init(struct radeon_device *rdev); |
996 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
997 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
997 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
998 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
998 | /* Ring access between begin & end cannot sleep */ |
999 | /* Ring access between begin & end cannot sleep */ |
999 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1000 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1000 | struct radeon_ring *ring); |
1001 | struct radeon_ring *ring); |
1001 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1002 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1002 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1003 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1003 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1004 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1004 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1005 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1005 | bool hdp_flush); |
1006 | bool hdp_flush); |
1006 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1007 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1007 | bool hdp_flush); |
1008 | bool hdp_flush); |
1008 | void radeon_ring_undo(struct radeon_ring *ring); |
1009 | void radeon_ring_undo(struct radeon_ring *ring); |
1009 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1010 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1010 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1011 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1011 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1012 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1012 | struct radeon_ring *ring); |
1013 | struct radeon_ring *ring); |
1013 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
1014 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
1014 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1015 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1015 | uint32_t **data); |
1016 | uint32_t **data); |
1016 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
1017 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
1017 | unsigned size, uint32_t *data); |
1018 | unsigned size, uint32_t *data); |
1018 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
1019 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
1019 | unsigned rptr_offs, u32 nop); |
1020 | unsigned rptr_offs, u32 nop); |
1020 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
1021 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
1021 | 1022 | ||
1022 | 1023 | ||
1023 | /* r600 async dma */ |
1024 | /* r600 async dma */ |
1024 | void r600_dma_stop(struct radeon_device *rdev); |
1025 | void r600_dma_stop(struct radeon_device *rdev); |
1025 | int r600_dma_resume(struct radeon_device *rdev); |
1026 | int r600_dma_resume(struct radeon_device *rdev); |
1026 | void r600_dma_fini(struct radeon_device *rdev); |
1027 | void r600_dma_fini(struct radeon_device *rdev); |
1027 | 1028 | ||
1028 | void cayman_dma_stop(struct radeon_device *rdev); |
1029 | void cayman_dma_stop(struct radeon_device *rdev); |
1029 | int cayman_dma_resume(struct radeon_device *rdev); |
1030 | int cayman_dma_resume(struct radeon_device *rdev); |
1030 | void cayman_dma_fini(struct radeon_device *rdev); |
1031 | void cayman_dma_fini(struct radeon_device *rdev); |
1031 | 1032 | ||
1032 | /* |
1033 | /* |
1033 | * CS. |
1034 | * CS. |
1034 | */ |
1035 | */ |
1035 | struct radeon_cs_reloc { |
1036 | struct radeon_cs_reloc { |
1036 | struct drm_gem_object *gobj; |
1037 | struct drm_gem_object *gobj; |
1037 | struct radeon_bo *robj; |
1038 | struct radeon_bo *robj; |
1038 | struct ttm_validate_buffer tv; |
1039 | struct ttm_validate_buffer tv; |
1039 | uint64_t gpu_offset; |
1040 | uint64_t gpu_offset; |
1040 | unsigned prefered_domains; |
1041 | unsigned prefered_domains; |
1041 | unsigned allowed_domains; |
1042 | unsigned allowed_domains; |
1042 | uint32_t tiling_flags; |
1043 | uint32_t tiling_flags; |
1043 | uint32_t handle; |
1044 | uint32_t handle; |
1044 | }; |
1045 | }; |
1045 | 1046 | ||
1046 | struct radeon_cs_chunk { |
1047 | struct radeon_cs_chunk { |
1047 | uint32_t chunk_id; |
1048 | uint32_t chunk_id; |
1048 | uint32_t length_dw; |
1049 | uint32_t length_dw; |
1049 | uint32_t *kdata; |
1050 | uint32_t *kdata; |
1050 | void __user *user_ptr; |
1051 | void __user *user_ptr; |
1051 | }; |
1052 | }; |
1052 | 1053 | ||
1053 | struct radeon_cs_parser { |
1054 | struct radeon_cs_parser { |
1054 | struct device *dev; |
1055 | struct device *dev; |
1055 | struct radeon_device *rdev; |
1056 | struct radeon_device *rdev; |
1056 | struct drm_file *filp; |
1057 | struct drm_file *filp; |
1057 | /* chunks */ |
1058 | /* chunks */ |
1058 | unsigned nchunks; |
1059 | unsigned nchunks; |
1059 | struct radeon_cs_chunk *chunks; |
1060 | struct radeon_cs_chunk *chunks; |
1060 | uint64_t *chunks_array; |
1061 | uint64_t *chunks_array; |
1061 | /* IB */ |
1062 | /* IB */ |
1062 | unsigned idx; |
1063 | unsigned idx; |
1063 | /* relocations */ |
1064 | /* relocations */ |
1064 | unsigned nrelocs; |
1065 | unsigned nrelocs; |
1065 | struct radeon_cs_reloc *relocs; |
1066 | struct radeon_cs_reloc *relocs; |
1066 | struct radeon_cs_reloc **relocs_ptr; |
1067 | struct radeon_cs_reloc **relocs_ptr; |
1067 | struct radeon_cs_reloc *vm_bos; |
1068 | struct radeon_cs_reloc *vm_bos; |
1068 | struct list_head validated; |
1069 | struct list_head validated; |
1069 | unsigned dma_reloc_idx; |
1070 | unsigned dma_reloc_idx; |
1070 | /* indices of various chunks */ |
1071 | /* indices of various chunks */ |
1071 | int chunk_ib_idx; |
1072 | int chunk_ib_idx; |
1072 | int chunk_relocs_idx; |
1073 | int chunk_relocs_idx; |
1073 | int chunk_flags_idx; |
1074 | int chunk_flags_idx; |
1074 | int chunk_const_ib_idx; |
1075 | int chunk_const_ib_idx; |
1075 | struct radeon_ib ib; |
1076 | struct radeon_ib ib; |
1076 | struct radeon_ib const_ib; |
1077 | struct radeon_ib const_ib; |
1077 | void *track; |
1078 | void *track; |
1078 | unsigned family; |
1079 | unsigned family; |
1079 | int parser_error; |
1080 | int parser_error; |
1080 | u32 cs_flags; |
1081 | u32 cs_flags; |
1081 | u32 ring; |
1082 | u32 ring; |
1082 | s32 priority; |
1083 | s32 priority; |
1083 | struct ww_acquire_ctx ticket; |
1084 | struct ww_acquire_ctx ticket; |
1084 | }; |
1085 | }; |
1085 | 1086 | ||
1086 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1087 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1087 | { |
1088 | { |
1088 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
1089 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
1089 | 1090 | ||
1090 | if (ibc->kdata) |
1091 | if (ibc->kdata) |
1091 | return ibc->kdata[idx]; |
1092 | return ibc->kdata[idx]; |
1092 | return p->ib.ptr[idx]; |
1093 | return p->ib.ptr[idx]; |
1093 | } |
1094 | } |
1094 | 1095 | ||
1095 | 1096 | ||
1096 | struct radeon_cs_packet { |
1097 | struct radeon_cs_packet { |
1097 | unsigned idx; |
1098 | unsigned idx; |
1098 | unsigned type; |
1099 | unsigned type; |
1099 | unsigned reg; |
1100 | unsigned reg; |
1100 | unsigned opcode; |
1101 | unsigned opcode; |
1101 | int count; |
1102 | int count; |
1102 | unsigned one_reg_wr; |
1103 | unsigned one_reg_wr; |
1103 | }; |
1104 | }; |
1104 | 1105 | ||
1105 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
1106 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
1106 | struct radeon_cs_packet *pkt, |
1107 | struct radeon_cs_packet *pkt, |
1107 | unsigned idx, unsigned reg); |
1108 | unsigned idx, unsigned reg); |
1108 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
1109 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
1109 | struct radeon_cs_packet *pkt); |
1110 | struct radeon_cs_packet *pkt); |
1110 | 1111 | ||
1111 | 1112 | ||
1112 | /* |
1113 | /* |
1113 | * AGP |
1114 | * AGP |
1114 | */ |
1115 | */ |
1115 | int radeon_agp_init(struct radeon_device *rdev); |
1116 | int radeon_agp_init(struct radeon_device *rdev); |
1116 | void radeon_agp_resume(struct radeon_device *rdev); |
1117 | void radeon_agp_resume(struct radeon_device *rdev); |
1117 | void radeon_agp_suspend(struct radeon_device *rdev); |
1118 | void radeon_agp_suspend(struct radeon_device *rdev); |
1118 | void radeon_agp_fini(struct radeon_device *rdev); |
1119 | void radeon_agp_fini(struct radeon_device *rdev); |
1119 | 1120 | ||
1120 | 1121 | ||
1121 | /* |
1122 | /* |
1122 | * Writeback |
1123 | * Writeback |
1123 | */ |
1124 | */ |
1124 | struct radeon_wb { |
1125 | struct radeon_wb { |
1125 | struct radeon_bo *wb_obj; |
1126 | struct radeon_bo *wb_obj; |
1126 | volatile uint32_t *wb; |
1127 | volatile uint32_t *wb; |
1127 | uint64_t gpu_addr; |
1128 | uint64_t gpu_addr; |
1128 | bool enabled; |
1129 | bool enabled; |
1129 | bool use_event; |
1130 | bool use_event; |
1130 | }; |
1131 | }; |
1131 | 1132 | ||
1132 | #define RADEON_WB_SCRATCH_OFFSET 0 |
1133 | #define RADEON_WB_SCRATCH_OFFSET 0 |
1133 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1134 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1134 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
1135 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
1135 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1136 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1136 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
1137 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
1137 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1138 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1138 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1139 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1139 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1140 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1140 | #define R600_WB_EVENT_OFFSET 3072 |
1141 | #define R600_WB_EVENT_OFFSET 3072 |
1141 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1142 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1142 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
1143 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
- | 1144 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
|
- | 1145 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
|
1143 | 1146 | ||
1144 | /** |
1147 | /** |
1145 | * struct radeon_pm - power management datas |
1148 | * struct radeon_pm - power management datas |
1146 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1149 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1147 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
1150 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
1148 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
1151 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
1149 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
1152 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
1150 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
1153 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
1151 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
1154 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
1152 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
1155 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
1153 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
1156 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
1154 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
1157 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
1155 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1158 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1156 | * @needed_bandwidth: current bandwidth needs |
1159 | * @needed_bandwidth: current bandwidth needs |
1157 | * |
1160 | * |
1158 | * It keeps track of various data needed to take powermanagement decision. |
1161 | * It keeps track of various data needed to take powermanagement decision. |
1159 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1162 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1160 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1163 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1161 | * (type of memory, bus size, efficiency, ...) |
1164 | * (type of memory, bus size, efficiency, ...) |
1162 | */ |
1165 | */ |
1163 | 1166 | ||
1164 | enum radeon_pm_method { |
1167 | enum radeon_pm_method { |
1165 | PM_METHOD_PROFILE, |
1168 | PM_METHOD_PROFILE, |
1166 | PM_METHOD_DYNPM, |
1169 | PM_METHOD_DYNPM, |
1167 | PM_METHOD_DPM, |
1170 | PM_METHOD_DPM, |
1168 | }; |
1171 | }; |
1169 | 1172 | ||
1170 | enum radeon_dynpm_state { |
1173 | enum radeon_dynpm_state { |
1171 | DYNPM_STATE_DISABLED, |
1174 | DYNPM_STATE_DISABLED, |
1172 | DYNPM_STATE_MINIMUM, |
1175 | DYNPM_STATE_MINIMUM, |
1173 | DYNPM_STATE_PAUSED, |
1176 | DYNPM_STATE_PAUSED, |
1174 | DYNPM_STATE_ACTIVE, |
1177 | DYNPM_STATE_ACTIVE, |
1175 | DYNPM_STATE_SUSPENDED, |
1178 | DYNPM_STATE_SUSPENDED, |
1176 | }; |
1179 | }; |
1177 | enum radeon_dynpm_action { |
1180 | enum radeon_dynpm_action { |
1178 | DYNPM_ACTION_NONE, |
1181 | DYNPM_ACTION_NONE, |
1179 | DYNPM_ACTION_MINIMUM, |
1182 | DYNPM_ACTION_MINIMUM, |
1180 | DYNPM_ACTION_DOWNCLOCK, |
1183 | DYNPM_ACTION_DOWNCLOCK, |
1181 | DYNPM_ACTION_UPCLOCK, |
1184 | DYNPM_ACTION_UPCLOCK, |
1182 | DYNPM_ACTION_DEFAULT |
1185 | DYNPM_ACTION_DEFAULT |
1183 | }; |
1186 | }; |
1184 | 1187 | ||
1185 | enum radeon_voltage_type { |
1188 | enum radeon_voltage_type { |
1186 | VOLTAGE_NONE = 0, |
1189 | VOLTAGE_NONE = 0, |
1187 | VOLTAGE_GPIO, |
1190 | VOLTAGE_GPIO, |
1188 | VOLTAGE_VDDC, |
1191 | VOLTAGE_VDDC, |
1189 | VOLTAGE_SW |
1192 | VOLTAGE_SW |
1190 | }; |
1193 | }; |
1191 | 1194 | ||
1192 | enum radeon_pm_state_type { |
1195 | enum radeon_pm_state_type { |
1193 | /* not used for dpm */ |
1196 | /* not used for dpm */ |
1194 | POWER_STATE_TYPE_DEFAULT, |
1197 | POWER_STATE_TYPE_DEFAULT, |
1195 | POWER_STATE_TYPE_POWERSAVE, |
1198 | POWER_STATE_TYPE_POWERSAVE, |
1196 | /* user selectable states */ |
1199 | /* user selectable states */ |
1197 | POWER_STATE_TYPE_BATTERY, |
1200 | POWER_STATE_TYPE_BATTERY, |
1198 | POWER_STATE_TYPE_BALANCED, |
1201 | POWER_STATE_TYPE_BALANCED, |
1199 | POWER_STATE_TYPE_PERFORMANCE, |
1202 | POWER_STATE_TYPE_PERFORMANCE, |
1200 | /* internal states */ |
1203 | /* internal states */ |
1201 | POWER_STATE_TYPE_INTERNAL_UVD, |
1204 | POWER_STATE_TYPE_INTERNAL_UVD, |
1202 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
1205 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
1203 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
1206 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
1204 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
1207 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
1205 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
1208 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
1206 | POWER_STATE_TYPE_INTERNAL_BOOT, |
1209 | POWER_STATE_TYPE_INTERNAL_BOOT, |
1207 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
1210 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
1208 | POWER_STATE_TYPE_INTERNAL_ACPI, |
1211 | POWER_STATE_TYPE_INTERNAL_ACPI, |
1209 | POWER_STATE_TYPE_INTERNAL_ULV, |
1212 | POWER_STATE_TYPE_INTERNAL_ULV, |
1210 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
1213 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
1211 | }; |
1214 | }; |
1212 | 1215 | ||
1213 | enum radeon_pm_profile_type { |
1216 | enum radeon_pm_profile_type { |
1214 | PM_PROFILE_DEFAULT, |
1217 | PM_PROFILE_DEFAULT, |
1215 | PM_PROFILE_AUTO, |
1218 | PM_PROFILE_AUTO, |
1216 | PM_PROFILE_LOW, |
1219 | PM_PROFILE_LOW, |
1217 | PM_PROFILE_MID, |
1220 | PM_PROFILE_MID, |
1218 | PM_PROFILE_HIGH, |
1221 | PM_PROFILE_HIGH, |
1219 | }; |
1222 | }; |
1220 | 1223 | ||
1221 | #define PM_PROFILE_DEFAULT_IDX 0 |
1224 | #define PM_PROFILE_DEFAULT_IDX 0 |
1222 | #define PM_PROFILE_LOW_SH_IDX 1 |
1225 | #define PM_PROFILE_LOW_SH_IDX 1 |
1223 | #define PM_PROFILE_MID_SH_IDX 2 |
1226 | #define PM_PROFILE_MID_SH_IDX 2 |
1224 | #define PM_PROFILE_HIGH_SH_IDX 3 |
1227 | #define PM_PROFILE_HIGH_SH_IDX 3 |
1225 | #define PM_PROFILE_LOW_MH_IDX 4 |
1228 | #define PM_PROFILE_LOW_MH_IDX 4 |
1226 | #define PM_PROFILE_MID_MH_IDX 5 |
1229 | #define PM_PROFILE_MID_MH_IDX 5 |
1227 | #define PM_PROFILE_HIGH_MH_IDX 6 |
1230 | #define PM_PROFILE_HIGH_MH_IDX 6 |
1228 | #define PM_PROFILE_MAX 7 |
1231 | #define PM_PROFILE_MAX 7 |
1229 | 1232 | ||
1230 | struct radeon_pm_profile { |
1233 | struct radeon_pm_profile { |
1231 | int dpms_off_ps_idx; |
1234 | int dpms_off_ps_idx; |
1232 | int dpms_on_ps_idx; |
1235 | int dpms_on_ps_idx; |
1233 | int dpms_off_cm_idx; |
1236 | int dpms_off_cm_idx; |
1234 | int dpms_on_cm_idx; |
1237 | int dpms_on_cm_idx; |
1235 | }; |
1238 | }; |
1236 | 1239 | ||
1237 | enum radeon_int_thermal_type { |
1240 | enum radeon_int_thermal_type { |
1238 | THERMAL_TYPE_NONE, |
1241 | THERMAL_TYPE_NONE, |
1239 | THERMAL_TYPE_EXTERNAL, |
1242 | THERMAL_TYPE_EXTERNAL, |
1240 | THERMAL_TYPE_EXTERNAL_GPIO, |
1243 | THERMAL_TYPE_EXTERNAL_GPIO, |
1241 | THERMAL_TYPE_RV6XX, |
1244 | THERMAL_TYPE_RV6XX, |
1242 | THERMAL_TYPE_RV770, |
1245 | THERMAL_TYPE_RV770, |
1243 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
1246 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
1244 | THERMAL_TYPE_EVERGREEN, |
1247 | THERMAL_TYPE_EVERGREEN, |
1245 | THERMAL_TYPE_SUMO, |
1248 | THERMAL_TYPE_SUMO, |
1246 | THERMAL_TYPE_NI, |
1249 | THERMAL_TYPE_NI, |
1247 | THERMAL_TYPE_SI, |
1250 | THERMAL_TYPE_SI, |
1248 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
1251 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
1249 | THERMAL_TYPE_CI, |
1252 | THERMAL_TYPE_CI, |
1250 | THERMAL_TYPE_KV, |
1253 | THERMAL_TYPE_KV, |
1251 | }; |
1254 | }; |
1252 | 1255 | ||
1253 | struct radeon_voltage { |
1256 | struct radeon_voltage { |
1254 | enum radeon_voltage_type type; |
1257 | enum radeon_voltage_type type; |
1255 | /* gpio voltage */ |
1258 | /* gpio voltage */ |
1256 | struct radeon_gpio_rec gpio; |
1259 | struct radeon_gpio_rec gpio; |
1257 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
1260 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
1258 | bool active_high; /* voltage drop is active when bit is high */ |
1261 | bool active_high; /* voltage drop is active when bit is high */ |
1259 | /* VDDC voltage */ |
1262 | /* VDDC voltage */ |
1260 | u8 vddc_id; /* index into vddc voltage table */ |
1263 | u8 vddc_id; /* index into vddc voltage table */ |
1261 | u8 vddci_id; /* index into vddci voltage table */ |
1264 | u8 vddci_id; /* index into vddci voltage table */ |
1262 | bool vddci_enabled; |
1265 | bool vddci_enabled; |
1263 | /* r6xx+ sw */ |
1266 | /* r6xx+ sw */ |
1264 | u16 voltage; |
1267 | u16 voltage; |
1265 | /* evergreen+ vddci */ |
1268 | /* evergreen+ vddci */ |
1266 | u16 vddci; |
1269 | u16 vddci; |
1267 | }; |
1270 | }; |
1268 | 1271 | ||
1269 | /* clock mode flags */ |
1272 | /* clock mode flags */ |
1270 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
1273 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
1271 | 1274 | ||
1272 | struct radeon_pm_clock_info { |
1275 | struct radeon_pm_clock_info { |
1273 | /* memory clock */ |
1276 | /* memory clock */ |
1274 | u32 mclk; |
1277 | u32 mclk; |
1275 | /* engine clock */ |
1278 | /* engine clock */ |
1276 | u32 sclk; |
1279 | u32 sclk; |
1277 | /* voltage info */ |
1280 | /* voltage info */ |
1278 | struct radeon_voltage voltage; |
1281 | struct radeon_voltage voltage; |
1279 | /* standardized clock flags */ |
1282 | /* standardized clock flags */ |
1280 | u32 flags; |
1283 | u32 flags; |
1281 | }; |
1284 | }; |
1282 | 1285 | ||
1283 | /* state flags */ |
1286 | /* state flags */ |
1284 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
1287 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
1285 | 1288 | ||
1286 | struct radeon_power_state { |
1289 | struct radeon_power_state { |
1287 | enum radeon_pm_state_type type; |
1290 | enum radeon_pm_state_type type; |
1288 | struct radeon_pm_clock_info *clock_info; |
1291 | struct radeon_pm_clock_info *clock_info; |
1289 | /* number of valid clock modes in this power state */ |
1292 | /* number of valid clock modes in this power state */ |
1290 | int num_clock_modes; |
1293 | int num_clock_modes; |
1291 | struct radeon_pm_clock_info *default_clock_mode; |
1294 | struct radeon_pm_clock_info *default_clock_mode; |
1292 | /* standardized state flags */ |
1295 | /* standardized state flags */ |
1293 | u32 flags; |
1296 | u32 flags; |
1294 | u32 misc; /* vbios specific flags */ |
1297 | u32 misc; /* vbios specific flags */ |
1295 | u32 misc2; /* vbios specific flags */ |
1298 | u32 misc2; /* vbios specific flags */ |
1296 | int pcie_lanes; /* pcie lanes */ |
1299 | int pcie_lanes; /* pcie lanes */ |
1297 | }; |
1300 | }; |
1298 | 1301 | ||
1299 | /* |
1302 | /* |
1300 | * Some modes are overclocked by very low value, accept them |
1303 | * Some modes are overclocked by very low value, accept them |
1301 | */ |
1304 | */ |
1302 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
1305 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
1303 | 1306 | ||
1304 | enum radeon_dpm_auto_throttle_src { |
1307 | enum radeon_dpm_auto_throttle_src { |
1305 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
1308 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
1306 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
1309 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
1307 | }; |
1310 | }; |
1308 | 1311 | ||
1309 | enum radeon_dpm_event_src { |
1312 | enum radeon_dpm_event_src { |
1310 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
1313 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
1311 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
1314 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
1312 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
1315 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
1313 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
1316 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
1314 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
1317 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
1315 | }; |
1318 | }; |
1316 | 1319 | ||
1317 | #define RADEON_MAX_VCE_LEVELS 6 |
1320 | #define RADEON_MAX_VCE_LEVELS 6 |
1318 | 1321 | ||
1319 | enum radeon_vce_level { |
1322 | enum radeon_vce_level { |
1320 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
1323 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
1321 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
1324 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
1322 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
1325 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
1323 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
1326 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
1324 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
1327 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
1325 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
1328 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
1326 | }; |
1329 | }; |
1327 | 1330 | ||
1328 | struct radeon_ps { |
1331 | struct radeon_ps { |
1329 | u32 caps; /* vbios flags */ |
1332 | u32 caps; /* vbios flags */ |
1330 | u32 class; /* vbios flags */ |
1333 | u32 class; /* vbios flags */ |
1331 | u32 class2; /* vbios flags */ |
1334 | u32 class2; /* vbios flags */ |
1332 | /* UVD clocks */ |
1335 | /* UVD clocks */ |
1333 | u32 vclk; |
1336 | u32 vclk; |
1334 | u32 dclk; |
1337 | u32 dclk; |
1335 | /* VCE clocks */ |
1338 | /* VCE clocks */ |
1336 | u32 evclk; |
1339 | u32 evclk; |
1337 | u32 ecclk; |
1340 | u32 ecclk; |
1338 | bool vce_active; |
1341 | bool vce_active; |
1339 | enum radeon_vce_level vce_level; |
1342 | enum radeon_vce_level vce_level; |
1340 | /* asic priv */ |
1343 | /* asic priv */ |
1341 | void *ps_priv; |
1344 | void *ps_priv; |
1342 | }; |
1345 | }; |
1343 | 1346 | ||
1344 | struct radeon_dpm_thermal { |
1347 | struct radeon_dpm_thermal { |
1345 | /* thermal interrupt work */ |
1348 | /* thermal interrupt work */ |
1346 | struct work_struct work; |
1349 | struct work_struct work; |
1347 | /* low temperature threshold */ |
1350 | /* low temperature threshold */ |
1348 | int min_temp; |
1351 | int min_temp; |
1349 | /* high temperature threshold */ |
1352 | /* high temperature threshold */ |
1350 | int max_temp; |
1353 | int max_temp; |
1351 | /* was interrupt low to high or high to low */ |
1354 | /* was interrupt low to high or high to low */ |
1352 | bool high_to_low; |
1355 | bool high_to_low; |
1353 | }; |
1356 | }; |
1354 | 1357 | ||
1355 | enum radeon_clk_action |
1358 | enum radeon_clk_action |
1356 | { |
1359 | { |
1357 | RADEON_SCLK_UP = 1, |
1360 | RADEON_SCLK_UP = 1, |
1358 | RADEON_SCLK_DOWN |
1361 | RADEON_SCLK_DOWN |
1359 | }; |
1362 | }; |
1360 | 1363 | ||
1361 | struct radeon_blacklist_clocks |
1364 | struct radeon_blacklist_clocks |
1362 | { |
1365 | { |
1363 | u32 sclk; |
1366 | u32 sclk; |
1364 | u32 mclk; |
1367 | u32 mclk; |
1365 | enum radeon_clk_action action; |
1368 | enum radeon_clk_action action; |
1366 | }; |
1369 | }; |
1367 | 1370 | ||
1368 | struct radeon_clock_and_voltage_limits { |
1371 | struct radeon_clock_and_voltage_limits { |
1369 | u32 sclk; |
1372 | u32 sclk; |
1370 | u32 mclk; |
1373 | u32 mclk; |
1371 | u16 vddc; |
1374 | u16 vddc; |
1372 | u16 vddci; |
1375 | u16 vddci; |
1373 | }; |
1376 | }; |
1374 | 1377 | ||
1375 | struct radeon_clock_array { |
1378 | struct radeon_clock_array { |
1376 | u32 count; |
1379 | u32 count; |
1377 | u32 *values; |
1380 | u32 *values; |
1378 | }; |
1381 | }; |
1379 | 1382 | ||
1380 | struct radeon_clock_voltage_dependency_entry { |
1383 | struct radeon_clock_voltage_dependency_entry { |
1381 | u32 clk; |
1384 | u32 clk; |
1382 | u16 v; |
1385 | u16 v; |
1383 | }; |
1386 | }; |
1384 | 1387 | ||
1385 | struct radeon_clock_voltage_dependency_table { |
1388 | struct radeon_clock_voltage_dependency_table { |
1386 | u32 count; |
1389 | u32 count; |
1387 | struct radeon_clock_voltage_dependency_entry *entries; |
1390 | struct radeon_clock_voltage_dependency_entry *entries; |
1388 | }; |
1391 | }; |
1389 | 1392 | ||
1390 | union radeon_cac_leakage_entry { |
1393 | union radeon_cac_leakage_entry { |
1391 | struct { |
1394 | struct { |
1392 | u16 vddc; |
1395 | u16 vddc; |
1393 | u32 leakage; |
1396 | u32 leakage; |
1394 | }; |
1397 | }; |
1395 | struct { |
1398 | struct { |
1396 | u16 vddc1; |
1399 | u16 vddc1; |
1397 | u16 vddc2; |
1400 | u16 vddc2; |
1398 | u16 vddc3; |
1401 | u16 vddc3; |
1399 | }; |
1402 | }; |
1400 | }; |
1403 | }; |
1401 | 1404 | ||
1402 | struct radeon_cac_leakage_table { |
1405 | struct radeon_cac_leakage_table { |
1403 | u32 count; |
1406 | u32 count; |
1404 | union radeon_cac_leakage_entry *entries; |
1407 | union radeon_cac_leakage_entry *entries; |
1405 | }; |
1408 | }; |
1406 | 1409 | ||
1407 | struct radeon_phase_shedding_limits_entry { |
1410 | struct radeon_phase_shedding_limits_entry { |
1408 | u16 voltage; |
1411 | u16 voltage; |
1409 | u32 sclk; |
1412 | u32 sclk; |
1410 | u32 mclk; |
1413 | u32 mclk; |
1411 | }; |
1414 | }; |
1412 | 1415 | ||
1413 | struct radeon_phase_shedding_limits_table { |
1416 | struct radeon_phase_shedding_limits_table { |
1414 | u32 count; |
1417 | u32 count; |
1415 | struct radeon_phase_shedding_limits_entry *entries; |
1418 | struct radeon_phase_shedding_limits_entry *entries; |
1416 | }; |
1419 | }; |
1417 | 1420 | ||
1418 | struct radeon_uvd_clock_voltage_dependency_entry { |
1421 | struct radeon_uvd_clock_voltage_dependency_entry { |
1419 | u32 vclk; |
1422 | u32 vclk; |
1420 | u32 dclk; |
1423 | u32 dclk; |
1421 | u16 v; |
1424 | u16 v; |
1422 | }; |
1425 | }; |
1423 | 1426 | ||
1424 | struct radeon_uvd_clock_voltage_dependency_table { |
1427 | struct radeon_uvd_clock_voltage_dependency_table { |
1425 | u8 count; |
1428 | u8 count; |
1426 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
1429 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
1427 | }; |
1430 | }; |
1428 | 1431 | ||
1429 | struct radeon_vce_clock_voltage_dependency_entry { |
1432 | struct radeon_vce_clock_voltage_dependency_entry { |
1430 | u32 ecclk; |
1433 | u32 ecclk; |
1431 | u32 evclk; |
1434 | u32 evclk; |
1432 | u16 v; |
1435 | u16 v; |
1433 | }; |
1436 | }; |
1434 | 1437 | ||
1435 | struct radeon_vce_clock_voltage_dependency_table { |
1438 | struct radeon_vce_clock_voltage_dependency_table { |
1436 | u8 count; |
1439 | u8 count; |
1437 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
1440 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
1438 | }; |
1441 | }; |
1439 | 1442 | ||
1440 | struct radeon_ppm_table { |
1443 | struct radeon_ppm_table { |
1441 | u8 ppm_design; |
1444 | u8 ppm_design; |
1442 | u16 cpu_core_number; |
1445 | u16 cpu_core_number; |
1443 | u32 platform_tdp; |
1446 | u32 platform_tdp; |
1444 | u32 small_ac_platform_tdp; |
1447 | u32 small_ac_platform_tdp; |
1445 | u32 platform_tdc; |
1448 | u32 platform_tdc; |
1446 | u32 small_ac_platform_tdc; |
1449 | u32 small_ac_platform_tdc; |
1447 | u32 apu_tdp; |
1450 | u32 apu_tdp; |
1448 | u32 dgpu_tdp; |
1451 | u32 dgpu_tdp; |
1449 | u32 dgpu_ulv_power; |
1452 | u32 dgpu_ulv_power; |
1450 | u32 tj_max; |
1453 | u32 tj_max; |
1451 | }; |
1454 | }; |
1452 | 1455 | ||
1453 | struct radeon_cac_tdp_table { |
1456 | struct radeon_cac_tdp_table { |
1454 | u16 tdp; |
1457 | u16 tdp; |
1455 | u16 configurable_tdp; |
1458 | u16 configurable_tdp; |
1456 | u16 tdc; |
1459 | u16 tdc; |
1457 | u16 battery_power_limit; |
1460 | u16 battery_power_limit; |
1458 | u16 small_power_limit; |
1461 | u16 small_power_limit; |
1459 | u16 low_cac_leakage; |
1462 | u16 low_cac_leakage; |
1460 | u16 high_cac_leakage; |
1463 | u16 high_cac_leakage; |
1461 | u16 maximum_power_delivery_limit; |
1464 | u16 maximum_power_delivery_limit; |
1462 | }; |
1465 | }; |
1463 | 1466 | ||
1464 | struct radeon_dpm_dynamic_state { |
1467 | struct radeon_dpm_dynamic_state { |
1465 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
1468 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
1466 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
1469 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
1467 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
1470 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
1468 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
1471 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
1469 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
1472 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
1470 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
1473 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
1471 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
1474 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
1472 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1475 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1473 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
1476 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
1474 | struct radeon_clock_array valid_sclk_values; |
1477 | struct radeon_clock_array valid_sclk_values; |
1475 | struct radeon_clock_array valid_mclk_values; |
1478 | struct radeon_clock_array valid_mclk_values; |
1476 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
1479 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
1477 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
1480 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
1478 | u32 mclk_sclk_ratio; |
1481 | u32 mclk_sclk_ratio; |
1479 | u32 sclk_mclk_delta; |
1482 | u32 sclk_mclk_delta; |
1480 | u16 vddc_vddci_delta; |
1483 | u16 vddc_vddci_delta; |
1481 | u16 min_vddc_for_pcie_gen2; |
1484 | u16 min_vddc_for_pcie_gen2; |
1482 | struct radeon_cac_leakage_table cac_leakage_table; |
1485 | struct radeon_cac_leakage_table cac_leakage_table; |
1483 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
1486 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
1484 | struct radeon_ppm_table *ppm_table; |
1487 | struct radeon_ppm_table *ppm_table; |
1485 | struct radeon_cac_tdp_table *cac_tdp_table; |
1488 | struct radeon_cac_tdp_table *cac_tdp_table; |
1486 | }; |
1489 | }; |
1487 | 1490 | ||
1488 | struct radeon_dpm_fan { |
1491 | struct radeon_dpm_fan { |
1489 | u16 t_min; |
1492 | u16 t_min; |
1490 | u16 t_med; |
1493 | u16 t_med; |
1491 | u16 t_high; |
1494 | u16 t_high; |
1492 | u16 pwm_min; |
1495 | u16 pwm_min; |
1493 | u16 pwm_med; |
1496 | u16 pwm_med; |
1494 | u16 pwm_high; |
1497 | u16 pwm_high; |
1495 | u8 t_hyst; |
1498 | u8 t_hyst; |
1496 | u32 cycle_delay; |
1499 | u32 cycle_delay; |
1497 | u16 t_max; |
1500 | u16 t_max; |
1498 | bool ucode_fan_control; |
1501 | bool ucode_fan_control; |
1499 | }; |
1502 | }; |
1500 | 1503 | ||
1501 | enum radeon_pcie_gen { |
1504 | enum radeon_pcie_gen { |
1502 | RADEON_PCIE_GEN1 = 0, |
1505 | RADEON_PCIE_GEN1 = 0, |
1503 | RADEON_PCIE_GEN2 = 1, |
1506 | RADEON_PCIE_GEN2 = 1, |
1504 | RADEON_PCIE_GEN3 = 2, |
1507 | RADEON_PCIE_GEN3 = 2, |
1505 | RADEON_PCIE_GEN_INVALID = 0xffff |
1508 | RADEON_PCIE_GEN_INVALID = 0xffff |
1506 | }; |
1509 | }; |
1507 | 1510 | ||
1508 | enum radeon_dpm_forced_level { |
1511 | enum radeon_dpm_forced_level { |
1509 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
1512 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
1510 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
1513 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
1511 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
1514 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
1512 | }; |
1515 | }; |
1513 | 1516 | ||
1514 | struct radeon_vce_state { |
1517 | struct radeon_vce_state { |
1515 | /* vce clocks */ |
1518 | /* vce clocks */ |
1516 | u32 evclk; |
1519 | u32 evclk; |
1517 | u32 ecclk; |
1520 | u32 ecclk; |
1518 | /* gpu clocks */ |
1521 | /* gpu clocks */ |
1519 | u32 sclk; |
1522 | u32 sclk; |
1520 | u32 mclk; |
1523 | u32 mclk; |
1521 | u8 clk_idx; |
1524 | u8 clk_idx; |
1522 | u8 pstate; |
1525 | u8 pstate; |
1523 | }; |
1526 | }; |
1524 | 1527 | ||
1525 | struct radeon_dpm { |
1528 | struct radeon_dpm { |
1526 | struct radeon_ps *ps; |
1529 | struct radeon_ps *ps; |
1527 | /* number of valid power states */ |
1530 | /* number of valid power states */ |
1528 | int num_ps; |
1531 | int num_ps; |
1529 | /* current power state that is active */ |
1532 | /* current power state that is active */ |
1530 | struct radeon_ps *current_ps; |
1533 | struct radeon_ps *current_ps; |
1531 | /* requested power state */ |
1534 | /* requested power state */ |
1532 | struct radeon_ps *requested_ps; |
1535 | struct radeon_ps *requested_ps; |
1533 | /* boot up power state */ |
1536 | /* boot up power state */ |
1534 | struct radeon_ps *boot_ps; |
1537 | struct radeon_ps *boot_ps; |
1535 | /* default uvd power state */ |
1538 | /* default uvd power state */ |
1536 | struct radeon_ps *uvd_ps; |
1539 | struct radeon_ps *uvd_ps; |
1537 | /* vce requirements */ |
1540 | /* vce requirements */ |
1538 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
1541 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
1539 | enum radeon_vce_level vce_level; |
1542 | enum radeon_vce_level vce_level; |
1540 | enum radeon_pm_state_type state; |
1543 | enum radeon_pm_state_type state; |
1541 | enum radeon_pm_state_type user_state; |
1544 | enum radeon_pm_state_type user_state; |
1542 | u32 platform_caps; |
1545 | u32 platform_caps; |
1543 | u32 voltage_response_time; |
1546 | u32 voltage_response_time; |
1544 | u32 backbias_response_time; |
1547 | u32 backbias_response_time; |
1545 | void *priv; |
1548 | void *priv; |
1546 | u32 new_active_crtcs; |
1549 | u32 new_active_crtcs; |
1547 | int new_active_crtc_count; |
1550 | int new_active_crtc_count; |
1548 | u32 current_active_crtcs; |
1551 | u32 current_active_crtcs; |
1549 | int current_active_crtc_count; |
1552 | int current_active_crtc_count; |
1550 | struct radeon_dpm_dynamic_state dyn_state; |
1553 | struct radeon_dpm_dynamic_state dyn_state; |
1551 | struct radeon_dpm_fan fan; |
1554 | struct radeon_dpm_fan fan; |
1552 | u32 tdp_limit; |
1555 | u32 tdp_limit; |
1553 | u32 near_tdp_limit; |
1556 | u32 near_tdp_limit; |
1554 | u32 near_tdp_limit_adjusted; |
1557 | u32 near_tdp_limit_adjusted; |
1555 | u32 sq_ramping_threshold; |
1558 | u32 sq_ramping_threshold; |
1556 | u32 cac_leakage; |
1559 | u32 cac_leakage; |
1557 | u16 tdp_od_limit; |
1560 | u16 tdp_od_limit; |
1558 | u32 tdp_adjustment; |
1561 | u32 tdp_adjustment; |
1559 | u16 load_line_slope; |
1562 | u16 load_line_slope; |
1560 | bool power_control; |
1563 | bool power_control; |
1561 | bool ac_power; |
1564 | bool ac_power; |
1562 | /* special states active */ |
1565 | /* special states active */ |
1563 | bool thermal_active; |
1566 | bool thermal_active; |
1564 | bool uvd_active; |
1567 | bool uvd_active; |
1565 | bool vce_active; |
1568 | bool vce_active; |
1566 | /* thermal handling */ |
1569 | /* thermal handling */ |
1567 | struct radeon_dpm_thermal thermal; |
1570 | struct radeon_dpm_thermal thermal; |
1568 | /* forced levels */ |
1571 | /* forced levels */ |
1569 | enum radeon_dpm_forced_level forced_level; |
1572 | enum radeon_dpm_forced_level forced_level; |
1570 | /* track UVD streams */ |
1573 | /* track UVD streams */ |
1571 | unsigned sd; |
1574 | unsigned sd; |
1572 | unsigned hd; |
1575 | unsigned hd; |
1573 | }; |
1576 | }; |
1574 | 1577 | ||
1575 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
1578 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
1576 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
1579 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
1577 | 1580 | ||
1578 | struct radeon_pm { |
1581 | struct radeon_pm { |
1579 | struct mutex mutex; |
1582 | struct mutex mutex; |
1580 | /* write locked while reprogramming mclk */ |
1583 | /* write locked while reprogramming mclk */ |
1581 | struct rw_semaphore mclk_lock; |
1584 | struct rw_semaphore mclk_lock; |
1582 | u32 active_crtcs; |
1585 | u32 active_crtcs; |
1583 | int active_crtc_count; |
1586 | int active_crtc_count; |
1584 | int req_vblank; |
1587 | int req_vblank; |
1585 | bool vblank_sync; |
1588 | bool vblank_sync; |
1586 | fixed20_12 max_bandwidth; |
1589 | fixed20_12 max_bandwidth; |
1587 | fixed20_12 igp_sideport_mclk; |
1590 | fixed20_12 igp_sideport_mclk; |
1588 | fixed20_12 igp_system_mclk; |
1591 | fixed20_12 igp_system_mclk; |
1589 | fixed20_12 igp_ht_link_clk; |
1592 | fixed20_12 igp_ht_link_clk; |
1590 | fixed20_12 igp_ht_link_width; |
1593 | fixed20_12 igp_ht_link_width; |
1591 | fixed20_12 k8_bandwidth; |
1594 | fixed20_12 k8_bandwidth; |
1592 | fixed20_12 sideport_bandwidth; |
1595 | fixed20_12 sideport_bandwidth; |
1593 | fixed20_12 ht_bandwidth; |
1596 | fixed20_12 ht_bandwidth; |
1594 | fixed20_12 core_bandwidth; |
1597 | fixed20_12 core_bandwidth; |
1595 | fixed20_12 sclk; |
1598 | fixed20_12 sclk; |
1596 | fixed20_12 mclk; |
1599 | fixed20_12 mclk; |
1597 | fixed20_12 needed_bandwidth; |
1600 | fixed20_12 needed_bandwidth; |
1598 | struct radeon_power_state *power_state; |
1601 | struct radeon_power_state *power_state; |
1599 | /* number of valid power states */ |
1602 | /* number of valid power states */ |
1600 | int num_power_states; |
1603 | int num_power_states; |
1601 | int current_power_state_index; |
1604 | int current_power_state_index; |
1602 | int current_clock_mode_index; |
1605 | int current_clock_mode_index; |
1603 | int requested_power_state_index; |
1606 | int requested_power_state_index; |
1604 | int requested_clock_mode_index; |
1607 | int requested_clock_mode_index; |
1605 | int default_power_state_index; |
1608 | int default_power_state_index; |
1606 | u32 current_sclk; |
1609 | u32 current_sclk; |
1607 | u32 current_mclk; |
1610 | u32 current_mclk; |
1608 | u16 current_vddc; |
1611 | u16 current_vddc; |
1609 | u16 current_vddci; |
1612 | u16 current_vddci; |
1610 | u32 default_sclk; |
1613 | u32 default_sclk; |
1611 | u32 default_mclk; |
1614 | u32 default_mclk; |
1612 | u16 default_vddc; |
1615 | u16 default_vddc; |
1613 | u16 default_vddci; |
1616 | u16 default_vddci; |
1614 | struct radeon_i2c_chan *i2c_bus; |
1617 | struct radeon_i2c_chan *i2c_bus; |
1615 | /* selected pm method */ |
1618 | /* selected pm method */ |
1616 | enum radeon_pm_method pm_method; |
1619 | enum radeon_pm_method pm_method; |
1617 | /* dynpm power management */ |
1620 | /* dynpm power management */ |
1618 | struct delayed_work dynpm_idle_work; |
1621 | struct delayed_work dynpm_idle_work; |
1619 | enum radeon_dynpm_state dynpm_state; |
1622 | enum radeon_dynpm_state dynpm_state; |
1620 | enum radeon_dynpm_action dynpm_planned_action; |
1623 | enum radeon_dynpm_action dynpm_planned_action; |
1621 | unsigned long dynpm_action_timeout; |
1624 | unsigned long dynpm_action_timeout; |
1622 | bool dynpm_can_upclock; |
1625 | bool dynpm_can_upclock; |
1623 | bool dynpm_can_downclock; |
1626 | bool dynpm_can_downclock; |
1624 | /* profile-based power management */ |
1627 | /* profile-based power management */ |
1625 | enum radeon_pm_profile_type profile; |
1628 | enum radeon_pm_profile_type profile; |
1626 | int profile_index; |
1629 | int profile_index; |
1627 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
1630 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
1628 | /* internal thermal controller on rv6xx+ */ |
1631 | /* internal thermal controller on rv6xx+ */ |
1629 | enum radeon_int_thermal_type int_thermal_type; |
1632 | enum radeon_int_thermal_type int_thermal_type; |
1630 | struct device *int_hwmon_dev; |
1633 | struct device *int_hwmon_dev; |
1631 | /* dpm */ |
1634 | /* dpm */ |
1632 | bool dpm_enabled; |
1635 | bool dpm_enabled; |
1633 | struct radeon_dpm dpm; |
1636 | struct radeon_dpm dpm; |
1634 | }; |
1637 | }; |
1635 | 1638 | ||
1636 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1639 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1637 | enum radeon_pm_state_type ps_type, |
1640 | enum radeon_pm_state_type ps_type, |
1638 | int instance); |
1641 | int instance); |
1639 | /* |
1642 | /* |
1640 | * UVD |
1643 | * UVD |
1641 | */ |
1644 | */ |
1642 | #define RADEON_MAX_UVD_HANDLES 10 |
1645 | #define RADEON_MAX_UVD_HANDLES 10 |
1643 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
1646 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
1644 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
1647 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
1645 | 1648 | ||
1646 | struct radeon_uvd { |
1649 | struct radeon_uvd { |
1647 | struct radeon_bo *vcpu_bo; |
1650 | struct radeon_bo *vcpu_bo; |
1648 | void *cpu_addr; |
1651 | void *cpu_addr; |
1649 | uint64_t gpu_addr; |
1652 | uint64_t gpu_addr; |
1650 | void *saved_bo; |
1653 | void *saved_bo; |
1651 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1654 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1652 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
1655 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
1653 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
1656 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
1654 | struct delayed_work idle_work; |
1657 | struct delayed_work idle_work; |
1655 | }; |
1658 | }; |
1656 | 1659 | ||
1657 | int radeon_uvd_init(struct radeon_device *rdev); |
1660 | int radeon_uvd_init(struct radeon_device *rdev); |
1658 | void radeon_uvd_fini(struct radeon_device *rdev); |
1661 | void radeon_uvd_fini(struct radeon_device *rdev); |
1659 | int radeon_uvd_suspend(struct radeon_device *rdev); |
1662 | int radeon_uvd_suspend(struct radeon_device *rdev); |
1660 | int radeon_uvd_resume(struct radeon_device *rdev); |
1663 | int radeon_uvd_resume(struct radeon_device *rdev); |
1661 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
1664 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
1662 | uint32_t handle, struct radeon_fence **fence); |
1665 | uint32_t handle, struct radeon_fence **fence); |
1663 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
1666 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
1664 | uint32_t handle, struct radeon_fence **fence); |
1667 | uint32_t handle, struct radeon_fence **fence); |
1665 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); |
1668 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); |
1666 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1669 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1667 | struct drm_file *filp); |
1670 | struct drm_file *filp); |
1668 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
1671 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
1669 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
1672 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
1670 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1673 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1671 | unsigned vclk, unsigned dclk, |
1674 | unsigned vclk, unsigned dclk, |
1672 | unsigned vco_min, unsigned vco_max, |
1675 | unsigned vco_min, unsigned vco_max, |
1673 | unsigned fb_factor, unsigned fb_mask, |
1676 | unsigned fb_factor, unsigned fb_mask, |
1674 | unsigned pd_min, unsigned pd_max, |
1677 | unsigned pd_min, unsigned pd_max, |
1675 | unsigned pd_even, |
1678 | unsigned pd_even, |
1676 | unsigned *optimal_fb_div, |
1679 | unsigned *optimal_fb_div, |
1677 | unsigned *optimal_vclk_div, |
1680 | unsigned *optimal_vclk_div, |
1678 | unsigned *optimal_dclk_div); |
1681 | unsigned *optimal_dclk_div); |
1679 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
1682 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
1680 | unsigned cg_upll_func_cntl); |
1683 | unsigned cg_upll_func_cntl); |
1681 | 1684 | ||
1682 | /* |
1685 | /* |
1683 | * VCE |
1686 | * VCE |
1684 | */ |
1687 | */ |
1685 | #define RADEON_MAX_VCE_HANDLES 16 |
1688 | #define RADEON_MAX_VCE_HANDLES 16 |
1686 | #define RADEON_VCE_STACK_SIZE (1024*1024) |
1689 | #define RADEON_VCE_STACK_SIZE (1024*1024) |
1687 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) |
1690 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) |
1688 | 1691 | ||
1689 | struct radeon_vce { |
1692 | struct radeon_vce { |
1690 | struct radeon_bo *vcpu_bo; |
1693 | struct radeon_bo *vcpu_bo; |
1691 | uint64_t gpu_addr; |
1694 | uint64_t gpu_addr; |
1692 | unsigned fw_version; |
1695 | unsigned fw_version; |
1693 | unsigned fb_version; |
1696 | unsigned fb_version; |
1694 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1697 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1695 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
1698 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
1696 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
1699 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
1697 | struct delayed_work idle_work; |
1700 | struct delayed_work idle_work; |
1698 | }; |
1701 | }; |
1699 | 1702 | ||
1700 | int radeon_vce_init(struct radeon_device *rdev); |
1703 | int radeon_vce_init(struct radeon_device *rdev); |
1701 | void radeon_vce_fini(struct radeon_device *rdev); |
1704 | void radeon_vce_fini(struct radeon_device *rdev); |
1702 | int radeon_vce_suspend(struct radeon_device *rdev); |
1705 | int radeon_vce_suspend(struct radeon_device *rdev); |
1703 | int radeon_vce_resume(struct radeon_device *rdev); |
1706 | int radeon_vce_resume(struct radeon_device *rdev); |
1704 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
1707 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
1705 | uint32_t handle, struct radeon_fence **fence); |
1708 | uint32_t handle, struct radeon_fence **fence); |
1706 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
1709 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
1707 | uint32_t handle, struct radeon_fence **fence); |
1710 | uint32_t handle, struct radeon_fence **fence); |
1708 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
1711 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
1709 | void radeon_vce_note_usage(struct radeon_device *rdev); |
1712 | void radeon_vce_note_usage(struct radeon_device *rdev); |
1710 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
1713 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
1711 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1714 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1712 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
1715 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
1713 | struct radeon_ring *ring, |
1716 | struct radeon_ring *ring, |
1714 | struct radeon_semaphore *semaphore, |
1717 | struct radeon_semaphore *semaphore, |
1715 | bool emit_wait); |
1718 | bool emit_wait); |
1716 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1719 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1717 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
1720 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
1718 | struct radeon_fence *fence); |
1721 | struct radeon_fence *fence); |
1719 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1722 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1720 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1723 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1721 | 1724 | ||
1722 | struct r600_audio_pin { |
1725 | struct r600_audio_pin { |
1723 | int channels; |
1726 | int channels; |
1724 | int rate; |
1727 | int rate; |
1725 | int bits_per_sample; |
1728 | int bits_per_sample; |
1726 | u8 status_bits; |
1729 | u8 status_bits; |
1727 | u8 category_code; |
1730 | u8 category_code; |
1728 | u32 offset; |
1731 | u32 offset; |
1729 | bool connected; |
1732 | bool connected; |
1730 | u32 id; |
1733 | u32 id; |
1731 | }; |
1734 | }; |
1732 | 1735 | ||
1733 | struct r600_audio { |
1736 | struct r600_audio { |
1734 | bool enabled; |
1737 | bool enabled; |
1735 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
1738 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
1736 | int num_pins; |
1739 | int num_pins; |
1737 | }; |
1740 | }; |
1738 | 1741 | ||
1739 | /* |
1742 | /* |
1740 | * Benchmarking |
1743 | * Benchmarking |
1741 | */ |
1744 | */ |
1742 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
1745 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
1743 | 1746 | ||
1744 | 1747 | ||
1745 | /* |
1748 | /* |
1746 | * Testing |
1749 | * Testing |
1747 | */ |
1750 | */ |
1748 | void radeon_test_moves(struct radeon_device *rdev); |
1751 | void radeon_test_moves(struct radeon_device *rdev); |
1749 | void radeon_test_ring_sync(struct radeon_device *rdev, |
1752 | void radeon_test_ring_sync(struct radeon_device *rdev, |
1750 | struct radeon_ring *cpA, |
1753 | struct radeon_ring *cpA, |
1751 | struct radeon_ring *cpB); |
1754 | struct radeon_ring *cpB); |
1752 | void radeon_test_syncing(struct radeon_device *rdev); |
1755 | void radeon_test_syncing(struct radeon_device *rdev); |
1753 | 1756 | ||
1754 | 1757 | ||
1755 | /* |
1758 | /* |
1756 | * Debugfs |
1759 | * Debugfs |
1757 | */ |
1760 | */ |
1758 | struct radeon_debugfs { |
1761 | struct radeon_debugfs { |
1759 | struct drm_info_list *files; |
1762 | struct drm_info_list *files; |
1760 | unsigned num_files; |
1763 | unsigned num_files; |
1761 | }; |
1764 | }; |
1762 | 1765 | ||
1763 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1766 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1764 | struct drm_info_list *files, |
1767 | struct drm_info_list *files, |
1765 | unsigned nfiles); |
1768 | unsigned nfiles); |
1766 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
1769 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
1767 | 1770 | ||
1768 | /* |
1771 | /* |
1769 | * ASIC ring specific functions. |
1772 | * ASIC ring specific functions. |
1770 | */ |
1773 | */ |
1771 | struct radeon_asic_ring { |
1774 | struct radeon_asic_ring { |
1772 | /* ring read/write ptr handling */ |
1775 | /* ring read/write ptr handling */ |
1773 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1776 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1774 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1777 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1775 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1778 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1776 | 1779 | ||
1777 | /* validating and patching of IBs */ |
1780 | /* validating and patching of IBs */ |
1778 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
1781 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
1779 | int (*cs_parse)(struct radeon_cs_parser *p); |
1782 | int (*cs_parse)(struct radeon_cs_parser *p); |
1780 | 1783 | ||
1781 | /* command emmit functions */ |
1784 | /* command emmit functions */ |
1782 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1785 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1783 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
1786 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
1784 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1787 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1785 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1788 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1786 | struct radeon_semaphore *semaphore, bool emit_wait); |
1789 | struct radeon_semaphore *semaphore, bool emit_wait); |
1787 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
1790 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
1788 | 1791 | ||
1789 | /* testing functions */ |
1792 | /* testing functions */ |
1790 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1793 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1791 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1794 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1792 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
1795 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
1793 | 1796 | ||
1794 | /* deprecated */ |
1797 | /* deprecated */ |
1795 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1798 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1796 | }; |
1799 | }; |
1797 | 1800 | ||
1798 | /* |
1801 | /* |
1799 | * ASIC specific functions. |
1802 | * ASIC specific functions. |
1800 | */ |
1803 | */ |
1801 | struct radeon_asic { |
1804 | struct radeon_asic { |
1802 | int (*init)(struct radeon_device *rdev); |
1805 | int (*init)(struct radeon_device *rdev); |
1803 | void (*fini)(struct radeon_device *rdev); |
1806 | void (*fini)(struct radeon_device *rdev); |
1804 | int (*resume)(struct radeon_device *rdev); |
1807 | int (*resume)(struct radeon_device *rdev); |
1805 | int (*suspend)(struct radeon_device *rdev); |
1808 | int (*suspend)(struct radeon_device *rdev); |
1806 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
1809 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
1807 | int (*asic_reset)(struct radeon_device *rdev); |
1810 | int (*asic_reset)(struct radeon_device *rdev); |
1808 | /* Flush the HDP cache via MMIO */ |
1811 | /* Flush the HDP cache via MMIO */ |
1809 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
1812 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
1810 | /* check if 3D engine is idle */ |
1813 | /* check if 3D engine is idle */ |
1811 | bool (*gui_idle)(struct radeon_device *rdev); |
1814 | bool (*gui_idle)(struct radeon_device *rdev); |
1812 | /* wait for mc_idle */ |
1815 | /* wait for mc_idle */ |
1813 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1816 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1814 | /* get the reference clock */ |
1817 | /* get the reference clock */ |
1815 | u32 (*get_xclk)(struct radeon_device *rdev); |
1818 | u32 (*get_xclk)(struct radeon_device *rdev); |
1816 | /* get the gpu clock counter */ |
1819 | /* get the gpu clock counter */ |
1817 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
1820 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
1818 | /* gart */ |
1821 | /* gart */ |
1819 | struct { |
1822 | struct { |
1820 | void (*tlb_flush)(struct radeon_device *rdev); |
1823 | void (*tlb_flush)(struct radeon_device *rdev); |
1821 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
1824 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
1822 | uint64_t addr, uint32_t flags); |
1825 | uint64_t addr, uint32_t flags); |
1823 | } gart; |
1826 | } gart; |
1824 | struct { |
1827 | struct { |
1825 | int (*init)(struct radeon_device *rdev); |
1828 | int (*init)(struct radeon_device *rdev); |
1826 | void (*fini)(struct radeon_device *rdev); |
1829 | void (*fini)(struct radeon_device *rdev); |
1827 | void (*copy_pages)(struct radeon_device *rdev, |
1830 | void (*copy_pages)(struct radeon_device *rdev, |
1828 | struct radeon_ib *ib, |
1831 | struct radeon_ib *ib, |
1829 | uint64_t pe, uint64_t src, |
1832 | uint64_t pe, uint64_t src, |
1830 | unsigned count); |
1833 | unsigned count); |
1831 | void (*write_pages)(struct radeon_device *rdev, |
1834 | void (*write_pages)(struct radeon_device *rdev, |
1832 | struct radeon_ib *ib, |
1835 | struct radeon_ib *ib, |
1833 | uint64_t pe, |
1836 | uint64_t pe, |
1834 | uint64_t addr, unsigned count, |
1837 | uint64_t addr, unsigned count, |
1835 | uint32_t incr, uint32_t flags); |
1838 | uint32_t incr, uint32_t flags); |
1836 | void (*set_pages)(struct radeon_device *rdev, |
1839 | void (*set_pages)(struct radeon_device *rdev, |
1837 | struct radeon_ib *ib, |
1840 | struct radeon_ib *ib, |
1838 | uint64_t pe, |
1841 | uint64_t pe, |
1839 | uint64_t addr, unsigned count, |
1842 | uint64_t addr, unsigned count, |
1840 | uint32_t incr, uint32_t flags); |
1843 | uint32_t incr, uint32_t flags); |
1841 | void (*pad_ib)(struct radeon_ib *ib); |
1844 | void (*pad_ib)(struct radeon_ib *ib); |
1842 | } vm; |
1845 | } vm; |
1843 | /* ring specific callbacks */ |
1846 | /* ring specific callbacks */ |
1844 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
1847 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
1845 | /* irqs */ |
1848 | /* irqs */ |
1846 | struct { |
1849 | struct { |
1847 | int (*set)(struct radeon_device *rdev); |
1850 | int (*set)(struct radeon_device *rdev); |
1848 | int (*process)(struct radeon_device *rdev); |
1851 | int (*process)(struct radeon_device *rdev); |
1849 | } irq; |
1852 | } irq; |
1850 | /* displays */ |
1853 | /* displays */ |
1851 | struct { |
1854 | struct { |
1852 | /* display watermarks */ |
1855 | /* display watermarks */ |
1853 | void (*bandwidth_update)(struct radeon_device *rdev); |
1856 | void (*bandwidth_update)(struct radeon_device *rdev); |
1854 | /* get frame count */ |
1857 | /* get frame count */ |
1855 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1858 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1856 | /* wait for vblank */ |
1859 | /* wait for vblank */ |
1857 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
1860 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
1858 | /* set backlight level */ |
1861 | /* set backlight level */ |
1859 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
1862 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
1860 | /* get backlight level */ |
1863 | /* get backlight level */ |
1861 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
1864 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
1862 | /* audio callbacks */ |
1865 | /* audio callbacks */ |
1863 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
1866 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
1864 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1867 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1865 | } display; |
1868 | } display; |
1866 | /* copy functions for bo handling */ |
1869 | /* copy functions for bo handling */ |
1867 | struct { |
1870 | struct { |
1868 | int (*blit)(struct radeon_device *rdev, |
1871 | int (*blit)(struct radeon_device *rdev, |
1869 | uint64_t src_offset, |
1872 | uint64_t src_offset, |
1870 | uint64_t dst_offset, |
1873 | uint64_t dst_offset, |
1871 | unsigned num_gpu_pages, |
1874 | unsigned num_gpu_pages, |
1872 | struct radeon_fence **fence); |
1875 | struct radeon_fence **fence); |
1873 | u32 blit_ring_index; |
1876 | u32 blit_ring_index; |
1874 | int (*dma)(struct radeon_device *rdev, |
1877 | int (*dma)(struct radeon_device *rdev, |
1875 | uint64_t src_offset, |
1878 | uint64_t src_offset, |
1876 | uint64_t dst_offset, |
1879 | uint64_t dst_offset, |
1877 | unsigned num_gpu_pages, |
1880 | unsigned num_gpu_pages, |
1878 | struct radeon_fence **fence); |
1881 | struct radeon_fence **fence); |
1879 | u32 dma_ring_index; |
1882 | u32 dma_ring_index; |
1880 | /* method used for bo copy */ |
1883 | /* method used for bo copy */ |
1881 | int (*copy)(struct radeon_device *rdev, |
1884 | int (*copy)(struct radeon_device *rdev, |
1882 | uint64_t src_offset, |
1885 | uint64_t src_offset, |
1883 | uint64_t dst_offset, |
1886 | uint64_t dst_offset, |
1884 | unsigned num_gpu_pages, |
1887 | unsigned num_gpu_pages, |
1885 | struct radeon_fence **fence); |
1888 | struct radeon_fence **fence); |
1886 | /* ring used for bo copies */ |
1889 | /* ring used for bo copies */ |
1887 | u32 copy_ring_index; |
1890 | u32 copy_ring_index; |
1888 | } copy; |
1891 | } copy; |
1889 | /* surfaces */ |
1892 | /* surfaces */ |
1890 | struct { |
1893 | struct { |
1891 | int (*set_reg)(struct radeon_device *rdev, int reg, |
1894 | int (*set_reg)(struct radeon_device *rdev, int reg, |
1892 | uint32_t tiling_flags, uint32_t pitch, |
1895 | uint32_t tiling_flags, uint32_t pitch, |
1893 | uint32_t offset, uint32_t obj_size); |
1896 | uint32_t offset, uint32_t obj_size); |
1894 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
1897 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
1895 | } surface; |
1898 | } surface; |
1896 | /* hotplug detect */ |
1899 | /* hotplug detect */ |
1897 | struct { |
1900 | struct { |
1898 | void (*init)(struct radeon_device *rdev); |
1901 | void (*init)(struct radeon_device *rdev); |
1899 | void (*fini)(struct radeon_device *rdev); |
1902 | void (*fini)(struct radeon_device *rdev); |
1900 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1903 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1901 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1904 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1902 | } hpd; |
1905 | } hpd; |
1903 | /* static power management */ |
1906 | /* static power management */ |
1904 | struct { |
1907 | struct { |
1905 | void (*misc)(struct radeon_device *rdev); |
1908 | void (*misc)(struct radeon_device *rdev); |
1906 | void (*prepare)(struct radeon_device *rdev); |
1909 | void (*prepare)(struct radeon_device *rdev); |
1907 | void (*finish)(struct radeon_device *rdev); |
1910 | void (*finish)(struct radeon_device *rdev); |
1908 | void (*init_profile)(struct radeon_device *rdev); |
1911 | void (*init_profile)(struct radeon_device *rdev); |
1909 | void (*get_dynpm_state)(struct radeon_device *rdev); |
1912 | void (*get_dynpm_state)(struct radeon_device *rdev); |
1910 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1913 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1911 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1914 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1912 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1915 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1913 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1916 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1914 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1917 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1915 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1918 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1916 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
1919 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
1917 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
1920 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
1918 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
1921 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
1919 | int (*get_temperature)(struct radeon_device *rdev); |
1922 | int (*get_temperature)(struct radeon_device *rdev); |
1920 | } pm; |
1923 | } pm; |
1921 | /* dynamic power management */ |
1924 | /* dynamic power management */ |
1922 | struct { |
1925 | struct { |
1923 | int (*init)(struct radeon_device *rdev); |
1926 | int (*init)(struct radeon_device *rdev); |
1924 | void (*setup_asic)(struct radeon_device *rdev); |
1927 | void (*setup_asic)(struct radeon_device *rdev); |
1925 | int (*enable)(struct radeon_device *rdev); |
1928 | int (*enable)(struct radeon_device *rdev); |
1926 | int (*late_enable)(struct radeon_device *rdev); |
1929 | int (*late_enable)(struct radeon_device *rdev); |
1927 | void (*disable)(struct radeon_device *rdev); |
1930 | void (*disable)(struct radeon_device *rdev); |
1928 | int (*pre_set_power_state)(struct radeon_device *rdev); |
1931 | int (*pre_set_power_state)(struct radeon_device *rdev); |
1929 | int (*set_power_state)(struct radeon_device *rdev); |
1932 | int (*set_power_state)(struct radeon_device *rdev); |
1930 | void (*post_set_power_state)(struct radeon_device *rdev); |
1933 | void (*post_set_power_state)(struct radeon_device *rdev); |
1931 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1934 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1932 | void (*fini)(struct radeon_device *rdev); |
1935 | void (*fini)(struct radeon_device *rdev); |
1933 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
1936 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
1934 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
1937 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
1935 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
1938 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
1936 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
1939 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
1937 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
1940 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
1938 | bool (*vblank_too_short)(struct radeon_device *rdev); |
1941 | bool (*vblank_too_short)(struct radeon_device *rdev); |
1939 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1942 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1940 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
1943 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
1941 | } dpm; |
1944 | } dpm; |
1942 | /* pageflipping */ |
1945 | /* pageflipping */ |
1943 | struct { |
1946 | struct { |
1944 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1947 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1945 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
1948 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
1946 | } pflip; |
1949 | } pflip; |
1947 | }; |
1950 | }; |
1948 | 1951 | ||
1949 | /* |
1952 | /* |
1950 | * Asic structures |
1953 | * Asic structures |
1951 | */ |
1954 | */ |
1952 | struct r100_asic { |
1955 | struct r100_asic { |
1953 | const unsigned *reg_safe_bm; |
1956 | const unsigned *reg_safe_bm; |
1954 | unsigned reg_safe_bm_size; |
1957 | unsigned reg_safe_bm_size; |
1955 | u32 hdp_cntl; |
1958 | u32 hdp_cntl; |
1956 | }; |
1959 | }; |
1957 | 1960 | ||
1958 | struct r300_asic { |
1961 | struct r300_asic { |
1959 | const unsigned *reg_safe_bm; |
1962 | const unsigned *reg_safe_bm; |
1960 | unsigned reg_safe_bm_size; |
1963 | unsigned reg_safe_bm_size; |
1961 | u32 resync_scratch; |
1964 | u32 resync_scratch; |
1962 | u32 hdp_cntl; |
1965 | u32 hdp_cntl; |
1963 | }; |
1966 | }; |
1964 | 1967 | ||
1965 | struct r600_asic { |
1968 | struct r600_asic { |
1966 | unsigned max_pipes; |
1969 | unsigned max_pipes; |
1967 | unsigned max_tile_pipes; |
1970 | unsigned max_tile_pipes; |
1968 | unsigned max_simds; |
1971 | unsigned max_simds; |
1969 | unsigned max_backends; |
1972 | unsigned max_backends; |
1970 | unsigned max_gprs; |
1973 | unsigned max_gprs; |
1971 | unsigned max_threads; |
1974 | unsigned max_threads; |
1972 | unsigned max_stack_entries; |
1975 | unsigned max_stack_entries; |
1973 | unsigned max_hw_contexts; |
1976 | unsigned max_hw_contexts; |
1974 | unsigned max_gs_threads; |
1977 | unsigned max_gs_threads; |
1975 | unsigned sx_max_export_size; |
1978 | unsigned sx_max_export_size; |
1976 | unsigned sx_max_export_pos_size; |
1979 | unsigned sx_max_export_pos_size; |
1977 | unsigned sx_max_export_smx_size; |
1980 | unsigned sx_max_export_smx_size; |
1978 | unsigned sq_num_cf_insts; |
1981 | unsigned sq_num_cf_insts; |
1979 | unsigned tiling_nbanks; |
1982 | unsigned tiling_nbanks; |
1980 | unsigned tiling_npipes; |
1983 | unsigned tiling_npipes; |
1981 | unsigned tiling_group_size; |
1984 | unsigned tiling_group_size; |
1982 | unsigned tile_config; |
1985 | unsigned tile_config; |
1983 | unsigned backend_map; |
1986 | unsigned backend_map; |
1984 | unsigned active_simds; |
1987 | unsigned active_simds; |
1985 | }; |
1988 | }; |
1986 | 1989 | ||
1987 | struct rv770_asic { |
1990 | struct rv770_asic { |
1988 | unsigned max_pipes; |
1991 | unsigned max_pipes; |
1989 | unsigned max_tile_pipes; |
1992 | unsigned max_tile_pipes; |
1990 | unsigned max_simds; |
1993 | unsigned max_simds; |
1991 | unsigned max_backends; |
1994 | unsigned max_backends; |
1992 | unsigned max_gprs; |
1995 | unsigned max_gprs; |
1993 | unsigned max_threads; |
1996 | unsigned max_threads; |
1994 | unsigned max_stack_entries; |
1997 | unsigned max_stack_entries; |
1995 | unsigned max_hw_contexts; |
1998 | unsigned max_hw_contexts; |
1996 | unsigned max_gs_threads; |
1999 | unsigned max_gs_threads; |
1997 | unsigned sx_max_export_size; |
2000 | unsigned sx_max_export_size; |
1998 | unsigned sx_max_export_pos_size; |
2001 | unsigned sx_max_export_pos_size; |
1999 | unsigned sx_max_export_smx_size; |
2002 | unsigned sx_max_export_smx_size; |
2000 | unsigned sq_num_cf_insts; |
2003 | unsigned sq_num_cf_insts; |
2001 | unsigned sx_num_of_sets; |
2004 | unsigned sx_num_of_sets; |
2002 | unsigned sc_prim_fifo_size; |
2005 | unsigned sc_prim_fifo_size; |
2003 | unsigned sc_hiz_tile_fifo_size; |
2006 | unsigned sc_hiz_tile_fifo_size; |
2004 | unsigned sc_earlyz_tile_fifo_fize; |
2007 | unsigned sc_earlyz_tile_fifo_fize; |
2005 | unsigned tiling_nbanks; |
2008 | unsigned tiling_nbanks; |
2006 | unsigned tiling_npipes; |
2009 | unsigned tiling_npipes; |
2007 | unsigned tiling_group_size; |
2010 | unsigned tiling_group_size; |
2008 | unsigned tile_config; |
2011 | unsigned tile_config; |
2009 | unsigned backend_map; |
2012 | unsigned backend_map; |
2010 | unsigned active_simds; |
2013 | unsigned active_simds; |
2011 | }; |
2014 | }; |
2012 | 2015 | ||
2013 | struct evergreen_asic { |
2016 | struct evergreen_asic { |
2014 | unsigned num_ses; |
2017 | unsigned num_ses; |
2015 | unsigned max_pipes; |
2018 | unsigned max_pipes; |
2016 | unsigned max_tile_pipes; |
2019 | unsigned max_tile_pipes; |
2017 | unsigned max_simds; |
2020 | unsigned max_simds; |
2018 | unsigned max_backends; |
2021 | unsigned max_backends; |
2019 | unsigned max_gprs; |
2022 | unsigned max_gprs; |
2020 | unsigned max_threads; |
2023 | unsigned max_threads; |
2021 | unsigned max_stack_entries; |
2024 | unsigned max_stack_entries; |
2022 | unsigned max_hw_contexts; |
2025 | unsigned max_hw_contexts; |
2023 | unsigned max_gs_threads; |
2026 | unsigned max_gs_threads; |
2024 | unsigned sx_max_export_size; |
2027 | unsigned sx_max_export_size; |
2025 | unsigned sx_max_export_pos_size; |
2028 | unsigned sx_max_export_pos_size; |
2026 | unsigned sx_max_export_smx_size; |
2029 | unsigned sx_max_export_smx_size; |
2027 | unsigned sq_num_cf_insts; |
2030 | unsigned sq_num_cf_insts; |
2028 | unsigned sx_num_of_sets; |
2031 | unsigned sx_num_of_sets; |
2029 | unsigned sc_prim_fifo_size; |
2032 | unsigned sc_prim_fifo_size; |
2030 | unsigned sc_hiz_tile_fifo_size; |
2033 | unsigned sc_hiz_tile_fifo_size; |
2031 | unsigned sc_earlyz_tile_fifo_size; |
2034 | unsigned sc_earlyz_tile_fifo_size; |
2032 | unsigned tiling_nbanks; |
2035 | unsigned tiling_nbanks; |
2033 | unsigned tiling_npipes; |
2036 | unsigned tiling_npipes; |
2034 | unsigned tiling_group_size; |
2037 | unsigned tiling_group_size; |
2035 | unsigned tile_config; |
2038 | unsigned tile_config; |
2036 | unsigned backend_map; |
2039 | unsigned backend_map; |
2037 | unsigned active_simds; |
2040 | unsigned active_simds; |
2038 | }; |
2041 | }; |
2039 | 2042 | ||
2040 | struct cayman_asic { |
2043 | struct cayman_asic { |
2041 | unsigned max_shader_engines; |
2044 | unsigned max_shader_engines; |
2042 | unsigned max_pipes_per_simd; |
2045 | unsigned max_pipes_per_simd; |
2043 | unsigned max_tile_pipes; |
2046 | unsigned max_tile_pipes; |
2044 | unsigned max_simds_per_se; |
2047 | unsigned max_simds_per_se; |
2045 | unsigned max_backends_per_se; |
2048 | unsigned max_backends_per_se; |
2046 | unsigned max_texture_channel_caches; |
2049 | unsigned max_texture_channel_caches; |
2047 | unsigned max_gprs; |
2050 | unsigned max_gprs; |
2048 | unsigned max_threads; |
2051 | unsigned max_threads; |
2049 | unsigned max_gs_threads; |
2052 | unsigned max_gs_threads; |
2050 | unsigned max_stack_entries; |
2053 | unsigned max_stack_entries; |
2051 | unsigned sx_num_of_sets; |
2054 | unsigned sx_num_of_sets; |
2052 | unsigned sx_max_export_size; |
2055 | unsigned sx_max_export_size; |
2053 | unsigned sx_max_export_pos_size; |
2056 | unsigned sx_max_export_pos_size; |
2054 | unsigned sx_max_export_smx_size; |
2057 | unsigned sx_max_export_smx_size; |
2055 | unsigned max_hw_contexts; |
2058 | unsigned max_hw_contexts; |
2056 | unsigned sq_num_cf_insts; |
2059 | unsigned sq_num_cf_insts; |
2057 | unsigned sc_prim_fifo_size; |
2060 | unsigned sc_prim_fifo_size; |
2058 | unsigned sc_hiz_tile_fifo_size; |
2061 | unsigned sc_hiz_tile_fifo_size; |
2059 | unsigned sc_earlyz_tile_fifo_size; |
2062 | unsigned sc_earlyz_tile_fifo_size; |
2060 | 2063 | ||
2061 | unsigned num_shader_engines; |
2064 | unsigned num_shader_engines; |
2062 | unsigned num_shader_pipes_per_simd; |
2065 | unsigned num_shader_pipes_per_simd; |
2063 | unsigned num_tile_pipes; |
2066 | unsigned num_tile_pipes; |
2064 | unsigned num_simds_per_se; |
2067 | unsigned num_simds_per_se; |
2065 | unsigned num_backends_per_se; |
2068 | unsigned num_backends_per_se; |
2066 | unsigned backend_disable_mask_per_asic; |
2069 | unsigned backend_disable_mask_per_asic; |
2067 | unsigned backend_map; |
2070 | unsigned backend_map; |
2068 | unsigned num_texture_channel_caches; |
2071 | unsigned num_texture_channel_caches; |
2069 | unsigned mem_max_burst_length_bytes; |
2072 | unsigned mem_max_burst_length_bytes; |
2070 | unsigned mem_row_size_in_kb; |
2073 | unsigned mem_row_size_in_kb; |
2071 | unsigned shader_engine_tile_size; |
2074 | unsigned shader_engine_tile_size; |
2072 | unsigned num_gpus; |
2075 | unsigned num_gpus; |
2073 | unsigned multi_gpu_tile_size; |
2076 | unsigned multi_gpu_tile_size; |
2074 | 2077 | ||
2075 | unsigned tile_config; |
2078 | unsigned tile_config; |
2076 | unsigned active_simds; |
2079 | unsigned active_simds; |
2077 | }; |
2080 | }; |
2078 | 2081 | ||
2079 | struct si_asic { |
2082 | struct si_asic { |
2080 | unsigned max_shader_engines; |
2083 | unsigned max_shader_engines; |
2081 | unsigned max_tile_pipes; |
2084 | unsigned max_tile_pipes; |
2082 | unsigned max_cu_per_sh; |
2085 | unsigned max_cu_per_sh; |
2083 | unsigned max_sh_per_se; |
2086 | unsigned max_sh_per_se; |
2084 | unsigned max_backends_per_se; |
2087 | unsigned max_backends_per_se; |
2085 | unsigned max_texture_channel_caches; |
2088 | unsigned max_texture_channel_caches; |
2086 | unsigned max_gprs; |
2089 | unsigned max_gprs; |
2087 | unsigned max_gs_threads; |
2090 | unsigned max_gs_threads; |
2088 | unsigned max_hw_contexts; |
2091 | unsigned max_hw_contexts; |
2089 | unsigned sc_prim_fifo_size_frontend; |
2092 | unsigned sc_prim_fifo_size_frontend; |
2090 | unsigned sc_prim_fifo_size_backend; |
2093 | unsigned sc_prim_fifo_size_backend; |
2091 | unsigned sc_hiz_tile_fifo_size; |
2094 | unsigned sc_hiz_tile_fifo_size; |
2092 | unsigned sc_earlyz_tile_fifo_size; |
2095 | unsigned sc_earlyz_tile_fifo_size; |
2093 | 2096 | ||
2094 | unsigned num_tile_pipes; |
2097 | unsigned num_tile_pipes; |
2095 | unsigned backend_enable_mask; |
2098 | unsigned backend_enable_mask; |
2096 | unsigned backend_disable_mask_per_asic; |
2099 | unsigned backend_disable_mask_per_asic; |
2097 | unsigned backend_map; |
2100 | unsigned backend_map; |
2098 | unsigned num_texture_channel_caches; |
2101 | unsigned num_texture_channel_caches; |
2099 | unsigned mem_max_burst_length_bytes; |
2102 | unsigned mem_max_burst_length_bytes; |
2100 | unsigned mem_row_size_in_kb; |
2103 | unsigned mem_row_size_in_kb; |
2101 | unsigned shader_engine_tile_size; |
2104 | unsigned shader_engine_tile_size; |
2102 | unsigned num_gpus; |
2105 | unsigned num_gpus; |
2103 | unsigned multi_gpu_tile_size; |
2106 | unsigned multi_gpu_tile_size; |
2104 | 2107 | ||
2105 | unsigned tile_config; |
2108 | unsigned tile_config; |
2106 | uint32_t tile_mode_array[32]; |
2109 | uint32_t tile_mode_array[32]; |
2107 | uint32_t active_cus; |
2110 | uint32_t active_cus; |
2108 | }; |
2111 | }; |
2109 | 2112 | ||
2110 | struct cik_asic { |
2113 | struct cik_asic { |
2111 | unsigned max_shader_engines; |
2114 | unsigned max_shader_engines; |
2112 | unsigned max_tile_pipes; |
2115 | unsigned max_tile_pipes; |
2113 | unsigned max_cu_per_sh; |
2116 | unsigned max_cu_per_sh; |
2114 | unsigned max_sh_per_se; |
2117 | unsigned max_sh_per_se; |
2115 | unsigned max_backends_per_se; |
2118 | unsigned max_backends_per_se; |
2116 | unsigned max_texture_channel_caches; |
2119 | unsigned max_texture_channel_caches; |
2117 | unsigned max_gprs; |
2120 | unsigned max_gprs; |
2118 | unsigned max_gs_threads; |
2121 | unsigned max_gs_threads; |
2119 | unsigned max_hw_contexts; |
2122 | unsigned max_hw_contexts; |
2120 | unsigned sc_prim_fifo_size_frontend; |
2123 | unsigned sc_prim_fifo_size_frontend; |
2121 | unsigned sc_prim_fifo_size_backend; |
2124 | unsigned sc_prim_fifo_size_backend; |
2122 | unsigned sc_hiz_tile_fifo_size; |
2125 | unsigned sc_hiz_tile_fifo_size; |
2123 | unsigned sc_earlyz_tile_fifo_size; |
2126 | unsigned sc_earlyz_tile_fifo_size; |
2124 | 2127 | ||
2125 | unsigned num_tile_pipes; |
2128 | unsigned num_tile_pipes; |
2126 | unsigned backend_enable_mask; |
2129 | unsigned backend_enable_mask; |
2127 | unsigned backend_disable_mask_per_asic; |
2130 | unsigned backend_disable_mask_per_asic; |
2128 | unsigned backend_map; |
2131 | unsigned backend_map; |
2129 | unsigned num_texture_channel_caches; |
2132 | unsigned num_texture_channel_caches; |
2130 | unsigned mem_max_burst_length_bytes; |
2133 | unsigned mem_max_burst_length_bytes; |
2131 | unsigned mem_row_size_in_kb; |
2134 | unsigned mem_row_size_in_kb; |
2132 | unsigned shader_engine_tile_size; |
2135 | unsigned shader_engine_tile_size; |
2133 | unsigned num_gpus; |
2136 | unsigned num_gpus; |
2134 | unsigned multi_gpu_tile_size; |
2137 | unsigned multi_gpu_tile_size; |
2135 | 2138 | ||
2136 | unsigned tile_config; |
2139 | unsigned tile_config; |
2137 | uint32_t tile_mode_array[32]; |
2140 | uint32_t tile_mode_array[32]; |
2138 | uint32_t macrotile_mode_array[16]; |
2141 | uint32_t macrotile_mode_array[16]; |
2139 | uint32_t active_cus; |
2142 | uint32_t active_cus; |
2140 | }; |
2143 | }; |
2141 | 2144 | ||
2142 | union radeon_asic_config { |
2145 | union radeon_asic_config { |
2143 | struct r300_asic r300; |
2146 | struct r300_asic r300; |
2144 | struct r100_asic r100; |
2147 | struct r100_asic r100; |
2145 | struct r600_asic r600; |
2148 | struct r600_asic r600; |
2146 | struct rv770_asic rv770; |
2149 | struct rv770_asic rv770; |
2147 | struct evergreen_asic evergreen; |
2150 | struct evergreen_asic evergreen; |
2148 | struct cayman_asic cayman; |
2151 | struct cayman_asic cayman; |
2149 | struct si_asic si; |
2152 | struct si_asic si; |
2150 | struct cik_asic cik; |
2153 | struct cik_asic cik; |
2151 | }; |
2154 | }; |
2152 | 2155 | ||
2153 | /* |
2156 | /* |
2154 | * asic initizalization from radeon_asic.c |
2157 | * asic initizalization from radeon_asic.c |
2155 | */ |
2158 | */ |
2156 | void radeon_agp_disable(struct radeon_device *rdev); |
2159 | void radeon_agp_disable(struct radeon_device *rdev); |
2157 | int radeon_asic_init(struct radeon_device *rdev); |
2160 | int radeon_asic_init(struct radeon_device *rdev); |
2158 | 2161 | ||
2159 | 2162 | ||
2160 | 2163 | ||
2161 | /* VRAM scratch page for HDP bug, default vram page */ |
2164 | /* VRAM scratch page for HDP bug, default vram page */ |
2162 | struct r600_vram_scratch { |
2165 | struct r600_vram_scratch { |
2163 | struct radeon_bo *robj; |
2166 | struct radeon_bo *robj; |
2164 | volatile uint32_t *ptr; |
2167 | volatile uint32_t *ptr; |
2165 | u64 gpu_addr; |
2168 | u64 gpu_addr; |
2166 | }; |
2169 | }; |
2167 | 2170 | ||
2168 | /* |
2171 | /* |
2169 | * ACPI |
2172 | * ACPI |
2170 | */ |
2173 | */ |
2171 | struct radeon_atif_notification_cfg { |
2174 | struct radeon_atif_notification_cfg { |
2172 | bool enabled; |
2175 | bool enabled; |
2173 | int command_code; |
2176 | int command_code; |
2174 | }; |
2177 | }; |
2175 | 2178 | ||
2176 | struct radeon_atif_notifications { |
2179 | struct radeon_atif_notifications { |
2177 | bool display_switch; |
2180 | bool display_switch; |
2178 | bool expansion_mode_change; |
2181 | bool expansion_mode_change; |
2179 | bool thermal_state; |
2182 | bool thermal_state; |
2180 | bool forced_power_state; |
2183 | bool forced_power_state; |
2181 | bool system_power_state; |
2184 | bool system_power_state; |
2182 | bool display_conf_change; |
2185 | bool display_conf_change; |
2183 | bool px_gfx_switch; |
2186 | bool px_gfx_switch; |
2184 | bool brightness_change; |
2187 | bool brightness_change; |
2185 | bool dgpu_display_event; |
2188 | bool dgpu_display_event; |
2186 | }; |
2189 | }; |
2187 | 2190 | ||
2188 | struct radeon_atif_functions { |
2191 | struct radeon_atif_functions { |
2189 | bool system_params; |
2192 | bool system_params; |
2190 | bool sbios_requests; |
2193 | bool sbios_requests; |
2191 | bool select_active_disp; |
2194 | bool select_active_disp; |
2192 | bool lid_state; |
2195 | bool lid_state; |
2193 | bool get_tv_standard; |
2196 | bool get_tv_standard; |
2194 | bool set_tv_standard; |
2197 | bool set_tv_standard; |
2195 | bool get_panel_expansion_mode; |
2198 | bool get_panel_expansion_mode; |
2196 | bool set_panel_expansion_mode; |
2199 | bool set_panel_expansion_mode; |
2197 | bool temperature_change; |
2200 | bool temperature_change; |
2198 | bool graphics_device_types; |
2201 | bool graphics_device_types; |
2199 | }; |
2202 | }; |
2200 | 2203 | ||
2201 | struct radeon_atif { |
2204 | struct radeon_atif { |
2202 | struct radeon_atif_notifications notifications; |
2205 | struct radeon_atif_notifications notifications; |
2203 | struct radeon_atif_functions functions; |
2206 | struct radeon_atif_functions functions; |
2204 | struct radeon_atif_notification_cfg notification_cfg; |
2207 | struct radeon_atif_notification_cfg notification_cfg; |
2205 | struct radeon_encoder *encoder_for_bl; |
2208 | struct radeon_encoder *encoder_for_bl; |
2206 | }; |
2209 | }; |
2207 | 2210 | ||
2208 | struct radeon_atcs_functions { |
2211 | struct radeon_atcs_functions { |
2209 | bool get_ext_state; |
2212 | bool get_ext_state; |
2210 | bool pcie_perf_req; |
2213 | bool pcie_perf_req; |
2211 | bool pcie_dev_rdy; |
2214 | bool pcie_dev_rdy; |
2212 | bool pcie_bus_width; |
2215 | bool pcie_bus_width; |
2213 | }; |
2216 | }; |
2214 | 2217 | ||
2215 | struct radeon_atcs { |
2218 | struct radeon_atcs { |
2216 | struct radeon_atcs_functions functions; |
2219 | struct radeon_atcs_functions functions; |
2217 | }; |
2220 | }; |
2218 | 2221 | ||
2219 | /* |
2222 | /* |
2220 | * Core structure, functions and helpers. |
2223 | * Core structure, functions and helpers. |
2221 | */ |
2224 | */ |
2222 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
2225 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
2223 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
2226 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
2224 | 2227 | ||
2225 | struct radeon_device { |
2228 | struct radeon_device { |
2226 | struct device *dev; |
2229 | struct device *dev; |
2227 | struct drm_device *ddev; |
2230 | struct drm_device *ddev; |
2228 | struct pci_dev *pdev; |
2231 | struct pci_dev *pdev; |
2229 | struct rw_semaphore exclusive_lock; |
2232 | struct rw_semaphore exclusive_lock; |
2230 | /* ASIC */ |
2233 | /* ASIC */ |
2231 | union radeon_asic_config config; |
2234 | union radeon_asic_config config; |
2232 | enum radeon_family family; |
2235 | enum radeon_family family; |
2233 | unsigned long flags; |
2236 | unsigned long flags; |
2234 | int usec_timeout; |
2237 | int usec_timeout; |
2235 | enum radeon_pll_errata pll_errata; |
2238 | enum radeon_pll_errata pll_errata; |
2236 | int num_gb_pipes; |
2239 | int num_gb_pipes; |
2237 | int num_z_pipes; |
2240 | int num_z_pipes; |
2238 | int disp_priority; |
2241 | int disp_priority; |
2239 | /* BIOS */ |
2242 | /* BIOS */ |
2240 | uint8_t *bios; |
2243 | uint8_t *bios; |
2241 | bool is_atom_bios; |
2244 | bool is_atom_bios; |
2242 | uint16_t bios_header_start; |
2245 | uint16_t bios_header_start; |
2243 | struct radeon_bo *stollen_vga_memory; |
2246 | struct radeon_bo *stollen_vga_memory; |
2244 | /* Register mmio */ |
2247 | /* Register mmio */ |
2245 | resource_size_t rmmio_base; |
2248 | resource_size_t rmmio_base; |
2246 | resource_size_t rmmio_size; |
2249 | resource_size_t rmmio_size; |
2247 | /* protects concurrent MM_INDEX/DATA based register access */ |
2250 | /* protects concurrent MM_INDEX/DATA based register access */ |
2248 | spinlock_t mmio_idx_lock; |
2251 | spinlock_t mmio_idx_lock; |
2249 | /* protects concurrent SMC based register access */ |
2252 | /* protects concurrent SMC based register access */ |
2250 | spinlock_t smc_idx_lock; |
2253 | spinlock_t smc_idx_lock; |
2251 | /* protects concurrent PLL register access */ |
2254 | /* protects concurrent PLL register access */ |
2252 | spinlock_t pll_idx_lock; |
2255 | spinlock_t pll_idx_lock; |
2253 | /* protects concurrent MC register access */ |
2256 | /* protects concurrent MC register access */ |
2254 | spinlock_t mc_idx_lock; |
2257 | spinlock_t mc_idx_lock; |
2255 | /* protects concurrent PCIE register access */ |
2258 | /* protects concurrent PCIE register access */ |
2256 | spinlock_t pcie_idx_lock; |
2259 | spinlock_t pcie_idx_lock; |
2257 | /* protects concurrent PCIE_PORT register access */ |
2260 | /* protects concurrent PCIE_PORT register access */ |
2258 | spinlock_t pciep_idx_lock; |
2261 | spinlock_t pciep_idx_lock; |
2259 | /* protects concurrent PIF register access */ |
2262 | /* protects concurrent PIF register access */ |
2260 | spinlock_t pif_idx_lock; |
2263 | spinlock_t pif_idx_lock; |
2261 | /* protects concurrent CG register access */ |
2264 | /* protects concurrent CG register access */ |
2262 | spinlock_t cg_idx_lock; |
2265 | spinlock_t cg_idx_lock; |
2263 | /* protects concurrent UVD register access */ |
2266 | /* protects concurrent UVD register access */ |
2264 | spinlock_t uvd_idx_lock; |
2267 | spinlock_t uvd_idx_lock; |
2265 | /* protects concurrent RCU register access */ |
2268 | /* protects concurrent RCU register access */ |
2266 | spinlock_t rcu_idx_lock; |
2269 | spinlock_t rcu_idx_lock; |
2267 | /* protects concurrent DIDT register access */ |
2270 | /* protects concurrent DIDT register access */ |
2268 | spinlock_t didt_idx_lock; |
2271 | spinlock_t didt_idx_lock; |
2269 | /* protects concurrent ENDPOINT (audio) register access */ |
2272 | /* protects concurrent ENDPOINT (audio) register access */ |
2270 | spinlock_t end_idx_lock; |
2273 | spinlock_t end_idx_lock; |
2271 | void __iomem *rmmio; |
2274 | void __iomem *rmmio; |
2272 | radeon_rreg_t mc_rreg; |
2275 | radeon_rreg_t mc_rreg; |
2273 | radeon_wreg_t mc_wreg; |
2276 | radeon_wreg_t mc_wreg; |
2274 | radeon_rreg_t pll_rreg; |
2277 | radeon_rreg_t pll_rreg; |
2275 | radeon_wreg_t pll_wreg; |
2278 | radeon_wreg_t pll_wreg; |
2276 | uint32_t pcie_reg_mask; |
2279 | uint32_t pcie_reg_mask; |
2277 | radeon_rreg_t pciep_rreg; |
2280 | radeon_rreg_t pciep_rreg; |
2278 | radeon_wreg_t pciep_wreg; |
2281 | radeon_wreg_t pciep_wreg; |
2279 | /* io port */ |
2282 | /* io port */ |
2280 | void __iomem *rio_mem; |
2283 | void __iomem *rio_mem; |
2281 | resource_size_t rio_mem_size; |
2284 | resource_size_t rio_mem_size; |
2282 | struct radeon_clock clock; |
2285 | struct radeon_clock clock; |
2283 | struct radeon_mc mc; |
2286 | struct radeon_mc mc; |
2284 | struct radeon_gart gart; |
2287 | struct radeon_gart gart; |
2285 | struct radeon_mode_info mode_info; |
2288 | struct radeon_mode_info mode_info; |
2286 | struct radeon_scratch scratch; |
2289 | struct radeon_scratch scratch; |
2287 | struct radeon_doorbell doorbell; |
2290 | struct radeon_doorbell doorbell; |
2288 | struct radeon_mman mman; |
2291 | struct radeon_mman mman; |
2289 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
2292 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
2290 | wait_queue_head_t fence_queue; |
2293 | wait_queue_head_t fence_queue; |
2291 | struct mutex ring_lock; |
2294 | struct mutex ring_lock; |
2292 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
2295 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
2293 | bool ib_pool_ready; |
2296 | bool ib_pool_ready; |
2294 | struct radeon_sa_manager ring_tmp_bo; |
2297 | struct radeon_sa_manager ring_tmp_bo; |
2295 | struct radeon_irq irq; |
2298 | struct radeon_irq irq; |
2296 | struct radeon_asic *asic; |
2299 | struct radeon_asic *asic; |
2297 | struct radeon_gem gem; |
2300 | struct radeon_gem gem; |
2298 | struct radeon_pm pm; |
2301 | struct radeon_pm pm; |
2299 | struct radeon_uvd uvd; |
2302 | struct radeon_uvd uvd; |
2300 | struct radeon_vce vce; |
2303 | struct radeon_vce vce; |
2301 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
2304 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
2302 | struct radeon_wb wb; |
2305 | struct radeon_wb wb; |
2303 | struct radeon_dummy_page dummy_page; |
2306 | struct radeon_dummy_page dummy_page; |
2304 | bool shutdown; |
2307 | bool shutdown; |
2305 | bool suspend; |
2308 | bool suspend; |
2306 | bool need_dma32; |
2309 | bool need_dma32; |
2307 | bool accel_working; |
2310 | bool accel_working; |
2308 | bool fastfb_working; /* IGP feature*/ |
2311 | bool fastfb_working; /* IGP feature*/ |
2309 | bool needs_reset; |
2312 | bool needs_reset; |
2310 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
2313 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
2311 | const struct firmware *me_fw; /* all family ME firmware */ |
2314 | const struct firmware *me_fw; /* all family ME firmware */ |
2312 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
2315 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
2313 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
2316 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
2314 | const struct firmware *mc_fw; /* NI MC firmware */ |
2317 | const struct firmware *mc_fw; /* NI MC firmware */ |
2315 | const struct firmware *ce_fw; /* SI CE firmware */ |
2318 | const struct firmware *ce_fw; /* SI CE firmware */ |
2316 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
2319 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
2317 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
2320 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
2318 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
2321 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
2319 | const struct firmware *smc_fw; /* SMC firmware */ |
2322 | const struct firmware *smc_fw; /* SMC firmware */ |
2320 | const struct firmware *uvd_fw; /* UVD firmware */ |
2323 | const struct firmware *uvd_fw; /* UVD firmware */ |
2321 | const struct firmware *vce_fw; /* VCE firmware */ |
2324 | const struct firmware *vce_fw; /* VCE firmware */ |
2322 | bool new_fw; |
2325 | bool new_fw; |
2323 | struct r600_vram_scratch vram_scratch; |
2326 | struct r600_vram_scratch vram_scratch; |
2324 | int msi_enabled; /* msi enabled */ |
2327 | int msi_enabled; /* msi enabled */ |
2325 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2328 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2326 | struct radeon_rlc rlc; |
2329 | struct radeon_rlc rlc; |
2327 | struct radeon_mec mec; |
2330 | struct radeon_mec mec; |
2328 | struct work_struct hotplug_work; |
2331 | struct work_struct hotplug_work; |
2329 | struct work_struct audio_work; |
2332 | struct work_struct audio_work; |
2330 | struct work_struct reset_work; |
2333 | struct work_struct reset_work; |
2331 | int num_crtc; /* number of crtcs */ |
2334 | int num_crtc; /* number of crtcs */ |
2332 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
2335 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
2333 | bool has_uvd; |
2336 | bool has_uvd; |
2334 | struct r600_audio audio; /* audio stuff */ |
2337 | struct r600_audio audio; /* audio stuff */ |
2335 | /* only one userspace can use Hyperz features or CMASK at a time */ |
2338 | /* only one userspace can use Hyperz features or CMASK at a time */ |
2336 | struct drm_file *hyperz_filp; |
2339 | struct drm_file *hyperz_filp; |
2337 | struct drm_file *cmask_filp; |
2340 | struct drm_file *cmask_filp; |
2338 | /* i2c buses */ |
2341 | /* i2c buses */ |
2339 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
2342 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
2340 | /* debugfs */ |
2343 | /* debugfs */ |
2341 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
2344 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
2342 | unsigned debugfs_count; |
2345 | unsigned debugfs_count; |
2343 | /* virtual memory */ |
2346 | /* virtual memory */ |
2344 | struct radeon_vm_manager vm_manager; |
2347 | struct radeon_vm_manager vm_manager; |
2345 | struct mutex gpu_clock_mutex; |
2348 | struct mutex gpu_clock_mutex; |
2346 | /* memory stats */ |
2349 | /* memory stats */ |
2347 | atomic64_t vram_usage; |
2350 | atomic64_t vram_usage; |
2348 | atomic64_t gtt_usage; |
2351 | atomic64_t gtt_usage; |
2349 | atomic64_t num_bytes_moved; |
2352 | atomic64_t num_bytes_moved; |
2350 | /* ACPI interface */ |
2353 | /* ACPI interface */ |
2351 | struct radeon_atif atif; |
2354 | struct radeon_atif atif; |
2352 | struct radeon_atcs atcs; |
2355 | struct radeon_atcs atcs; |
2353 | /* srbm instance registers */ |
2356 | /* srbm instance registers */ |
2354 | struct mutex srbm_mutex; |
2357 | struct mutex srbm_mutex; |
2355 | /* clock, powergating flags */ |
2358 | /* clock, powergating flags */ |
2356 | u32 cg_flags; |
2359 | u32 cg_flags; |
2357 | u32 pg_flags; |
2360 | u32 pg_flags; |
2358 | 2361 | ||
2359 | // struct dev_pm_domain vga_pm_domain; |
2362 | // struct dev_pm_domain vga_pm_domain; |
2360 | bool have_disp_power_ref; |
2363 | bool have_disp_power_ref; |
2361 | u32 px_quirk_flags; |
2364 | u32 px_quirk_flags; |
2362 | 2365 | ||
2363 | /* tracking pinned memory */ |
2366 | /* tracking pinned memory */ |
2364 | u64 vram_pin_size; |
2367 | u64 vram_pin_size; |
2365 | u64 gart_pin_size; |
2368 | u64 gart_pin_size; |
2366 | }; |
2369 | }; |
2367 | 2370 | ||
2368 | bool radeon_is_px(struct drm_device *dev); |
2371 | bool radeon_is_px(struct drm_device *dev); |
2369 | int radeon_device_init(struct radeon_device *rdev, |
2372 | int radeon_device_init(struct radeon_device *rdev, |
2370 | struct drm_device *ddev, |
2373 | struct drm_device *ddev, |
2371 | struct pci_dev *pdev, |
2374 | struct pci_dev *pdev, |
2372 | uint32_t flags); |
2375 | uint32_t flags); |
2373 | void radeon_device_fini(struct radeon_device *rdev); |
2376 | void radeon_device_fini(struct radeon_device *rdev); |
2374 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
2377 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
2375 | 2378 | ||
2376 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2379 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2377 | 2380 | ||
2378 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2381 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2379 | bool always_indirect) |
2382 | bool always_indirect) |
2380 | { |
2383 | { |
2381 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
2384 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
2382 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2385 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2383 | return readl(((void __iomem *)rdev->rmmio) + reg); |
2386 | return readl(((void __iomem *)rdev->rmmio) + reg); |
2384 | else { |
2387 | else { |
2385 | unsigned long flags; |
2388 | unsigned long flags; |
2386 | uint32_t ret; |
2389 | uint32_t ret; |
2387 | 2390 | ||
2388 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
2391 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
2389 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2392 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2390 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
2393 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
2391 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
2394 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
2392 | 2395 | ||
2393 | return ret; |
2396 | return ret; |
2394 | } |
2397 | } |
2395 | } |
2398 | } |
2396 | 2399 | ||
2397 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
2400 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
2398 | bool always_indirect) |
2401 | bool always_indirect) |
2399 | { |
2402 | { |
2400 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2403 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2401 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
2404 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
2402 | else { |
2405 | else { |
2403 | unsigned long flags; |
2406 | unsigned long flags; |
2404 | 2407 | ||
2405 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
2408 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
2406 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2409 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
2407 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
2410 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
2408 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
2411 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
2409 | } |
2412 | } |
2410 | } |
2413 | } |
2411 | 2414 | ||
2412 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2415 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2413 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2416 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2414 | 2417 | ||
2415 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2418 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2416 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
2419 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
2417 | 2420 | ||
2418 | /* |
2421 | /* |
2419 | * Cast helper |
2422 | * Cast helper |
2420 | */ |
2423 | */ |
2421 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
2424 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
2422 | 2425 | ||
2423 | /* |
2426 | /* |
2424 | * Registers read & write functions. |
2427 | * Registers read & write functions. |
2425 | */ |
2428 | */ |
2426 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2429 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2427 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
2430 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
2428 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
2431 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
2429 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
2432 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
2430 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2433 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2431 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
2434 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
2432 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
2435 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
2433 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
2436 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
2434 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
2437 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
2435 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2438 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2436 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2439 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2437 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
2440 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
2438 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
2441 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
2439 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
2442 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
2440 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
2443 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
2441 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2444 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2442 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
2445 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
2443 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2446 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2444 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
2447 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
2445 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2448 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2446 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
2449 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
2447 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2450 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2448 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
2451 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
2449 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2452 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2450 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
2453 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
2451 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2454 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2452 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
2455 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
2453 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
2456 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
2454 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
2457 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
2455 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2458 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2456 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
2459 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
2457 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2460 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2458 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
2461 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
2459 | #define WREG32_P(reg, val, mask) \ |
2462 | #define WREG32_P(reg, val, mask) \ |
2460 | do { \ |
2463 | do { \ |
2461 | uint32_t tmp_ = RREG32(reg); \ |
2464 | uint32_t tmp_ = RREG32(reg); \ |
2462 | tmp_ &= (mask); \ |
2465 | tmp_ &= (mask); \ |
2463 | tmp_ |= ((val) & ~(mask)); \ |
2466 | tmp_ |= ((val) & ~(mask)); \ |
2464 | WREG32(reg, tmp_); \ |
2467 | WREG32(reg, tmp_); \ |
2465 | } while (0) |
2468 | } while (0) |
2466 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2469 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2467 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2470 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2468 | #define WREG32_PLL_P(reg, val, mask) \ |
2471 | #define WREG32_PLL_P(reg, val, mask) \ |
2469 | do { \ |
2472 | do { \ |
2470 | uint32_t tmp_ = RREG32_PLL(reg); \ |
2473 | uint32_t tmp_ = RREG32_PLL(reg); \ |
2471 | tmp_ &= (mask); \ |
2474 | tmp_ &= (mask); \ |
2472 | tmp_ |= ((val) & ~(mask)); \ |
2475 | tmp_ |= ((val) & ~(mask)); \ |
2473 | WREG32_PLL(reg, tmp_); \ |
2476 | WREG32_PLL(reg, tmp_); \ |
2474 | } while (0) |
2477 | } while (0) |
2475 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
2478 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
2476 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2479 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2477 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
2480 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
2478 | 2481 | ||
2479 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2482 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2480 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
2483 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
2481 | 2484 | ||
2482 | /* |
2485 | /* |
2483 | * Indirect registers accessor |
2486 | * Indirect registers accessor |
2484 | */ |
2487 | */ |
2485 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
2488 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
2486 | { |
2489 | { |
2487 | unsigned long flags; |
2490 | unsigned long flags; |
2488 | uint32_t r; |
2491 | uint32_t r; |
2489 | 2492 | ||
2490 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
2493 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
2491 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2494 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2492 | r = RREG32(RADEON_PCIE_DATA); |
2495 | r = RREG32(RADEON_PCIE_DATA); |
2493 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
2496 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
2494 | return r; |
2497 | return r; |
2495 | } |
2498 | } |
2496 | 2499 | ||
2497 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2500 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
2498 | { |
2501 | { |
2499 | unsigned long flags; |
2502 | unsigned long flags; |
2500 | 2503 | ||
2501 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
2504 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
2502 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2505 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2503 | WREG32(RADEON_PCIE_DATA, (v)); |
2506 | WREG32(RADEON_PCIE_DATA, (v)); |
2504 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
2507 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
2505 | } |
2508 | } |
2506 | 2509 | ||
2507 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
2510 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
2508 | { |
2511 | { |
2509 | unsigned long flags; |
2512 | unsigned long flags; |
2510 | u32 r; |
2513 | u32 r; |
2511 | 2514 | ||
2512 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
2515 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
2513 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2516 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2514 | r = RREG32(TN_SMC_IND_DATA_0); |
2517 | r = RREG32(TN_SMC_IND_DATA_0); |
2515 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
2518 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
2516 | return r; |
2519 | return r; |
2517 | } |
2520 | } |
2518 | 2521 | ||
2519 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2522 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2520 | { |
2523 | { |
2521 | unsigned long flags; |
2524 | unsigned long flags; |
2522 | 2525 | ||
2523 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
2526 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
2524 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2527 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2525 | WREG32(TN_SMC_IND_DATA_0, (v)); |
2528 | WREG32(TN_SMC_IND_DATA_0, (v)); |
2526 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
2529 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
2527 | } |
2530 | } |
2528 | 2531 | ||
2529 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
2532 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
2530 | { |
2533 | { |
2531 | unsigned long flags; |
2534 | unsigned long flags; |
2532 | u32 r; |
2535 | u32 r; |
2533 | 2536 | ||
2534 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
2537 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
2535 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2538 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2536 | r = RREG32(R600_RCU_DATA); |
2539 | r = RREG32(R600_RCU_DATA); |
2537 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
2540 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
2538 | return r; |
2541 | return r; |
2539 | } |
2542 | } |
2540 | 2543 | ||
2541 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2544 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2542 | { |
2545 | { |
2543 | unsigned long flags; |
2546 | unsigned long flags; |
2544 | 2547 | ||
2545 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
2548 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
2546 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2549 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2547 | WREG32(R600_RCU_DATA, (v)); |
2550 | WREG32(R600_RCU_DATA, (v)); |
2548 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
2551 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
2549 | } |
2552 | } |
2550 | 2553 | ||
2551 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
2554 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
2552 | { |
2555 | { |
2553 | unsigned long flags; |
2556 | unsigned long flags; |
2554 | u32 r; |
2557 | u32 r; |
2555 | 2558 | ||
2556 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
2559 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
2557 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2560 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2558 | r = RREG32(EVERGREEN_CG_IND_DATA); |
2561 | r = RREG32(EVERGREEN_CG_IND_DATA); |
2559 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
2562 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
2560 | return r; |
2563 | return r; |
2561 | } |
2564 | } |
2562 | 2565 | ||
2563 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2566 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2564 | { |
2567 | { |
2565 | unsigned long flags; |
2568 | unsigned long flags; |
2566 | 2569 | ||
2567 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
2570 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
2568 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2571 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2569 | WREG32(EVERGREEN_CG_IND_DATA, (v)); |
2572 | WREG32(EVERGREEN_CG_IND_DATA, (v)); |
2570 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
2573 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
2571 | } |
2574 | } |
2572 | 2575 | ||
2573 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
2576 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
2574 | { |
2577 | { |
2575 | unsigned long flags; |
2578 | unsigned long flags; |
2576 | u32 r; |
2579 | u32 r; |
2577 | 2580 | ||
2578 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2581 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2579 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2582 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2580 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); |
2583 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); |
2581 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2584 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2582 | return r; |
2585 | return r; |
2583 | } |
2586 | } |
2584 | 2587 | ||
2585 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2588 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2586 | { |
2589 | { |
2587 | unsigned long flags; |
2590 | unsigned long flags; |
2588 | 2591 | ||
2589 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2592 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2590 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2593 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2591 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); |
2594 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); |
2592 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2595 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2593 | } |
2596 | } |
2594 | 2597 | ||
2595 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) |
2598 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) |
2596 | { |
2599 | { |
2597 | unsigned long flags; |
2600 | unsigned long flags; |
2598 | u32 r; |
2601 | u32 r; |
2599 | 2602 | ||
2600 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2603 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2601 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2604 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2602 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); |
2605 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); |
2603 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2606 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2604 | return r; |
2607 | return r; |
2605 | } |
2608 | } |
2606 | 2609 | ||
2607 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2610 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2608 | { |
2611 | { |
2609 | unsigned long flags; |
2612 | unsigned long flags; |
2610 | 2613 | ||
2611 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2614 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
2612 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2615 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2613 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); |
2616 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); |
2614 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2617 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
2615 | } |
2618 | } |
2616 | 2619 | ||
2617 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
2620 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
2618 | { |
2621 | { |
2619 | unsigned long flags; |
2622 | unsigned long flags; |
2620 | u32 r; |
2623 | u32 r; |
2621 | 2624 | ||
2622 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
2625 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
2623 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2626 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2624 | r = RREG32(R600_UVD_CTX_DATA); |
2627 | r = RREG32(R600_UVD_CTX_DATA); |
2625 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
2628 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
2626 | return r; |
2629 | return r; |
2627 | } |
2630 | } |
2628 | 2631 | ||
2629 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2632 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2630 | { |
2633 | { |
2631 | unsigned long flags; |
2634 | unsigned long flags; |
2632 | 2635 | ||
2633 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
2636 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
2634 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2637 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2635 | WREG32(R600_UVD_CTX_DATA, (v)); |
2638 | WREG32(R600_UVD_CTX_DATA, (v)); |
2636 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
2639 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
2637 | } |
2640 | } |
2638 | 2641 | ||
2639 | 2642 | ||
2640 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
2643 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
2641 | { |
2644 | { |
2642 | unsigned long flags; |
2645 | unsigned long flags; |
2643 | u32 r; |
2646 | u32 r; |
2644 | 2647 | ||
2645 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
2648 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
2646 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2649 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2647 | r = RREG32(CIK_DIDT_IND_DATA); |
2650 | r = RREG32(CIK_DIDT_IND_DATA); |
2648 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
2651 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
2649 | return r; |
2652 | return r; |
2650 | } |
2653 | } |
2651 | 2654 | ||
2652 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2655 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
2653 | { |
2656 | { |
2654 | unsigned long flags; |
2657 | unsigned long flags; |
2655 | 2658 | ||
2656 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
2659 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
2657 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2660 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2658 | WREG32(CIK_DIDT_IND_DATA, (v)); |
2661 | WREG32(CIK_DIDT_IND_DATA, (v)); |
2659 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
2662 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
2660 | } |
2663 | } |
2661 | 2664 | ||
2662 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2665 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2663 | 2666 | ||
2664 | 2667 | ||
2665 | /* |
2668 | /* |
2666 | * ASICs helpers. |
2669 | * ASICs helpers. |
2667 | */ |
2670 | */ |
2668 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2671 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2669 | (rdev->pdev->device == 0x5969)) |
2672 | (rdev->pdev->device == 0x5969)) |
2670 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2673 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2671 | (rdev->family == CHIP_RV200) || \ |
2674 | (rdev->family == CHIP_RV200) || \ |
2672 | (rdev->family == CHIP_RS100) || \ |
2675 | (rdev->family == CHIP_RS100) || \ |
2673 | (rdev->family == CHIP_RS200) || \ |
2676 | (rdev->family == CHIP_RS200) || \ |
2674 | (rdev->family == CHIP_RV250) || \ |
2677 | (rdev->family == CHIP_RV250) || \ |
2675 | (rdev->family == CHIP_RV280) || \ |
2678 | (rdev->family == CHIP_RV280) || \ |
2676 | (rdev->family == CHIP_RS300)) |
2679 | (rdev->family == CHIP_RS300)) |
2677 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
2680 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
2678 | (rdev->family == CHIP_RV350) || \ |
2681 | (rdev->family == CHIP_RV350) || \ |
2679 | (rdev->family == CHIP_R350) || \ |
2682 | (rdev->family == CHIP_R350) || \ |
2680 | (rdev->family == CHIP_RV380) || \ |
2683 | (rdev->family == CHIP_RV380) || \ |
2681 | (rdev->family == CHIP_R420) || \ |
2684 | (rdev->family == CHIP_R420) || \ |
2682 | (rdev->family == CHIP_R423) || \ |
2685 | (rdev->family == CHIP_R423) || \ |
2683 | (rdev->family == CHIP_RV410) || \ |
2686 | (rdev->family == CHIP_RV410) || \ |
2684 | (rdev->family == CHIP_RS400) || \ |
2687 | (rdev->family == CHIP_RS400) || \ |
2685 | (rdev->family == CHIP_RS480)) |
2688 | (rdev->family == CHIP_RS480)) |
2686 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2689 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2687 | (rdev->ddev->pdev->device == 0x9443) || \ |
2690 | (rdev->ddev->pdev->device == 0x9443) || \ |
2688 | (rdev->ddev->pdev->device == 0x944B) || \ |
2691 | (rdev->ddev->pdev->device == 0x944B) || \ |
2689 | (rdev->ddev->pdev->device == 0x9506) || \ |
2692 | (rdev->ddev->pdev->device == 0x9506) || \ |
2690 | (rdev->ddev->pdev->device == 0x9509) || \ |
2693 | (rdev->ddev->pdev->device == 0x9509) || \ |
2691 | (rdev->ddev->pdev->device == 0x950F) || \ |
2694 | (rdev->ddev->pdev->device == 0x950F) || \ |
2692 | (rdev->ddev->pdev->device == 0x689C) || \ |
2695 | (rdev->ddev->pdev->device == 0x689C) || \ |
2693 | (rdev->ddev->pdev->device == 0x689D)) |
2696 | (rdev->ddev->pdev->device == 0x689D)) |
2694 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
2697 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
2695 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2698 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2696 | (rdev->family == CHIP_RS690) || \ |
2699 | (rdev->family == CHIP_RS690) || \ |
2697 | (rdev->family == CHIP_RS740) || \ |
2700 | (rdev->family == CHIP_RS740) || \ |
2698 | (rdev->family >= CHIP_R600)) |
2701 | (rdev->family >= CHIP_R600)) |
2699 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2702 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2700 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
2703 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
2701 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2704 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2702 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2705 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2703 | (rdev->flags & RADEON_IS_IGP)) |
2706 | (rdev->flags & RADEON_IS_IGP)) |
2704 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
2707 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
2705 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2708 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2706 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
2709 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
2707 | (rdev->flags & RADEON_IS_IGP)) |
2710 | (rdev->flags & RADEON_IS_IGP)) |
2708 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
2711 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
2709 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
2712 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
2710 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
2713 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
2711 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2714 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2712 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
2715 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
2713 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2716 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2714 | (rdev->family == CHIP_MULLINS)) |
2717 | (rdev->family == CHIP_MULLINS)) |
2715 | 2718 | ||
2716 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2719 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2717 | (rdev->ddev->pdev->device == 0x6850) || \ |
2720 | (rdev->ddev->pdev->device == 0x6850) || \ |
2718 | (rdev->ddev->pdev->device == 0x6858) || \ |
2721 | (rdev->ddev->pdev->device == 0x6858) || \ |
2719 | (rdev->ddev->pdev->device == 0x6859) || \ |
2722 | (rdev->ddev->pdev->device == 0x6859) || \ |
2720 | (rdev->ddev->pdev->device == 0x6840) || \ |
2723 | (rdev->ddev->pdev->device == 0x6840) || \ |
2721 | (rdev->ddev->pdev->device == 0x6841) || \ |
2724 | (rdev->ddev->pdev->device == 0x6841) || \ |
2722 | (rdev->ddev->pdev->device == 0x6842) || \ |
2725 | (rdev->ddev->pdev->device == 0x6842) || \ |
2723 | (rdev->ddev->pdev->device == 0x6843)) |
2726 | (rdev->ddev->pdev->device == 0x6843)) |
2724 | 2727 | ||
2725 | /* |
2728 | /* |
2726 | * BIOS helpers. |
2729 | * BIOS helpers. |
2727 | */ |
2730 | */ |
2728 | #define RBIOS8(i) (rdev->bios[i]) |
2731 | #define RBIOS8(i) (rdev->bios[i]) |
2729 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
2732 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
2730 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
2733 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
2731 | 2734 | ||
2732 | int radeon_combios_init(struct radeon_device *rdev); |
2735 | int radeon_combios_init(struct radeon_device *rdev); |
2733 | void radeon_combios_fini(struct radeon_device *rdev); |
2736 | void radeon_combios_fini(struct radeon_device *rdev); |
2734 | int radeon_atombios_init(struct radeon_device *rdev); |
2737 | int radeon_atombios_init(struct radeon_device *rdev); |
2735 | void radeon_atombios_fini(struct radeon_device *rdev); |
2738 | void radeon_atombios_fini(struct radeon_device *rdev); |
2736 | 2739 | ||
2737 | 2740 | ||
2738 | /* |
2741 | /* |
2739 | * RING helpers. |
2742 | * RING helpers. |
2740 | */ |
2743 | */ |
2741 | #if DRM_DEBUG_CODE == 0 |
2744 | #if DRM_DEBUG_CODE == 0 |
2742 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
2745 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
2743 | { |
2746 | { |
2744 | ring->ring[ring->wptr++] = v; |
2747 | ring->ring[ring->wptr++] = v; |
2745 | ring->wptr &= ring->ptr_mask; |
2748 | ring->wptr &= ring->ptr_mask; |
2746 | ring->count_dw--; |
2749 | ring->count_dw--; |
2747 | ring->ring_free_dw--; |
2750 | ring->ring_free_dw--; |
2748 | } |
2751 | } |
2749 | #else |
2752 | #else |
2750 | /* With debugging this is just too big to inline */ |
2753 | /* With debugging this is just too big to inline */ |
2751 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
2754 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
2752 | #endif |
2755 | #endif |
2753 | 2756 | ||
2754 | /* |
2757 | /* |
2755 | * ASICs macro. |
2758 | * ASICs macro. |
2756 | */ |
2759 | */ |
2757 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
2760 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
2758 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2761 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2759 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
2762 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
2760 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
2763 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
2761 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
2764 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
2762 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
2765 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
2763 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2766 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2764 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2767 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2765 | #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) |
2768 | #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) |
2766 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2769 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2767 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
2770 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
2768 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2771 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2769 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2772 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2770 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2773 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2771 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) |
2774 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) |
2772 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2775 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2773 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
2776 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
2774 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
2777 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
2775 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
2778 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
2776 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
2779 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
2777 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
2780 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
2778 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) |
2781 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) |
2779 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2782 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2780 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
2783 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
2781 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
2784 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
2782 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2785 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2783 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
2786 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
2784 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
2787 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
2785 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
2788 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
2786 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
2789 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
2787 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2790 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2788 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
2791 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
2789 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2792 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2790 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
2793 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
2791 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
2794 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
2792 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
2795 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
2793 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
2796 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
2794 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2797 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2795 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
2798 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
2796 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
2799 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
2797 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2800 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2798 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
2801 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
2799 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
2802 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
2800 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
2803 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
2801 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
2804 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
2802 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
2805 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
2803 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
2806 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
2804 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2807 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2805 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
2808 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
2806 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
2809 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
2807 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2810 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2808 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
2811 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
2809 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
2812 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
2810 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2813 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2811 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
2814 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
2812 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
2815 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
2813 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
2816 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
2814 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2817 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2815 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2818 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2816 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
2819 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
2817 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
2820 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
2818 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
2821 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
2819 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
2822 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
2820 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
2823 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
2821 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
2824 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
2822 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2825 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2823 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
2826 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
2824 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
2827 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
2825 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
2828 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
2826 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2829 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2827 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
2830 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
2828 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
2831 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
2829 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
2832 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
2830 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
2833 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
2831 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
2834 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
2832 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
2835 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
2833 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
2836 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
2834 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2837 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2835 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
2838 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
2836 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
2839 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
2837 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
2840 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
2838 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
2841 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
2839 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
2842 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
2840 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
2843 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
2841 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
2844 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
2842 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
2845 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
2843 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
2846 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
2844 | 2847 | ||
2845 | /* Common functions */ |
2848 | /* Common functions */ |
2846 | /* AGP */ |
2849 | /* AGP */ |
2847 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
2850 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
2848 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
2851 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
2849 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
2852 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
2850 | extern void radeon_agp_disable(struct radeon_device *rdev); |
2853 | extern void radeon_agp_disable(struct radeon_device *rdev); |
2851 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2854 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2852 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
2855 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
2853 | extern bool radeon_card_posted(struct radeon_device *rdev); |
2856 | extern bool radeon_card_posted(struct radeon_device *rdev); |
2854 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
2857 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
2855 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
2858 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
2856 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
2859 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
2857 | extern void radeon_scratch_init(struct radeon_device *rdev); |
2860 | extern void radeon_scratch_init(struct radeon_device *rdev); |
2858 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2861 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2859 | extern int radeon_wb_init(struct radeon_device *rdev); |
2862 | extern int radeon_wb_init(struct radeon_device *rdev); |
2860 | extern void radeon_wb_disable(struct radeon_device *rdev); |
2863 | extern void radeon_wb_disable(struct radeon_device *rdev); |
2861 | extern void radeon_surface_init(struct radeon_device *rdev); |
2864 | extern void radeon_surface_init(struct radeon_device *rdev); |
2862 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
2865 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
2863 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
2866 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
2864 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
2867 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
2865 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
2868 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
2866 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
2869 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
2867 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2870 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2868 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
2871 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
2869 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2872 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2870 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
2873 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
2871 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2874 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2872 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2875 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2873 | const u32 *registers, |
2876 | const u32 *registers, |
2874 | const u32 array_size); |
2877 | const u32 array_size); |
2875 | 2878 | ||
2876 | /* |
2879 | /* |
2877 | * vm |
2880 | * vm |
2878 | */ |
2881 | */ |
2879 | int radeon_vm_manager_init(struct radeon_device *rdev); |
2882 | int radeon_vm_manager_init(struct radeon_device *rdev); |
2880 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2883 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2881 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2884 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2882 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2885 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2883 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
2886 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
2884 | struct radeon_vm *vm, |
2887 | struct radeon_vm *vm, |
2885 | struct list_head *head); |
2888 | struct list_head *head); |
2886 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2889 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2887 | struct radeon_vm *vm, int ring); |
2890 | struct radeon_vm *vm, int ring); |
2888 | void radeon_vm_flush(struct radeon_device *rdev, |
2891 | void radeon_vm_flush(struct radeon_device *rdev, |
2889 | struct radeon_vm *vm, |
2892 | struct radeon_vm *vm, |
2890 | int ring); |
2893 | int ring); |
2891 | void radeon_vm_fence(struct radeon_device *rdev, |
2894 | void radeon_vm_fence(struct radeon_device *rdev, |
2892 | struct radeon_vm *vm, |
2895 | struct radeon_vm *vm, |
2893 | struct radeon_fence *fence); |
2896 | struct radeon_fence *fence); |
2894 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
2897 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
2895 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2898 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2896 | struct radeon_vm *vm); |
2899 | struct radeon_vm *vm); |
2897 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2900 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2898 | struct radeon_vm *vm); |
2901 | struct radeon_vm *vm); |
2899 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2902 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2900 | struct radeon_vm *vm); |
2903 | struct radeon_vm *vm); |
2901 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2904 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2902 | struct radeon_bo_va *bo_va, |
2905 | struct radeon_bo_va *bo_va, |
2903 | struct ttm_mem_reg *mem); |
2906 | struct ttm_mem_reg *mem); |
2904 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2907 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2905 | struct radeon_bo *bo); |
2908 | struct radeon_bo *bo); |
2906 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2909 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2907 | struct radeon_bo *bo); |
2910 | struct radeon_bo *bo); |
2908 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2911 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2909 | struct radeon_vm *vm, |
2912 | struct radeon_vm *vm, |
2910 | struct radeon_bo *bo); |
2913 | struct radeon_bo *bo); |
2911 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
2914 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
2912 | struct radeon_bo_va *bo_va, |
2915 | struct radeon_bo_va *bo_va, |
2913 | uint64_t offset, |
2916 | uint64_t offset, |
2914 | uint32_t flags); |
2917 | uint32_t flags); |
2915 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
2918 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
2916 | struct radeon_bo_va *bo_va); |
2919 | struct radeon_bo_va *bo_va); |
2917 | 2920 | ||
2918 | /* audio */ |
2921 | /* audio */ |
2919 | void r600_audio_update_hdmi(struct work_struct *work); |
2922 | void r600_audio_update_hdmi(struct work_struct *work); |
2920 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2923 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2921 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2924 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2922 | void r600_audio_enable(struct radeon_device *rdev, |
2925 | void r600_audio_enable(struct radeon_device *rdev, |
2923 | struct r600_audio_pin *pin, |
2926 | struct r600_audio_pin *pin, |
2924 | bool enable); |
2927 | bool enable); |
2925 | void dce6_audio_enable(struct radeon_device *rdev, |
2928 | void dce6_audio_enable(struct radeon_device *rdev, |
2926 | struct r600_audio_pin *pin, |
2929 | struct r600_audio_pin *pin, |
2927 | bool enable); |
2930 | bool enable); |
2928 | 2931 | ||
2929 | /* |
2932 | /* |
2930 | * R600 vram scratch functions |
2933 | * R600 vram scratch functions |
2931 | */ |
2934 | */ |
2932 | int r600_vram_scratch_init(struct radeon_device *rdev); |
2935 | int r600_vram_scratch_init(struct radeon_device *rdev); |
2933 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
2936 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
2934 | 2937 | ||
2935 | /* |
2938 | /* |
2936 | * r600 cs checking helper |
2939 | * r600 cs checking helper |
2937 | */ |
2940 | */ |
2938 | unsigned r600_mip_minify(unsigned size, unsigned level); |
2941 | unsigned r600_mip_minify(unsigned size, unsigned level); |
2939 | bool r600_fmt_is_valid_color(u32 format); |
2942 | bool r600_fmt_is_valid_color(u32 format); |
2940 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
2943 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
2941 | int r600_fmt_get_blocksize(u32 format); |
2944 | int r600_fmt_get_blocksize(u32 format); |
2942 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
2945 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
2943 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
2946 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
2944 | 2947 | ||
2945 | /* |
2948 | /* |
2946 | * r600 functions used by radeon_encoder.c |
2949 | * r600 functions used by radeon_encoder.c |
2947 | */ |
2950 | */ |
2948 | struct radeon_hdmi_acr { |
2951 | struct radeon_hdmi_acr { |
2949 | u32 clock; |
2952 | u32 clock; |
2950 | 2953 | ||
2951 | int n_32khz; |
2954 | int n_32khz; |
2952 | int cts_32khz; |
2955 | int cts_32khz; |
2953 | 2956 | ||
2954 | int n_44_1khz; |
2957 | int n_44_1khz; |
2955 | int cts_44_1khz; |
2958 | int cts_44_1khz; |
2956 | 2959 | ||
2957 | int n_48khz; |
2960 | int n_48khz; |
2958 | int cts_48khz; |
2961 | int cts_48khz; |
2959 | 2962 | ||
2960 | }; |
2963 | }; |
2961 | 2964 | ||
2962 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2965 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2963 | 2966 | ||
2964 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2967 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2965 | u32 tiling_pipe_num, |
2968 | u32 tiling_pipe_num, |
2966 | u32 max_rb_num, |
2969 | u32 max_rb_num, |
2967 | u32 total_max_rb_num, |
2970 | u32 total_max_rb_num, |
2968 | u32 enabled_rb_mask); |
2971 | u32 enabled_rb_mask); |
2969 | 2972 | ||
2970 | /* |
2973 | /* |
2971 | * evergreen functions used by radeon_encoder.c |
2974 | * evergreen functions used by radeon_encoder.c |
2972 | */ |
2975 | */ |
2973 | 2976 | ||
2974 | extern int ni_init_microcode(struct radeon_device *rdev); |
2977 | extern int ni_init_microcode(struct radeon_device *rdev); |
2975 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
2978 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
2976 | 2979 | ||
2977 | /* radeon_acpi.c */ |
2980 | /* radeon_acpi.c */ |
2978 | #if defined(CONFIG_ACPI) |
2981 | #if defined(CONFIG_ACPI) |
2979 | extern int radeon_acpi_init(struct radeon_device *rdev); |
2982 | extern int radeon_acpi_init(struct radeon_device *rdev); |
2980 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
2983 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
2981 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2984 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2982 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
2985 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
2983 | u8 perf_req, bool advertise); |
2986 | u8 perf_req, bool advertise); |
2984 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
2987 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
2985 | #else |
2988 | #else |
2986 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
2989 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
2987 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
2990 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
2988 | #endif |
2991 | #endif |
2989 | 2992 | ||
2990 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2993 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2991 | struct radeon_cs_packet *pkt, |
2994 | struct radeon_cs_packet *pkt, |
2992 | unsigned idx); |
2995 | unsigned idx); |
2993 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
2996 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
2994 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2997 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2995 | struct radeon_cs_packet *pkt); |
2998 | struct radeon_cs_packet *pkt); |
2996 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2999 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2997 | struct radeon_cs_reloc **cs_reloc, |
3000 | struct radeon_cs_reloc **cs_reloc, |
2998 | int nomm); |
3001 | int nomm); |
2999 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
3002 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
3000 | uint32_t *vline_start_end, |
3003 | uint32_t *vline_start_end, |
3001 | uint32_t *vline_status); |
3004 | uint32_t *vline_status); |
3002 | 3005 | ||
3003 | #include "radeon_object.h" |
3006 | #include "radeon_object.h" |
3004 | 3007 | ||
3005 | #define DRM_UDELAY(d) udelay(d) |
3008 | #define DRM_UDELAY(d) udelay(d) |
3006 | 3009 | ||
3007 | resource_size_t |
3010 | resource_size_t |
3008 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
3011 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
3009 | resource_size_t |
3012 | resource_size_t |
3010 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
3013 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
3011 | 3014 | ||
3012 | 3015 | ||
3013 | #endif><>><>><>><>>>>>=>=>><>><>><>><>><>><>><>><>><>><>><>=>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
3016 | #endif><>><>><>><>>>>>=>=>><>><>><>><>><>><>><>><>><>><>><>=>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |