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| Rev 5078 | Rev 5179 | ||
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| Line 112... | Line 112... | ||
| 112 | extern int radeon_vm_size; |
112 | extern int radeon_vm_size; |
| 113 | extern int radeon_vm_block_size; |
113 | extern int radeon_vm_block_size; |
| 114 | extern int radeon_deep_color; |
114 | extern int radeon_deep_color; |
| 115 | extern int radeon_use_pflipirq; |
115 | extern int radeon_use_pflipirq; |
| 116 | extern int radeon_bapm; |
116 | extern int radeon_bapm; |
| - | 117 | extern int radeon_backlight; |
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| Line 117... | Line 118... | ||
| 117 | 118 | ||
| 118 | 119 | ||
| 119 | typedef struct pm_message { |
120 | typedef struct pm_message { |
| Line 1138... | Line 1139... | ||
| 1138 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1139 | #define R600_WB_IH_WPTR_OFFSET 2048 |
| 1139 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1140 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
| 1140 | #define R600_WB_EVENT_OFFSET 3072 |
1141 | #define R600_WB_EVENT_OFFSET 3072 |
| 1141 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1142 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
| 1142 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
1143 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
| - | 1144 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
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| - | 1145 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
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| Line 1143... | Line 1146... | ||
| 1143 | 1146 | ||
| 1144 | /** |
1147 | /** |
| 1145 | * struct radeon_pm - power management datas |
1148 | * struct radeon_pm - power management datas |
| 1146 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1149 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |