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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __RADEON_H__ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | 30 | ||
31 | //#include "radeon_object.h" |
31 | //#include "radeon_object.h" |
32 | 32 | ||
33 | /* TODO: Here are things that needs to be done : |
33 | /* TODO: Here are things that needs to be done : |
34 | * - surface allocator & initializer : (bit like scratch reg) should |
34 | * - surface allocator & initializer : (bit like scratch reg) should |
35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
36 | * related to surface |
36 | * related to surface |
37 | * - WB : write back stuff (do it bit like scratch reg things) |
37 | * - WB : write back stuff (do it bit like scratch reg things) |
38 | * - Vblank : look at Jesse's rework and what we should do |
38 | * - Vblank : look at Jesse's rework and what we should do |
39 | * - r600/r700: gart & cp |
39 | * - r600/r700: gart & cp |
40 | * - cs : clean cs ioctl use bitmap & things like that. |
40 | * - cs : clean cs ioctl use bitmap & things like that. |
41 | * - power management stuff |
41 | * - power management stuff |
42 | * - Barrier in gart code |
42 | * - Barrier in gart code |
43 | * - Unmappabled vram ? |
43 | * - Unmappabled vram ? |
44 | * - TESTING, TESTING, TESTING |
44 | * - TESTING, TESTING, TESTING |
45 | */ |
45 | */ |
46 | 46 | ||
47 | #include "types.h" |
47 | #include |
- | 48 | #include |
|
- | 49 | ||
48 | #include "pci.h" |
50 | #include |
49 | 51 | ||
50 | #include "errno-base.h" |
52 | #include |
51 | 53 | ||
52 | #include "radeon_mode.h" |
54 | #include "radeon_mode.h" |
53 | #include "radeon_reg.h" |
55 | #include "radeon_reg.h" |
54 | #include "r300.h" |
56 | #include "r300.h" |
55 | 57 | ||
56 | #include |
58 | #include |
57 | 59 | ||
58 | extern int radeon_dynclks; |
60 | extern int radeon_dynclks; |
59 | extern int radeon_gart_size; |
61 | extern int radeon_gart_size; |
60 | extern int radeon_r4xx_atom; |
62 | extern int radeon_r4xx_atom; |
61 | 63 | ||
62 | - | ||
63 | 64 | ||
64 | /* |
65 | /* |
65 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
66 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
66 | * symbol; |
67 | * symbol; |
67 | */ |
68 | */ |
68 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
69 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
69 | #define RADEON_IB_POOL_SIZE 16 |
70 | #define RADEON_IB_POOL_SIZE 16 |
70 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
71 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
71 | #define RADEONFB_CONN_LIMIT 4 |
72 | #define RADEONFB_CONN_LIMIT 4 |
72 | 73 | ||
73 | enum radeon_family { |
74 | enum radeon_family { |
74 | CHIP_R100, |
75 | CHIP_R100, |
75 | CHIP_RV100, |
76 | CHIP_RV100, |
76 | CHIP_RS100, |
77 | CHIP_RS100, |
77 | CHIP_RV200, |
78 | CHIP_RV200, |
78 | CHIP_RS200, |
79 | CHIP_RS200, |
79 | CHIP_R200, |
80 | CHIP_R200, |
80 | CHIP_RV250, |
81 | CHIP_RV250, |
81 | CHIP_RS300, |
82 | CHIP_RS300, |
82 | CHIP_RV280, |
83 | CHIP_RV280, |
83 | CHIP_R300, |
84 | CHIP_R300, |
84 | CHIP_R350, |
85 | CHIP_R350, |
85 | CHIP_RV350, |
86 | CHIP_RV350, |
86 | CHIP_RV380, |
87 | CHIP_RV380, |
87 | CHIP_R420, |
88 | CHIP_R420, |
88 | CHIP_R423, |
89 | CHIP_R423, |
89 | CHIP_RV410, |
90 | CHIP_RV410, |
90 | CHIP_RS400, |
91 | CHIP_RS400, |
91 | CHIP_RS480, |
92 | CHIP_RS480, |
92 | CHIP_RS600, |
93 | CHIP_RS600, |
93 | CHIP_RS690, |
94 | CHIP_RS690, |
94 | CHIP_RS740, |
95 | CHIP_RS740, |
95 | CHIP_RV515, |
96 | CHIP_RV515, |
96 | CHIP_R520, |
97 | CHIP_R520, |
97 | CHIP_RV530, |
98 | CHIP_RV530, |
98 | CHIP_RV560, |
99 | CHIP_RV560, |
99 | CHIP_RV570, |
100 | CHIP_RV570, |
100 | CHIP_R580, |
101 | CHIP_R580, |
101 | CHIP_R600, |
102 | CHIP_R600, |
102 | CHIP_RV610, |
103 | CHIP_RV610, |
103 | CHIP_RV630, |
104 | CHIP_RV630, |
104 | CHIP_RV620, |
105 | CHIP_RV620, |
105 | CHIP_RV635, |
106 | CHIP_RV635, |
106 | CHIP_RV670, |
107 | CHIP_RV670, |
107 | CHIP_RS780, |
108 | CHIP_RS780, |
108 | CHIP_RV770, |
109 | CHIP_RV770, |
109 | CHIP_RV730, |
110 | CHIP_RV730, |
110 | CHIP_RV710, |
111 | CHIP_RV710, |
111 | CHIP_RV740, |
112 | CHIP_RV740, |
112 | CHIP_LAST, |
113 | CHIP_LAST, |
113 | }; |
114 | }; |
114 | 115 | ||
115 | enum radeon_chip_flags { |
116 | enum radeon_chip_flags { |
116 | RADEON_FAMILY_MASK = 0x0000ffffUL, |
117 | RADEON_FAMILY_MASK = 0x0000ffffUL, |
117 | RADEON_FLAGS_MASK = 0xffff0000UL, |
118 | RADEON_FLAGS_MASK = 0xffff0000UL, |
118 | RADEON_IS_MOBILITY = 0x00010000UL, |
119 | RADEON_IS_MOBILITY = 0x00010000UL, |
119 | RADEON_IS_IGP = 0x00020000UL, |
120 | RADEON_IS_IGP = 0x00020000UL, |
120 | RADEON_SINGLE_CRTC = 0x00040000UL, |
121 | RADEON_SINGLE_CRTC = 0x00040000UL, |
121 | RADEON_IS_AGP = 0x00080000UL, |
122 | RADEON_IS_AGP = 0x00080000UL, |
122 | RADEON_HAS_HIERZ = 0x00100000UL, |
123 | RADEON_HAS_HIERZ = 0x00100000UL, |
123 | RADEON_IS_PCIE = 0x00200000UL, |
124 | RADEON_IS_PCIE = 0x00200000UL, |
124 | RADEON_NEW_MEMMAP = 0x00400000UL, |
125 | RADEON_NEW_MEMMAP = 0x00400000UL, |
125 | RADEON_IS_PCI = 0x00800000UL, |
126 | RADEON_IS_PCI = 0x00800000UL, |
126 | RADEON_IS_IGPGART = 0x01000000UL, |
127 | RADEON_IS_IGPGART = 0x01000000UL, |
127 | }; |
128 | }; |
128 | 129 | ||
129 | 130 | ||
130 | /* |
131 | /* |
131 | * Errata workarounds. |
132 | * Errata workarounds. |
132 | */ |
133 | */ |
133 | enum radeon_pll_errata { |
134 | enum radeon_pll_errata { |
134 | CHIP_ERRATA_R300_CG = 0x00000001, |
135 | CHIP_ERRATA_R300_CG = 0x00000001, |
135 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
136 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
136 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
137 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
137 | }; |
138 | }; |
138 | 139 | ||
139 | 140 | ||
140 | struct radeon_device; |
141 | struct radeon_device; |
141 | 142 | ||
142 | 143 | ||
143 | /* |
144 | /* |
144 | * BIOS. |
145 | * BIOS. |
145 | */ |
146 | */ |
146 | bool radeon_get_bios(struct radeon_device *rdev); |
147 | bool radeon_get_bios(struct radeon_device *rdev); |
147 | 148 | ||
148 | /* |
149 | /* |
149 | * Clocks |
150 | * Clocks |
150 | */ |
151 | */ |
151 | 152 | ||
152 | struct radeon_clock { |
153 | struct radeon_clock { |
153 | struct radeon_pll p1pll; |
154 | struct radeon_pll p1pll; |
154 | struct radeon_pll p2pll; |
155 | struct radeon_pll p2pll; |
155 | struct radeon_pll spll; |
156 | struct radeon_pll spll; |
156 | struct radeon_pll mpll; |
157 | struct radeon_pll mpll; |
157 | /* 10 Khz units */ |
158 | /* 10 Khz units */ |
158 | uint32_t default_mclk; |
159 | uint32_t default_mclk; |
159 | uint32_t default_sclk; |
160 | uint32_t default_sclk; |
160 | }; |
161 | }; |
161 | 162 | ||
162 | /* |
163 | /* |
163 | * Fences. |
164 | * Fences. |
164 | */ |
165 | */ |
165 | struct radeon_fence_driver { |
166 | struct radeon_fence_driver { |
166 | uint32_t scratch_reg; |
167 | uint32_t scratch_reg; |
167 | // atomic_t seq; |
168 | // atomic_t seq; |
168 | uint32_t last_seq; |
169 | uint32_t last_seq; |
169 | unsigned long count_timeout; |
170 | unsigned long count_timeout; |
170 | // wait_queue_head_t queue; |
171 | // wait_queue_head_t queue; |
171 | // rwlock_t lock; |
172 | // rwlock_t lock; |
172 | // struct list_head created; |
173 | struct list_head created; |
173 | // struct list_head emited; |
174 | struct list_head emited; |
174 | // struct list_head signaled; |
175 | struct list_head signaled; |
175 | }; |
176 | }; |
176 | 177 | ||
177 | struct radeon_fence { |
178 | struct radeon_fence { |
178 | struct radeon_device *rdev; |
179 | struct radeon_device *rdev; |
179 | // struct kref kref; |
180 | // struct kref kref; |
180 | // struct list_head list; |
181 | struct list_head list; |
181 | /* protected by radeon_fence.lock */ |
182 | /* protected by radeon_fence.lock */ |
182 | uint32_t seq; |
183 | uint32_t seq; |
183 | unsigned long timeout; |
184 | unsigned long timeout; |
184 | bool emited; |
185 | bool emited; |
185 | bool signaled; |
186 | bool signaled; |
186 | }; |
187 | }; |
187 | 188 | ||
188 | int radeon_fence_driver_init(struct radeon_device *rdev); |
189 | int radeon_fence_driver_init(struct radeon_device *rdev); |
189 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
190 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
190 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
191 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
191 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
192 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
192 | void radeon_fence_process(struct radeon_device *rdev); |
193 | void radeon_fence_process(struct radeon_device *rdev); |
193 | bool radeon_fence_signaled(struct radeon_fence *fence); |
194 | bool radeon_fence_signaled(struct radeon_fence *fence); |
194 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
195 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
195 | int radeon_fence_wait_next(struct radeon_device *rdev); |
196 | int radeon_fence_wait_next(struct radeon_device *rdev); |
196 | int radeon_fence_wait_last(struct radeon_device *rdev); |
197 | int radeon_fence_wait_last(struct radeon_device *rdev); |
197 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
198 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
198 | void radeon_fence_unref(struct radeon_fence **fence); |
199 | void radeon_fence_unref(struct radeon_fence **fence); |
199 | 200 | ||
200 | 201 | ||
201 | /* |
202 | /* |
202 | * Radeon buffer. |
203 | * Radeon buffer. |
203 | */ |
204 | */ |
204 | struct radeon_object; |
205 | struct radeon_object; |
205 | 206 | ||
206 | struct radeon_object_list { |
207 | struct radeon_object_list { |
207 | // struct list_head list; |
208 | struct list_head list; |
208 | struct radeon_object *robj; |
209 | struct radeon_object *robj; |
209 | uint64_t gpu_offset; |
210 | uint64_t gpu_offset; |
210 | unsigned rdomain; |
211 | unsigned rdomain; |
211 | unsigned wdomain; |
212 | unsigned wdomain; |
212 | }; |
213 | }; |
213 | 214 | ||
214 | 215 | ||
215 | 216 | ||
216 | 217 | ||
217 | 218 | ||
218 | - | ||
219 | 219 | ||
220 | /* |
220 | /* |
221 | * GART structures, functions & helpers |
221 | * GART structures, functions & helpers |
222 | */ |
222 | */ |
223 | struct radeon_mc; |
223 | struct radeon_mc; |
224 | 224 | ||
225 | struct radeon_gart_table_ram { |
225 | struct radeon_gart_table_ram { |
226 | volatile uint32_t *ptr; |
226 | volatile uint32_t *ptr; |
227 | }; |
227 | }; |
228 | 228 | ||
229 | struct radeon_gart_table_vram { |
229 | struct radeon_gart_table_vram { |
230 | struct radeon_object *robj; |
230 | struct radeon_object *robj; |
231 | volatile uint32_t *ptr; |
231 | volatile uint32_t *ptr; |
232 | }; |
232 | }; |
233 | 233 | ||
234 | union radeon_gart_table { |
234 | union radeon_gart_table { |
235 | struct radeon_gart_table_ram ram; |
235 | struct radeon_gart_table_ram ram; |
236 | struct radeon_gart_table_vram vram; |
236 | struct radeon_gart_table_vram vram; |
237 | }; |
237 | }; |
238 | 238 | ||
239 | struct radeon_gart { |
239 | struct radeon_gart { |
240 | dma_addr_t table_addr; |
240 | dma_addr_t table_addr; |
241 | unsigned num_gpu_pages; |
241 | unsigned num_gpu_pages; |
242 | unsigned num_cpu_pages; |
242 | unsigned num_cpu_pages; |
243 | unsigned table_size; |
243 | unsigned table_size; |
244 | union radeon_gart_table table; |
244 | union radeon_gart_table table; |
245 | struct page **pages; |
245 | struct page **pages; |
246 | dma_addr_t *pages_addr; |
246 | dma_addr_t *pages_addr; |
247 | bool ready; |
247 | bool ready; |
248 | }; |
248 | }; |
249 | 249 | ||
250 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
250 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
251 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
251 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
252 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
252 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
253 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
253 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
254 | int radeon_gart_init(struct radeon_device *rdev); |
254 | int radeon_gart_init(struct radeon_device *rdev); |
255 | void radeon_gart_fini(struct radeon_device *rdev); |
255 | void radeon_gart_fini(struct radeon_device *rdev); |
256 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
256 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
257 | int pages); |
257 | int pages); |
258 | //int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
258 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
259 | // int pages, struct page **pagelist); |
259 | int pages, u32_t *pagelist); |
260 | 260 | ||
261 | 261 | ||
262 | /* |
262 | /* |
263 | * GPU MC structures, functions & helpers |
263 | * GPU MC structures, functions & helpers |
264 | */ |
264 | */ |
265 | struct radeon_mc { |
265 | struct radeon_mc { |
266 | resource_size_t aper_size; |
266 | resource_size_t aper_size; |
267 | resource_size_t aper_base; |
267 | resource_size_t aper_base; |
268 | resource_size_t agp_base; |
268 | resource_size_t agp_base; |
269 | unsigned gtt_location; |
269 | unsigned gtt_location; |
270 | unsigned gtt_size; |
270 | unsigned gtt_size; |
271 | unsigned vram_location; |
271 | unsigned vram_location; |
272 | unsigned vram_size; |
272 | unsigned vram_size; |
273 | unsigned vram_width; |
273 | unsigned vram_width; |
274 | int vram_mtrr; |
274 | int vram_mtrr; |
275 | bool vram_is_ddr; |
275 | bool vram_is_ddr; |
276 | }; |
276 | }; |
277 | 277 | ||
278 | int radeon_mc_setup(struct radeon_device *rdev); |
278 | int radeon_mc_setup(struct radeon_device *rdev); |
279 | 279 | ||
280 | 280 | ||
281 | /* |
281 | /* |
282 | * GPU scratch registers structures, functions & helpers |
282 | * GPU scratch registers structures, functions & helpers |
283 | */ |
283 | */ |
284 | struct radeon_scratch { |
284 | struct radeon_scratch { |
285 | unsigned num_reg; |
285 | unsigned num_reg; |
286 | bool free[32]; |
286 | bool free[32]; |
287 | uint32_t reg[32]; |
287 | uint32_t reg[32]; |
288 | }; |
288 | }; |
289 | 289 | ||
290 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
290 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
291 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
291 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
292 | 292 | ||
293 | 293 | ||
294 | /* |
294 | /* |
295 | * IRQS. |
295 | * IRQS. |
296 | */ |
296 | */ |
297 | struct radeon_irq { |
297 | struct radeon_irq { |
298 | bool installed; |
298 | bool installed; |
299 | bool sw_int; |
299 | bool sw_int; |
300 | /* FIXME: use a define max crtc rather than hardcode it */ |
300 | /* FIXME: use a define max crtc rather than hardcode it */ |
301 | bool crtc_vblank_int[2]; |
301 | bool crtc_vblank_int[2]; |
302 | }; |
302 | }; |
303 | 303 | ||
304 | int radeon_irq_kms_init(struct radeon_device *rdev); |
304 | int radeon_irq_kms_init(struct radeon_device *rdev); |
305 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
305 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
306 | 306 | ||
307 | 307 | ||
308 | /* |
308 | /* |
309 | * CP & ring. |
309 | * CP & ring. |
310 | */ |
310 | */ |
311 | struct radeon_ib { |
311 | struct radeon_ib { |
312 | // struct list_head list; |
312 | struct list_head list; |
313 | unsigned long idx; |
313 | unsigned long idx; |
314 | uint64_t gpu_addr; |
314 | uint64_t gpu_addr; |
315 | struct radeon_fence *fence; |
315 | struct radeon_fence *fence; |
316 | volatile uint32_t *ptr; |
316 | volatile uint32_t *ptr; |
317 | uint32_t length_dw; |
317 | uint32_t length_dw; |
318 | }; |
318 | }; |
319 | 319 | ||
320 | struct radeon_ib_pool { |
320 | struct radeon_ib_pool { |
321 | // struct mutex mutex; |
321 | // struct mutex mutex; |
322 | struct radeon_object *robj; |
322 | struct radeon_object *robj; |
323 | // struct list_head scheduled_ibs; |
323 | struct list_head scheduled_ibs; |
324 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
324 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
325 | bool ready; |
325 | bool ready; |
326 | // DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
326 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
327 | }; |
327 | }; |
328 | 328 | ||
329 | struct radeon_cp { |
329 | struct radeon_cp { |
330 | struct radeon_object *ring_obj; |
330 | struct radeon_object *ring_obj; |
331 | volatile uint32_t *ring; |
331 | volatile uint32_t *ring; |
332 | unsigned rptr; |
332 | unsigned rptr; |
333 | unsigned wptr; |
333 | unsigned wptr; |
334 | unsigned wptr_old; |
334 | unsigned wptr_old; |
335 | unsigned ring_size; |
335 | unsigned ring_size; |
336 | unsigned ring_free_dw; |
336 | unsigned ring_free_dw; |
337 | int count_dw; |
337 | int count_dw; |
338 | uint64_t gpu_addr; |
338 | uint64_t gpu_addr; |
339 | uint32_t align_mask; |
339 | uint32_t align_mask; |
340 | uint32_t ptr_mask; |
340 | uint32_t ptr_mask; |
341 | // struct mutex mutex; |
341 | // struct mutex mutex; |
342 | bool ready; |
342 | bool ready; |
343 | }; |
343 | }; |
344 | 344 | ||
345 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
345 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
346 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
346 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
347 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
347 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
348 | int radeon_ib_pool_init(struct radeon_device *rdev); |
348 | int radeon_ib_pool_init(struct radeon_device *rdev); |
349 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
349 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
350 | int radeon_ib_test(struct radeon_device *rdev); |
350 | int radeon_ib_test(struct radeon_device *rdev); |
351 | /* Ring access between begin & end cannot sleep */ |
351 | /* Ring access between begin & end cannot sleep */ |
352 | void radeon_ring_free_size(struct radeon_device *rdev); |
352 | void radeon_ring_free_size(struct radeon_device *rdev); |
353 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
353 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
354 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
354 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
355 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
355 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
356 | int radeon_ring_test(struct radeon_device *rdev); |
356 | int radeon_ring_test(struct radeon_device *rdev); |
357 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
357 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
358 | void radeon_ring_fini(struct radeon_device *rdev); |
358 | void radeon_ring_fini(struct radeon_device *rdev); |
359 | 359 | ||
360 | 360 | ||
361 | /* |
361 | /* |
362 | * CS. |
362 | * CS. |
363 | */ |
363 | */ |
364 | struct radeon_cs_reloc { |
364 | struct radeon_cs_reloc { |
365 | // struct drm_gem_object *gobj; |
365 | // struct drm_gem_object *gobj; |
366 | struct radeon_object *robj; |
366 | struct radeon_object *robj; |
367 | // struct radeon_object_list lobj; |
367 | struct radeon_object_list lobj; |
368 | uint32_t handle; |
368 | uint32_t handle; |
369 | uint32_t flags; |
369 | uint32_t flags; |
370 | }; |
370 | }; |
371 | 371 | ||
372 | struct radeon_cs_chunk { |
372 | struct radeon_cs_chunk { |
373 | uint32_t chunk_id; |
373 | uint32_t chunk_id; |
374 | uint32_t length_dw; |
374 | uint32_t length_dw; |
375 | uint32_t *kdata; |
375 | uint32_t *kdata; |
376 | }; |
376 | }; |
377 | 377 | ||
378 | struct radeon_cs_parser { |
378 | struct radeon_cs_parser { |
379 | struct radeon_device *rdev; |
379 | struct radeon_device *rdev; |
380 | // struct drm_file *filp; |
380 | // struct drm_file *filp; |
381 | /* chunks */ |
381 | /* chunks */ |
382 | unsigned nchunks; |
382 | unsigned nchunks; |
383 | struct radeon_cs_chunk *chunks; |
383 | struct radeon_cs_chunk *chunks; |
384 | uint64_t *chunks_array; |
384 | uint64_t *chunks_array; |
385 | /* IB */ |
385 | /* IB */ |
386 | unsigned idx; |
386 | unsigned idx; |
387 | /* relocations */ |
387 | /* relocations */ |
388 | unsigned nrelocs; |
388 | unsigned nrelocs; |
389 | struct radeon_cs_reloc *relocs; |
389 | struct radeon_cs_reloc *relocs; |
390 | struct radeon_cs_reloc **relocs_ptr; |
390 | struct radeon_cs_reloc **relocs_ptr; |
391 | // struct list_head validated; |
391 | struct list_head validated; |
392 | /* indices of various chunks */ |
392 | /* indices of various chunks */ |
393 | int chunk_ib_idx; |
393 | int chunk_ib_idx; |
394 | int chunk_relocs_idx; |
394 | int chunk_relocs_idx; |
395 | struct radeon_ib *ib; |
395 | struct radeon_ib *ib; |
396 | void *track; |
396 | void *track; |
397 | }; |
397 | }; |
398 | 398 | ||
399 | struct radeon_cs_packet { |
399 | struct radeon_cs_packet { |
400 | unsigned idx; |
400 | unsigned idx; |
401 | unsigned type; |
401 | unsigned type; |
402 | unsigned reg; |
402 | unsigned reg; |
403 | unsigned opcode; |
403 | unsigned opcode; |
404 | int count; |
404 | int count; |
405 | unsigned one_reg_wr; |
405 | unsigned one_reg_wr; |
406 | }; |
406 | }; |
407 | 407 | ||
408 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
408 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
409 | struct radeon_cs_packet *pkt, |
409 | struct radeon_cs_packet *pkt, |
410 | unsigned idx, unsigned reg); |
410 | unsigned idx, unsigned reg); |
411 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
411 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
412 | struct radeon_cs_packet *pkt); |
412 | struct radeon_cs_packet *pkt); |
413 | 413 | ||
414 | 414 | ||
415 | /* |
415 | /* |
416 | * AGP |
416 | * AGP |
417 | */ |
417 | */ |
418 | int radeon_agp_init(struct radeon_device *rdev); |
418 | int radeon_agp_init(struct radeon_device *rdev); |
419 | void radeon_agp_fini(struct radeon_device *rdev); |
419 | void radeon_agp_fini(struct radeon_device *rdev); |
420 | 420 | ||
421 | 421 | ||
422 | /* |
422 | /* |
423 | * Writeback |
423 | * Writeback |
424 | */ |
424 | */ |
425 | struct radeon_wb { |
425 | struct radeon_wb { |
426 | struct radeon_object *wb_obj; |
426 | struct radeon_object *wb_obj; |
427 | volatile uint32_t *wb; |
427 | volatile uint32_t *wb; |
428 | uint64_t gpu_addr; |
428 | uint64_t gpu_addr; |
429 | }; |
429 | }; |
430 | 430 | ||
431 | 431 | ||
432 | /* |
432 | /* |
433 | * ASIC specific functions. |
433 | * ASIC specific functions. |
434 | */ |
434 | */ |
435 | struct radeon_asic { |
435 | struct radeon_asic { |
436 | int (*init)(struct radeon_device *rdev); |
436 | int (*init)(struct radeon_device *rdev); |
437 | void (*errata)(struct radeon_device *rdev); |
437 | void (*errata)(struct radeon_device *rdev); |
438 | void (*vram_info)(struct radeon_device *rdev); |
438 | void (*vram_info)(struct radeon_device *rdev); |
439 | int (*gpu_reset)(struct radeon_device *rdev); |
439 | int (*gpu_reset)(struct radeon_device *rdev); |
440 | int (*mc_init)(struct radeon_device *rdev); |
440 | int (*mc_init)(struct radeon_device *rdev); |
441 | void (*mc_fini)(struct radeon_device *rdev); |
441 | void (*mc_fini)(struct radeon_device *rdev); |
442 | int (*wb_init)(struct radeon_device *rdev); |
442 | int (*wb_init)(struct radeon_device *rdev); |
443 | void (*wb_fini)(struct radeon_device *rdev); |
443 | void (*wb_fini)(struct radeon_device *rdev); |
444 | int (*gart_enable)(struct radeon_device *rdev); |
444 | int (*gart_enable)(struct radeon_device *rdev); |
445 | void (*gart_disable)(struct radeon_device *rdev); |
445 | void (*gart_disable)(struct radeon_device *rdev); |
446 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
446 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
447 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
447 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
448 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
448 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
449 | void (*cp_fini)(struct radeon_device *rdev); |
449 | void (*cp_fini)(struct radeon_device *rdev); |
450 | void (*cp_disable)(struct radeon_device *rdev); |
450 | void (*cp_disable)(struct radeon_device *rdev); |
451 | void (*ring_start)(struct radeon_device *rdev); |
451 | void (*ring_start)(struct radeon_device *rdev); |
452 | int (*irq_set)(struct radeon_device *rdev); |
452 | int (*irq_set)(struct radeon_device *rdev); |
453 | int (*irq_process)(struct radeon_device *rdev); |
453 | int (*irq_process)(struct radeon_device *rdev); |
454 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
454 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
455 | int (*cs_parse)(struct radeon_cs_parser *p); |
455 | int (*cs_parse)(struct radeon_cs_parser *p); |
456 | int (*copy_blit)(struct radeon_device *rdev, |
456 | int (*copy_blit)(struct radeon_device *rdev, |
457 | uint64_t src_offset, |
457 | uint64_t src_offset, |
458 | uint64_t dst_offset, |
458 | uint64_t dst_offset, |
459 | unsigned num_pages, |
459 | unsigned num_pages, |
460 | struct radeon_fence *fence); |
460 | struct radeon_fence *fence); |
461 | int (*copy_dma)(struct radeon_device *rdev, |
461 | int (*copy_dma)(struct radeon_device *rdev, |
462 | uint64_t src_offset, |
462 | uint64_t src_offset, |
463 | uint64_t dst_offset, |
463 | uint64_t dst_offset, |
464 | unsigned num_pages, |
464 | unsigned num_pages, |
465 | struct radeon_fence *fence); |
465 | struct radeon_fence *fence); |
466 | int (*copy)(struct radeon_device *rdev, |
466 | int (*copy)(struct radeon_device *rdev, |
467 | uint64_t src_offset, |
467 | uint64_t src_offset, |
468 | uint64_t dst_offset, |
468 | uint64_t dst_offset, |
469 | unsigned num_pages, |
469 | unsigned num_pages, |
470 | struct radeon_fence *fence); |
470 | struct radeon_fence *fence); |
471 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
471 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
472 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
472 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
473 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
473 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
474 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
474 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
475 | }; |
475 | }; |
476 | 476 | ||
477 | union radeon_asic_config { |
477 | union radeon_asic_config { |
478 | struct r300_asic r300; |
478 | struct r300_asic r300; |
479 | }; |
479 | }; |
480 | 480 | ||
481 | 481 | ||
482 | /* |
482 | /* |
483 | /* |
483 | /* |
484 | * Core structure, functions and helpers. |
484 | * Core structure, functions and helpers. |
485 | */ |
485 | */ |
486 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
486 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
487 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
487 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
488 | 488 | ||
489 | struct radeon_device { |
489 | struct radeon_device { |
490 | struct drm_device *ddev; |
490 | struct drm_device *ddev; |
491 | struct pci_dev *pdev; |
491 | struct pci_dev *pdev; |
492 | /* ASIC */ |
492 | /* ASIC */ |
493 | union radeon_asic_config config; |
493 | union radeon_asic_config config; |
494 | enum radeon_family family; |
494 | enum radeon_family family; |
495 | unsigned long flags; |
495 | unsigned long flags; |
496 | int usec_timeout; |
496 | int usec_timeout; |
497 | enum radeon_pll_errata pll_errata; |
497 | enum radeon_pll_errata pll_errata; |
498 | int num_gb_pipes; |
498 | int num_gb_pipes; |
499 | int disp_priority; |
499 | int disp_priority; |
500 | /* BIOS */ |
500 | /* BIOS */ |
501 | uint8_t *bios; |
501 | uint8_t *bios; |
502 | bool is_atom_bios; |
502 | bool is_atom_bios; |
503 | uint16_t bios_header_start; |
503 | uint16_t bios_header_start; |
504 | 504 | ||
505 | // struct radeon_object *stollen_vga_memory; |
505 | // struct radeon_object *stollen_vga_memory; |
506 | // struct fb_info *fbdev_info; |
506 | // struct fb_info *fbdev_info; |
507 | struct radeon_object *fbdev_robj; |
507 | struct radeon_object *fbdev_robj; |
508 | struct radeon_framebuffer *fbdev_rfb; |
508 | struct radeon_framebuffer *fbdev_rfb; |
509 | 509 | ||
510 | /* Register mmio */ |
510 | /* Register mmio */ |
511 | unsigned long rmmio_base; |
511 | unsigned long rmmio_base; |
512 | unsigned long rmmio_size; |
512 | unsigned long rmmio_size; |
513 | void *rmmio; |
513 | void *rmmio; |
514 | 514 | ||
515 | radeon_rreg_t mm_rreg; |
515 | radeon_rreg_t mm_rreg; |
516 | radeon_wreg_t mm_wreg; |
516 | radeon_wreg_t mm_wreg; |
517 | radeon_rreg_t mc_rreg; |
517 | radeon_rreg_t mc_rreg; |
518 | radeon_wreg_t mc_wreg; |
518 | radeon_wreg_t mc_wreg; |
519 | radeon_rreg_t pll_rreg; |
519 | radeon_rreg_t pll_rreg; |
520 | radeon_wreg_t pll_wreg; |
520 | radeon_wreg_t pll_wreg; |
521 | radeon_rreg_t pcie_rreg; |
521 | radeon_rreg_t pcie_rreg; |
522 | radeon_wreg_t pcie_wreg; |
522 | radeon_wreg_t pcie_wreg; |
523 | radeon_rreg_t pciep_rreg; |
523 | radeon_rreg_t pciep_rreg; |
524 | radeon_wreg_t pciep_wreg; |
524 | radeon_wreg_t pciep_wreg; |
525 | struct radeon_clock clock; |
525 | struct radeon_clock clock; |
526 | struct radeon_mc mc; |
526 | struct radeon_mc mc; |
527 | struct radeon_gart gart; |
527 | struct radeon_gart gart; |
528 | struct radeon_mode_info mode_info; |
528 | struct radeon_mode_info mode_info; |
529 | struct radeon_scratch scratch; |
529 | struct radeon_scratch scratch; |
530 | // struct radeon_mman mman; |
530 | // struct radeon_mman mman; |
531 | struct radeon_fence_driver fence_drv; |
531 | struct radeon_fence_driver fence_drv; |
532 | struct radeon_cp cp; |
532 | struct radeon_cp cp; |
533 | struct radeon_ib_pool ib_pool; |
533 | struct radeon_ib_pool ib_pool; |
534 | // struct radeon_irq irq; |
534 | // struct radeon_irq irq; |
535 | struct radeon_asic *asic; |
535 | struct radeon_asic *asic; |
536 | // struct radeon_gem gem; |
536 | // struct radeon_gem gem; |
537 | // struct mutex cs_mutex; |
537 | // struct mutex cs_mutex; |
538 | struct radeon_wb wb; |
538 | struct radeon_wb wb; |
539 | bool gpu_lockup; |
539 | bool gpu_lockup; |
540 | bool shutdown; |
540 | bool shutdown; |
541 | bool suspend; |
541 | bool suspend; |
542 | }; |
542 | }; |
543 | 543 | ||
544 | int radeon_device_init(struct radeon_device *rdev, |
544 | int radeon_device_init(struct radeon_device *rdev, |
545 | struct drm_device *ddev, |
545 | struct drm_device *ddev, |
546 | struct pci_dev *pdev, |
546 | struct pci_dev *pdev, |
547 | uint32_t flags); |
547 | uint32_t flags); |
548 | void radeon_device_fini(struct radeon_device *rdev); |
548 | void radeon_device_fini(struct radeon_device *rdev); |
549 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
549 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
550 | 550 | ||
551 | #define __iomem |
551 | #define __iomem |
552 | #define __force |
552 | #define __force |
553 | 553 | ||
554 | 554 | ||
555 | 555 | ||
556 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
556 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
557 | { |
557 | { |
558 | return *(const volatile uint8_t __force *) addr; |
558 | return *(const volatile uint8_t __force *) addr; |
559 | } |
559 | } |
560 | 560 | ||
561 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
561 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
562 | { |
562 | { |
563 | return *(const volatile uint16_t __force *) addr; |
563 | return *(const volatile uint16_t __force *) addr; |
564 | } |
564 | } |
565 | 565 | ||
566 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
566 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
567 | { |
567 | { |
568 | return *(const volatile uint32_t __force *) addr; |
568 | return *(const volatile uint32_t __force *) addr; |
569 | } |
569 | } |
570 | 570 | ||
571 | #define readb __raw_readb |
571 | #define readb __raw_readb |
572 | #define readw __raw_readw |
572 | #define readw __raw_readw |
573 | #define readl __raw_readl |
573 | #define readl __raw_readl |
574 | 574 | ||
575 | 575 | ||
576 | 576 | ||
577 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
577 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
578 | { |
578 | { |
579 | *(volatile uint8_t __force *) addr = b; |
579 | *(volatile uint8_t __force *) addr = b; |
580 | } |
580 | } |
581 | 581 | ||
582 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
582 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
583 | { |
583 | { |
584 | *(volatile uint16_t __force *) addr = b; |
584 | *(volatile uint16_t __force *) addr = b; |
585 | } |
585 | } |
586 | 586 | ||
587 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
587 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
588 | { |
588 | { |
589 | *(volatile uint32_t __force *) addr = b; |
589 | *(volatile uint32_t __force *) addr = b; |
590 | } |
590 | } |
591 | 591 | ||
592 | #define writeb __raw_writeb |
592 | #define writeb __raw_writeb |
593 | #define writew __raw_writew |
593 | #define writew __raw_writew |
594 | #define writel __raw_writel |
594 | #define writel __raw_writel |
595 | 595 | ||
596 | //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
596 | //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
597 | //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
597 | //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
598 | //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b |
598 | //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b |
599 | 599 | ||
600 | 600 | ||
601 | 601 | ||
602 | /* |
602 | /* |
603 | * Registers read & write functions. |
603 | * Registers read & write functions. |
604 | */ |
604 | */ |
605 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
605 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
606 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
606 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
607 | #define RREG32(reg) rdev->mm_rreg(rdev, (reg)) |
607 | #define RREG32(reg) rdev->mm_rreg(rdev, (reg)) |
608 | #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) |
608 | #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) |
609 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
609 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
610 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
610 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
611 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
611 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
612 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
612 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
613 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
613 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
614 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
614 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
615 | #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) |
615 | #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) |
616 | #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) |
616 | #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) |
617 | #define WREG32_P(reg, val, mask) \ |
617 | #define WREG32_P(reg, val, mask) \ |
618 | do { \ |
618 | do { \ |
619 | uint32_t tmp_ = RREG32(reg); \ |
619 | uint32_t tmp_ = RREG32(reg); \ |
620 | tmp_ &= (mask); \ |
620 | tmp_ &= (mask); \ |
621 | tmp_ |= ((val) & ~(mask)); \ |
621 | tmp_ |= ((val) & ~(mask)); \ |
622 | WREG32(reg, tmp_); \ |
622 | WREG32(reg, tmp_); \ |
623 | } while (0) |
623 | } while (0) |
624 | #define WREG32_PLL_P(reg, val, mask) \ |
624 | #define WREG32_PLL_P(reg, val, mask) \ |
625 | do { \ |
625 | do { \ |
626 | uint32_t tmp_ = RREG32_PLL(reg); \ |
626 | uint32_t tmp_ = RREG32_PLL(reg); \ |
627 | tmp_ &= (mask); \ |
627 | tmp_ &= (mask); \ |
628 | tmp_ |= ((val) & ~(mask)); \ |
628 | tmp_ |= ((val) & ~(mask)); \ |
629 | WREG32_PLL(reg, tmp_); \ |
629 | WREG32_PLL(reg, tmp_); \ |
630 | } while (0) |
630 | } while (0) |
631 | 631 | ||
632 | 632 | ||
633 | #define radeon_PCI_IDS \ |
633 | #define radeon_PCI_IDS \ |
634 | {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
634 | {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
635 | {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
635 | {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
636 | {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
636 | {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
637 | {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
637 | {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
638 | {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
638 | {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
639 | {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ |
639 | {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ |
640 | {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
640 | {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
641 | {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
641 | {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
642 | {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
642 | {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
643 | {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
643 | {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
644 | {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
644 | {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
645 | {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
645 | {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
646 | {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
646 | {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
647 | {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
647 | {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
648 | {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
648 | {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
649 | {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
649 | {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
650 | {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
650 | {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
651 | {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
651 | {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
652 | {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
652 | {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
653 | {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
653 | {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
654 | {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
654 | {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
655 | {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
655 | {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
656 | {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
656 | {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
657 | {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
657 | {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
658 | {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
658 | {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
659 | {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
659 | {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
660 | {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
660 | {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
661 | {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
661 | {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
662 | {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
662 | {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
663 | {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
663 | {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
664 | {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
664 | {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
665 | {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
665 | {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
666 | {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
666 | {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
667 | {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
667 | {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
668 | {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
668 | {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
669 | {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
669 | {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
670 | {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
670 | {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
671 | {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
671 | {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
672 | {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
672 | {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
673 | {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
673 | {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
674 | {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
674 | {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
675 | {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
675 | {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
676 | {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
676 | {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
677 | {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
677 | {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
678 | {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
678 | {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
679 | {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
679 | {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
680 | {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
680 | {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
681 | {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
681 | {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
682 | {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
682 | {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
683 | {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
683 | {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
684 | {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
684 | {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
685 | {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
685 | {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
686 | {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
686 | {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
687 | {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
687 | {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
688 | {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
688 | {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
689 | {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
689 | {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
690 | {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
690 | {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
691 | {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
691 | {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
692 | {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
692 | {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
693 | {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
693 | {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
694 | {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
694 | {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
695 | {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
695 | {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
696 | {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
696 | {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
697 | {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
697 | {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
698 | {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
698 | {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
699 | {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
699 | {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
700 | {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
700 | {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
701 | {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
701 | {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
702 | {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
702 | {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
703 | {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
703 | {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
704 | {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
704 | {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
705 | {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
705 | {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
706 | {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
706 | {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
707 | {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
707 | {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
708 | {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
708 | {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
709 | {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
709 | {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
710 | {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
710 | {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
711 | {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
711 | {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
712 | {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
712 | {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
713 | {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
713 | {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
714 | {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
714 | {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
715 | {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
715 | {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
716 | {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
716 | {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
717 | {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
717 | {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
718 | {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
718 | {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
719 | {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
719 | {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
720 | {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
720 | {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
721 | {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
721 | {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
722 | {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
722 | {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
723 | {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
723 | {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
724 | {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
724 | {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
725 | {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
725 | {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
726 | {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
726 | {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
727 | {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
727 | {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
728 | {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
728 | {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
729 | {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
729 | {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
730 | {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
730 | {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
731 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
731 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
732 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
732 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
733 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
733 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
734 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
734 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
735 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
735 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
736 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
736 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
737 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
737 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
738 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
738 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
739 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
739 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
740 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
740 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
741 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
741 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
742 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
742 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
743 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
743 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
744 | {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
744 | {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
745 | {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
745 | {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
746 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
746 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
747 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
747 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
748 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
748 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
749 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
749 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
750 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
750 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
751 | {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
751 | {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
752 | {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
752 | {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
753 | {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
753 | {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
754 | {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
754 | {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
755 | {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
755 | {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
756 | {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
756 | {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
757 | {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
757 | {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
758 | {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
758 | {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
759 | {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
759 | {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
760 | {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
760 | {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
761 | {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
761 | {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
762 | {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
762 | {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
763 | {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
763 | {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
764 | {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
764 | {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
765 | {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
765 | {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
766 | {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
766 | {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
767 | {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
767 | {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
768 | {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
768 | {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
769 | {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
769 | {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
770 | {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
770 | {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
771 | {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
771 | {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
772 | {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
772 | {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
773 | {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
773 | {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
774 | {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
774 | {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
775 | {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
775 | {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
776 | {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
776 | {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
777 | {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
777 | {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
778 | {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
778 | {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
779 | {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
779 | {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
780 | {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
780 | {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
781 | {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
781 | {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
782 | {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
782 | {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
783 | {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
783 | {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
784 | {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
784 | {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
785 | {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
785 | {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
786 | {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
786 | {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
787 | {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
787 | {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
788 | {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
788 | {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
789 | {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
789 | {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
790 | {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
790 | {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
791 | {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
791 | {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
792 | {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
792 | {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
793 | {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
793 | {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
794 | {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
794 | {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
795 | {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
795 | {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
796 | {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
796 | {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
797 | {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
797 | {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
798 | {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
798 | {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
799 | {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
799 | {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
800 | {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
800 | {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
801 | {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
801 | {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
802 | {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
802 | {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
803 | {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
803 | {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
804 | {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
804 | {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
805 | {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
805 | {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
806 | {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
806 | {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
807 | {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
807 | {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
808 | {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
808 | {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
809 | {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
809 | {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
810 | {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
810 | {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
811 | {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
811 | {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
812 | {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
812 | {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
813 | {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
813 | {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
814 | {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
814 | {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
815 | {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
815 | {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
816 | {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
816 | {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
817 | {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
817 | {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
818 | {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
818 | {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
819 | {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
819 | {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
820 | {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
820 | {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
821 | {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
821 | {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
822 | {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
822 | {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
823 | {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
823 | {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
824 | {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
824 | {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
825 | {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
825 | {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
826 | {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
826 | {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
827 | {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
827 | {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
828 | {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
828 | {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
829 | {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
829 | {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
830 | {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
830 | {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
831 | {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
831 | {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
832 | {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
832 | {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
833 | {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
833 | {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
834 | {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
834 | {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
835 | {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
835 | {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
836 | {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
836 | {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
837 | {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
837 | {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
838 | {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
838 | {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
839 | {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
839 | {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
840 | {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
840 | {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
841 | {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
841 | {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
842 | {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
842 | {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
843 | {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
843 | {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
844 | {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
844 | {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
845 | {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
845 | {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
846 | {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
846 | {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
847 | {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
847 | {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
848 | {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
848 | {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
849 | {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
849 | {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
850 | {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
850 | {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
851 | {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
851 | {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
852 | {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
852 | {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
853 | {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
853 | {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
854 | {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
854 | {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
855 | {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
855 | {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
856 | {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
856 | {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
857 | {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
857 | {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
858 | {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
858 | {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
859 | {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
859 | {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
860 | {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
860 | {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
861 | {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
861 | {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
862 | {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
862 | {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
863 | {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
863 | {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
864 | {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
864 | {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
865 | {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
865 | {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
866 | {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
866 | {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
867 | {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
867 | {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
868 | {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
868 | {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
869 | {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
869 | {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
870 | {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
870 | {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
871 | {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
871 | {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
872 | {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
872 | {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
873 | {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
873 | {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
874 | {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
874 | {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
875 | {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
875 | {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
876 | {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
876 | {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
877 | {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
877 | {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
878 | {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
878 | {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
879 | {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
879 | {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
880 | {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
880 | {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
881 | {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
881 | {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
882 | {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
882 | {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
883 | {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
883 | {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
884 | {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
884 | {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
885 | {0x1002, 0x94A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
885 | {0x1002, 0x94A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
886 | {0x1002, 0x94A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
886 | {0x1002, 0x94A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
887 | {0x1002, 0x94B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
887 | {0x1002, 0x94B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
888 | {0x1002, 0x94B3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
888 | {0x1002, 0x94B3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
889 | {0x1002, 0x94B5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
889 | {0x1002, 0x94B5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
890 | {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
890 | {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
891 | {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
891 | {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
892 | {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
892 | {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
893 | {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
893 | {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
894 | {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
894 | {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
895 | {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
895 | {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
896 | {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
896 | {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
897 | {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
897 | {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
898 | {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
898 | {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
899 | {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
899 | {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
900 | {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
900 | {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
901 | {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
901 | {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
902 | {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
902 | {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
903 | {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
903 | {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
904 | {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
904 | {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
905 | {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
905 | {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
906 | {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
906 | {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
907 | {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
907 | {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
908 | {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
908 | {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
909 | {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
909 | {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
910 | {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
910 | {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
911 | {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
911 | {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
912 | {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
912 | {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
913 | {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
913 | {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
914 | {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
914 | {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
915 | {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
915 | {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
916 | {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
916 | {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
917 | {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
917 | {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
918 | {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
918 | {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
919 | {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
919 | {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
920 | {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
920 | {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
921 | {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
921 | {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
922 | {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
922 | {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
923 | {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
923 | {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
924 | {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
924 | {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
925 | {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
925 | {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
926 | {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
926 | {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
927 | {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
927 | {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
928 | {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
928 | {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
929 | {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
929 | {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
930 | {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
930 | {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
931 | {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
931 | {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
932 | {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
932 | {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
933 | {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
933 | {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
934 | {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
934 | {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
935 | {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
935 | {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
936 | {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
936 | {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
937 | {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
937 | {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
938 | {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
938 | {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
939 | {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
939 | {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
940 | {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
940 | {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
941 | {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
941 | {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
942 | {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
942 | {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
943 | {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
943 | {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
944 | {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
944 | {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
945 | {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
945 | {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
946 | {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
946 | {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
947 | {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
947 | {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
948 | {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
948 | {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
949 | {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
949 | {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
950 | {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
950 | {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
951 | {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
951 | {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
952 | {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
952 | {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
953 | {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
953 | {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
954 | {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
954 | {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
955 | {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
955 | {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
956 | {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
956 | {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
957 | {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
957 | {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
958 | {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
958 | {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
959 | {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
959 | {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
960 | {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
960 | {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
961 | {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
961 | {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
962 | {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
962 | {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
963 | {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
963 | {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
964 | {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
964 | {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
965 | {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
965 | {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
966 | {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
966 | {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
967 | {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
967 | {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
968 | {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
968 | {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
969 | {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
969 | {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
970 | {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
970 | {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
971 | {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
971 | {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
972 | {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
972 | {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
973 | {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
973 | {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
974 | {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
974 | {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
975 | {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
975 | {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
976 | {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
976 | {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
977 | {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
977 | {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
978 | {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
978 | {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
979 | {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
979 | {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
980 | {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
980 | {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
981 | {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
981 | {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
982 | {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
982 | {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
983 | {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
983 | {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
984 | {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
984 | {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
985 | {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
985 | {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
986 | {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
986 | {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
987 | {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
987 | {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
988 | {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
988 | {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
989 | {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
989 | {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
990 | {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
990 | {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
991 | {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
991 | {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
992 | {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
992 | {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
993 | {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
993 | {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
994 | {0, 0, 0} |
994 | {0, 0, 0} |
995 | 995 | ||
996 | 996 | ||
997 | enum chipset_type { |
997 | enum chipset_type { |
998 | NOT_SUPPORTED, |
998 | NOT_SUPPORTED, |
999 | SUPPORTED, |
999 | SUPPORTED, |
1000 | }; |
1000 | }; |
1001 | 1001 | ||
1002 | struct agp_version { |
1002 | struct agp_version { |
1003 | u16_t major; |
1003 | u16_t major; |
1004 | u16_t minor; |
1004 | u16_t minor; |
1005 | }; |
1005 | }; |
1006 | 1006 | ||
1007 | struct agp_bridge_data; |
1007 | struct agp_bridge_data; |
1008 | 1008 | ||
1009 | struct agp_kern_info { |
1009 | struct agp_kern_info { |
1010 | struct agp_version version; |
1010 | struct agp_version version; |
1011 | struct pci_dev *device; |
1011 | struct pci_dev *device; |
1012 | enum chipset_type chipset; |
1012 | enum chipset_type chipset; |
1013 | unsigned long mode; |
1013 | unsigned long mode; |
1014 | unsigned long aper_base; |
1014 | unsigned long aper_base; |
1015 | size_t aper_size; |
1015 | size_t aper_size; |
1016 | int max_memory; /* In pages */ |
1016 | int max_memory; /* In pages */ |
1017 | int current_memory; |
1017 | int current_memory; |
1018 | bool cant_use_aperture; |
1018 | bool cant_use_aperture; |
1019 | unsigned long page_mask; |
1019 | unsigned long page_mask; |
1020 | // struct vm_operations_struct *vm_ops; |
1020 | // struct vm_operations_struct *vm_ops; |
1021 | }; |
1021 | }; |
1022 | 1022 | ||
1023 | 1023 | ||
1024 | /** |
1024 | /** |
1025 | * AGP data. |
1025 | * AGP data. |
1026 | * |
1026 | * |
1027 | * \sa drm_agp_init() and drm_device::agp. |
1027 | * \sa drm_agp_init() and drm_device::agp. |
1028 | */ |
1028 | */ |
1029 | struct drm_agp_head { |
1029 | struct drm_agp_head { |
1030 | struct agp_kern_info agp_info; /**< AGP device information */ |
1030 | struct agp_kern_info agp_info; /**< AGP device information */ |
1031 | // struct list_head memory; |
1031 | // struct list_head memory; |
1032 | unsigned long mode; /**< AGP mode */ |
1032 | unsigned long mode; /**< AGP mode */ |
1033 | struct agp_bridge_data *bridge; |
1033 | struct agp_bridge_data *bridge; |
1034 | int enabled; /**< whether the AGP bus as been enabled */ |
1034 | int enabled; /**< whether the AGP bus as been enabled */ |
1035 | int acquired; /**< whether the AGP device has been acquired */ |
1035 | int acquired; /**< whether the AGP device has been acquired */ |
1036 | unsigned long base; |
1036 | unsigned long base; |
1037 | int agp_mtrr; |
1037 | int agp_mtrr; |
1038 | int cant_use_aperture; |
1038 | int cant_use_aperture; |
1039 | unsigned long page_mask; |
1039 | unsigned long page_mask; |
1040 | }; |
1040 | }; |
1041 | 1041 | ||
1042 | 1042 | ||
1043 | 1043 | ||
1044 | 1044 | ||
1045 | 1045 | ||
1046 | /** |
1046 | /** |
1047 | * DRM device structure. This structure represent a complete card that |
1047 | * DRM device structure. This structure represent a complete card that |
1048 | * may contain multiple heads. |
1048 | * may contain multiple heads. |
1049 | */ |
1049 | */ |
1050 | struct drm_device { |
1050 | struct drm_device { |
1051 | 1051 | ||
1052 | int irq_enabled; /**< True if irq handler is enabled */ |
1052 | int irq_enabled; /**< True if irq handler is enabled */ |
1053 | __volatile__ long context_flag; /**< Context swapping flag */ |
1053 | __volatile__ long context_flag; /**< Context swapping flag */ |
1054 | __volatile__ long interrupt_flag; /**< Interruption handler flag */ |
1054 | __volatile__ long interrupt_flag; /**< Interruption handler flag */ |
1055 | __volatile__ long dma_flag; /**< DMA dispatch flag */ |
1055 | __volatile__ long dma_flag; /**< DMA dispatch flag */ |
1056 | int last_checked; /**< Last context checked for DMA */ |
1056 | int last_checked; /**< Last context checked for DMA */ |
1057 | int last_context; /**< Last current context */ |
1057 | int last_context; /**< Last current context */ |
1058 | unsigned long last_switch; /**< jiffies at last context switch */ |
1058 | unsigned long last_switch; /**< jiffies at last context switch */ |
1059 | 1059 | ||
1060 | struct drm_agp_head *agp; /**< AGP data */ |
1060 | struct drm_agp_head *agp; /**< AGP data */ |
1061 | 1061 | ||
1062 | struct pci_dev *pdev; /**< PCI device structure */ |
1062 | struct pci_dev *pdev; /**< PCI device structure */ |
1063 | int pci_vendor; /**< PCI vendor id */ |
1063 | int pci_vendor; /**< PCI vendor id */ |
1064 | int pci_device; /** PCI device id */ |
1064 | int pci_device; /** PCI device id */ |
1065 | int num_crtcs; /**< Number of CRTCs on this device */ |
1065 | int num_crtcs; /**< Number of CRTCs on this device */ |
1066 | void *dev_private; /**< device private data */ |
1066 | void *dev_private; /**< device private data */ |
1067 | void *mm_private; |
1067 | void *mm_private; |
1068 | 1068 | ||
1069 | // struct address_space *dev_mapping; |
1069 | // struct address_space *dev_mapping; |
1070 | 1070 | ||
1071 | struct drm_mode_config mode_config; /**< Current mode config */ |
1071 | struct drm_mode_config mode_config; /**< Current mode config */ |
1072 | 1072 | ||
1073 | }; |
1073 | }; |
1074 | 1074 | ||
1075 | 1075 | ||
1076 | 1076 | ||
1077 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
1077 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
1078 | 1078 | ||
1079 | 1079 | ||
1080 | /* |
1080 | /* |
1081 | * ASICs helpers. |
1081 | * ASICs helpers. |
1082 | */ |
1082 | */ |
1083 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1083 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1084 | (rdev->family == CHIP_RV200) || \ |
1084 | (rdev->family == CHIP_RV200) || \ |
1085 | (rdev->family == CHIP_RS100) || \ |
1085 | (rdev->family == CHIP_RS100) || \ |
1086 | (rdev->family == CHIP_RS200) || \ |
1086 | (rdev->family == CHIP_RS200) || \ |
1087 | (rdev->family == CHIP_RV250) || \ |
1087 | (rdev->family == CHIP_RV250) || \ |
1088 | (rdev->family == CHIP_RV280) || \ |
1088 | (rdev->family == CHIP_RV280) || \ |
1089 | (rdev->family == CHIP_RS300)) |
1089 | (rdev->family == CHIP_RS300)) |
1090 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
1090 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
1091 | (rdev->family == CHIP_RV350) || \ |
1091 | (rdev->family == CHIP_RV350) || \ |
1092 | (rdev->family == CHIP_R350) || \ |
1092 | (rdev->family == CHIP_R350) || \ |
1093 | (rdev->family == CHIP_RV380) || \ |
1093 | (rdev->family == CHIP_RV380) || \ |
1094 | (rdev->family == CHIP_R420) || \ |
1094 | (rdev->family == CHIP_R420) || \ |
1095 | (rdev->family == CHIP_R423) || \ |
1095 | (rdev->family == CHIP_R423) || \ |
1096 | (rdev->family == CHIP_RV410) || \ |
1096 | (rdev->family == CHIP_RV410) || \ |
1097 | (rdev->family == CHIP_RS400) || \ |
1097 | (rdev->family == CHIP_RS400) || \ |
1098 | (rdev->family == CHIP_RS480)) |
1098 | (rdev->family == CHIP_RS480)) |
1099 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1099 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1100 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1100 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1101 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1101 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1102 | 1102 | ||
1103 | 1103 | ||
1104 | /* |
1104 | /* |
1105 | * BIOS helpers. |
1105 | * BIOS helpers. |
1106 | */ |
1106 | */ |
1107 | #define RBIOS8(i) (rdev->bios[i]) |
1107 | #define RBIOS8(i) (rdev->bios[i]) |
1108 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
1108 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
1109 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
1109 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
1110 | 1110 | ||
1111 | int radeon_combios_init(struct radeon_device *rdev); |
1111 | int radeon_combios_init(struct radeon_device *rdev); |
1112 | void radeon_combios_fini(struct radeon_device *rdev); |
1112 | void radeon_combios_fini(struct radeon_device *rdev); |
1113 | int radeon_atombios_init(struct radeon_device *rdev); |
1113 | int radeon_atombios_init(struct radeon_device *rdev); |
1114 | void radeon_atombios_fini(struct radeon_device *rdev); |
1114 | void radeon_atombios_fini(struct radeon_device *rdev); |
1115 | 1115 | ||
1116 | 1116 | ||
1117 | /* |
1117 | /* |
1118 | * RING helpers. |
1118 | * RING helpers. |
1119 | */ |
1119 | */ |
1120 | #define CP_PACKET0 0x00000000 |
1120 | #define CP_PACKET0 0x00000000 |
1121 | #define PACKET0_BASE_INDEX_SHIFT 0 |
1121 | #define PACKET0_BASE_INDEX_SHIFT 0 |
1122 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
1122 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
1123 | #define PACKET0_COUNT_SHIFT 16 |
1123 | #define PACKET0_COUNT_SHIFT 16 |
1124 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
1124 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
1125 | #define CP_PACKET1 0x40000000 |
1125 | #define CP_PACKET1 0x40000000 |
1126 | #define CP_PACKET2 0x80000000 |
1126 | #define CP_PACKET2 0x80000000 |
1127 | #define PACKET2_PAD_SHIFT 0 |
1127 | #define PACKET2_PAD_SHIFT 0 |
1128 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
1128 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
1129 | #define CP_PACKET3 0xC0000000 |
1129 | #define CP_PACKET3 0xC0000000 |
1130 | #define PACKET3_IT_OPCODE_SHIFT 8 |
1130 | #define PACKET3_IT_OPCODE_SHIFT 8 |
1131 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
1131 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
1132 | #define PACKET3_COUNT_SHIFT 16 |
1132 | #define PACKET3_COUNT_SHIFT 16 |
1133 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
1133 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
1134 | /* PACKET3 op code */ |
1134 | /* PACKET3 op code */ |
1135 | #define PACKET3_NOP 0x10 |
1135 | #define PACKET3_NOP 0x10 |
1136 | #define PACKET3_3D_DRAW_VBUF 0x28 |
1136 | #define PACKET3_3D_DRAW_VBUF 0x28 |
1137 | #define PACKET3_3D_DRAW_IMMD 0x29 |
1137 | #define PACKET3_3D_DRAW_IMMD 0x29 |
1138 | #define PACKET3_3D_DRAW_INDX 0x2A |
1138 | #define PACKET3_3D_DRAW_INDX 0x2A |
1139 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
1139 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
1140 | #define PACKET3_INDX_BUFFER 0x33 |
1140 | #define PACKET3_INDX_BUFFER 0x33 |
1141 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
1141 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
1142 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
1142 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
1143 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
1143 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
1144 | #define PACKET3_BITBLT_MULTI 0x9B |
1144 | #define PACKET3_BITBLT_MULTI 0x9B |
1145 | 1145 | ||
1146 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
1146 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
1147 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
1147 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
1148 | REG_SET(PACKET0_COUNT, (n))) |
1148 | REG_SET(PACKET0_COUNT, (n))) |
1149 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
1149 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
1150 | #define PACKET3(op, n) (CP_PACKET3 | \ |
1150 | #define PACKET3(op, n) (CP_PACKET3 | \ |
1151 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
1151 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
1152 | REG_SET(PACKET3_COUNT, (n))) |
1152 | REG_SET(PACKET3_COUNT, (n))) |
1153 | 1153 | ||
1154 | #define PACKET_TYPE0 0 |
1154 | #define PACKET_TYPE0 0 |
1155 | #define PACKET_TYPE1 1 |
1155 | #define PACKET_TYPE1 1 |
1156 | #define PACKET_TYPE2 2 |
1156 | #define PACKET_TYPE2 2 |
1157 | #define PACKET_TYPE3 3 |
1157 | #define PACKET_TYPE3 3 |
1158 | 1158 | ||
1159 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
1159 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
1160 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
1160 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
1161 | #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
1161 | #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
1162 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
1162 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
1163 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
1163 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
1164 | 1164 | ||
1165 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1165 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1166 | { |
1166 | { |
1167 | #if DRM_DEBUG_CODE |
1167 | #if DRM_DEBUG_CODE |
1168 | if (rdev->cp.count_dw <= 0) { |
1168 | if (rdev->cp.count_dw <= 0) { |
1169 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
1169 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
1170 | } |
1170 | } |
1171 | #endif |
1171 | #endif |
1172 | rdev->cp.ring[rdev->cp.wptr++] = v; |
1172 | rdev->cp.ring[rdev->cp.wptr++] = v; |
1173 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
1173 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
1174 | rdev->cp.count_dw--; |
1174 | rdev->cp.count_dw--; |
1175 | rdev->cp.ring_free_dw--; |
1175 | rdev->cp.ring_free_dw--; |
1176 | } |
1176 | } |
1177 | 1177 | ||
1178 | 1178 | ||
1179 | /* |
1179 | /* |
1180 | * ASICs macro. |
1180 | * ASICs macro. |
1181 | */ |
1181 | */ |
1182 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
1182 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
1183 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1183 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1184 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
1184 | #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
1185 | #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
1185 | #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
1186 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1186 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1187 | #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
1187 | #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
1188 | #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
1188 | #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
1189 | #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
1189 | #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
1190 | #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
1190 | #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
1191 | #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
1191 | #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
1192 | #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
1192 | #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
1193 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1193 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1194 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1194 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1195 | #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
1195 | #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
1196 | #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
1196 | #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
1197 | #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
1197 | #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
1198 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1198 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1199 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1199 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1200 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
1200 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
1201 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1201 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1202 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
1202 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
1203 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
1203 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
1204 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1204 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1205 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1205 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1206 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1206 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1207 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1207 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1208 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1208 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1209 | 1209 | ||
1210 | 1210 | ||
1211 | #define DRM_UDELAY(d) udelay(d) |
1211 | #define DRM_UDELAY(d) udelay(d) |
1212 | 1212 | ||
1213 | resource_size_t |
1213 | resource_size_t |
1214 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1214 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1215 | resource_size_t |
1215 | resource_size_t |
1216 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1216 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1217 | 1217 | ||
1218 | 1218 | ||
1219 | #endif=>><>><>><>><>><>><>><>><>>>>>>>>>>>>>>>>>>><>><> |
1219 | #endif=>><>><>><>><>><>><>><>><>>>>>>>>>>>>>>>>>>><>><> |