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Rev 3764 | Rev 5078 | ||
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Line 300... | Line 300... | ||
300 | #define GUI_ACTIVE (1<<31) |
300 | #define GUI_ACTIVE (1<<31) |
301 | #define GRBM_STATUS2 0x8014 |
301 | #define GRBM_STATUS2 0x8014 |
302 | #define GRBM_SOFT_RESET 0x8020 |
302 | #define GRBM_SOFT_RESET 0x8020 |
303 | #define SOFT_RESET_CP (1<<0) |
303 | #define SOFT_RESET_CP (1<<0) |
Line -... | Line 304... | ||
- | 304 | ||
- | 305 | #define CG_THERMAL_CTRL 0x7F0 |
|
- | 306 | #define DIG_THERM_DPM(x) ((x) << 12) |
|
- | 307 | #define DIG_THERM_DPM_MASK 0x000FF000 |
|
304 | 308 | #define DIG_THERM_DPM_SHIFT 12 |
|
305 | #define CG_THERMAL_STATUS 0x7F4 |
309 | #define CG_THERMAL_STATUS 0x7F4 |
306 | #define ASIC_T(x) ((x) << 0) |
310 | #define ASIC_T(x) ((x) << 0) |
307 | #define ASIC_T_MASK 0x1FF |
311 | #define ASIC_T_MASK 0x1FF |
- | 312 | #define ASIC_T_SHIFT 0 |
|
- | 313 | #define CG_THERMAL_INT 0x7F8 |
|
- | 314 | #define DIG_THERM_INTH(x) ((x) << 8) |
|
- | 315 | #define DIG_THERM_INTH_MASK 0x0000FF00 |
|
- | 316 | #define DIG_THERM_INTH_SHIFT 8 |
|
- | 317 | #define DIG_THERM_INTL(x) ((x) << 16) |
|
- | 318 | #define DIG_THERM_INTL_MASK 0x00FF0000 |
|
- | 319 | #define DIG_THERM_INTL_SHIFT 16 |
|
- | 320 | #define THERM_INT_MASK_HIGH (1 << 24) |
|
- | 321 | #define THERM_INT_MASK_LOW (1 << 25) |
|
- | 322 | ||
Line 308... | Line 323... | ||
308 | #define ASIC_T_SHIFT 0 |
323 | #define RV770_CG_THERMAL_INT 0x734 |
309 | 324 | ||
310 | #define HDP_HOST_PATH_CNTL 0x2C00 |
325 | #define HDP_HOST_PATH_CNTL 0x2C00 |
311 | #define HDP_NONSURFACE_BASE 0x2C04 |
326 | #define HDP_NONSURFACE_BASE 0x2C04 |
Line 585... | Line 600... | ||
585 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) |
600 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) |
586 | #define VM_L2_STATUS 0x140C |
601 | #define VM_L2_STATUS 0x140C |
587 | #define L2_BUSY (1 << 0) |
602 | #define L2_BUSY (1 << 0) |
Line 588... | Line 603... | ||
588 | 603 | ||
- | 604 | #define WAIT_UNTIL 0x8040 |
|
589 | #define WAIT_UNTIL 0x8040 |
605 | #define WAIT_CP_DMA_IDLE_bit (1 << 8) |
590 | #define WAIT_2D_IDLE_bit (1 << 14) |
606 | #define WAIT_2D_IDLE_bit (1 << 14) |
591 | #define WAIT_3D_IDLE_bit (1 << 15) |
607 | #define WAIT_3D_IDLE_bit (1 << 15) |
592 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) |
608 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) |
Line 682... | Line 698... | ||
682 | #define RLC_MC_CNTL 0x3f44 |
698 | #define RLC_MC_CNTL 0x3f44 |
683 | #define RLC_UCODE_CNTL 0x3f48 |
699 | #define RLC_UCODE_CNTL 0x3f48 |
684 | #define RLC_UCODE_ADDR 0x3f2c |
700 | #define RLC_UCODE_ADDR 0x3f2c |
685 | #define RLC_UCODE_DATA 0x3f30 |
701 | #define RLC_UCODE_DATA 0x3f30 |
Line 686... | Line -... | ||
686 | - | ||
687 | /* new for TN */ |
- | |
688 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 |
- | |
689 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
- | |
690 | 702 | ||
- | 703 | #define SRBM_SOFT_RESET 0xe60 |
|
691 | #define SRBM_SOFT_RESET 0xe60 |
704 | # define SOFT_RESET_BIF (1 << 1) |
692 | # define SOFT_RESET_DMA (1 << 12) |
705 | # define SOFT_RESET_DMA (1 << 12) |
693 | # define SOFT_RESET_RLC (1 << 13) |
706 | # define SOFT_RESET_RLC (1 << 13) |
694 | # define SOFT_RESET_UVD (1 << 18) |
707 | # define SOFT_RESET_UVD (1 << 18) |
Line -... | Line 708... | ||
- | 708 | # define RV770_SOFT_RESET_DMA (1 << 20) |
|
- | 709 | ||
- | 710 | #define BIF_SCRATCH0 0x5438 |
|
- | 711 | ||
- | 712 | #define BUS_CNTL 0x5420 |
|
- | 713 | # define BIOS_ROM_DIS (1 << 1) |
|
695 | # define RV770_SOFT_RESET_DMA (1 << 20) |
714 | # define VGA_COHE_SPEC_TIMER_DIS (1 << 9) |
696 | 715 | ||
697 | #define CP_INT_CNTL 0xc124 |
716 | #define CP_INT_CNTL 0xc124 |
698 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
717 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
699 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
718 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
Line 919... | Line 938... | ||
919 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
938 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
920 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
939 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
921 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
940 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
922 | # define DTO_LOAD (1 << 31) |
941 | # define DTO_LOAD (1 << 31) |
923 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 |
942 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 |
- | 943 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) |
|
- | 944 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 |
|
- | 945 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 |
|
Line 924... | Line 946... | ||
924 | 946 | ||
925 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 |
947 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 |
926 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 |
948 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 |
927 | #define DCCG_AUDIO_DTO1_LOAD 0x052c |
949 | #define DCCG_AUDIO_DTO1_LOAD 0x052c |
Line 943... | Line 965... | ||
943 | # define DIG_MODE_TMDS_DVI 2 |
965 | # define DIG_MODE_TMDS_DVI 2 |
944 | # define DIG_MODE_TMDS_HDMI 3 |
966 | # define DIG_MODE_TMDS_HDMI 3 |
945 | # define DIG_MODE_SDVO 4 |
967 | # define DIG_MODE_SDVO 4 |
946 | #define DIG1_CNTL 0x79a0 |
968 | #define DIG1_CNTL 0x79a0 |
Line -... | Line 969... | ||
- | 969 | ||
- | 970 | #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc |
|
- | 971 | #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) |
|
- | 972 | #define SPEAKER_ALLOCATION_MASK (0x7f << 0) |
|
- | 973 | #define SPEAKER_ALLOCATION_SHIFT 0 |
|
- | 974 | #define HDMI_CONNECTION (1 << 16) |
|
- | 975 | #define DP_CONNECTION (1 << 17) |
|
- | 976 | ||
- | 977 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ |
|
- | 978 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ |
|
- | 979 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ |
|
- | 980 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ |
|
- | 981 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ |
|
- | 982 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ |
|
- | 983 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ |
|
- | 984 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ |
|
- | 985 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ |
|
- | 986 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ |
|
- | 987 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ |
|
- | 988 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ |
|
- | 989 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ |
|
- | 990 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ |
|
- | 991 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) |
|
- | 992 | /* max channels minus one. 7 = 8 channels */ |
|
- | 993 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) |
|
- | 994 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) |
|
- | 995 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ |
|
- | 996 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO |
|
- | 997 | * bit0 = 32 kHz |
|
- | 998 | * bit1 = 44.1 kHz |
|
- | 999 | * bit2 = 48 kHz |
|
- | 1000 | * bit3 = 88.2 kHz |
|
- | 1001 | * bit4 = 96 kHz |
|
- | 1002 | * bit5 = 176.4 kHz |
|
- | 1003 | * bit6 = 192 kHz |
|
- | 1004 | */ |
|
947 | 1005 | ||
948 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one |
1006 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one |
949 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly |
1007 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly |
950 | * different due to the new DIG blocks, but also have 2 instances. |
1008 | * different due to the new DIG blocks, but also have 2 instances. |
951 | * DCE 3.0 HDMI blocks are part of each DIG encoder. |
1009 | * DCE 3.0 HDMI blocks are part of each DIG encoder. |
Line 969... | Line 1027... | ||
969 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) |
1027 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) |
970 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) |
1028 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) |
971 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 |
1029 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 |
972 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) |
1030 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) |
973 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) |
1031 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) |
- | 1032 | # define HDMI0_AUDIO_DELAY_EN_MASK (3 << 4) |
|
974 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) |
1033 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) |
975 | # define HDMI0_AUDIO_TEST_EN (1 << 12) |
1034 | # define HDMI0_AUDIO_TEST_EN (1 << 12) |
976 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) |
1035 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) |
- | 1036 | # define HDMI0_AUDIO_PACKETS_PER_LINE_MASK (0x1f << 16) |
|
977 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) |
1037 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) |
978 | # define HDMI0_60958_CS_UPDATE (1 << 26) |
1038 | # define HDMI0_60958_CS_UPDATE (1 << 26) |
979 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) |
1039 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) |
980 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) |
1040 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) |
981 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c |
1041 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c |
982 | # define HDMI0_AUDIO_CRC_EN (1 << 0) |
1042 | # define HDMI0_AUDIO_CRC_EN (1 << 0) |
- | 1043 | #define DCE3_HDMI0_ACR_PACKET_CONTROL 0x740c |
|
983 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 |
1044 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 |
984 | # define HDMI0_NULL_SEND (1 << 0) |
1045 | # define HDMI0_NULL_SEND (1 << 0) |
985 | # define HDMI0_GC_SEND (1 << 4) |
1046 | # define HDMI0_GC_SEND (1 << 4) |
986 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ |
1047 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ |
987 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 |
1048 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 |
988 | # define HDMI0_AVI_INFO_SEND (1 << 0) |
1049 | # define HDMI0_AVI_INFO_SEND (1 << 0) |
989 | # define HDMI0_AVI_INFO_CONT (1 << 1) |
1050 | # define HDMI0_AVI_INFO_CONT (1 << 1) |
990 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) |
1051 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) |
991 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) |
1052 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) |
992 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ |
1053 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ |
993 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) |
1054 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) |
994 | # define HDMI0_MPEG_INFO_SEND (1 << 8) |
1055 | # define HDMI0_MPEG_INFO_SEND (1 << 8) |
995 | # define HDMI0_MPEG_INFO_CONT (1 << 9) |
1056 | # define HDMI0_MPEG_INFO_CONT (1 << 9) |
996 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) |
1057 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) |
997 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 |
1058 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 |
998 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) |
1059 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) |
- | 1060 | # define HDMI0_AVI_INFO_LINE_MASK (0x3f << 0) |
|
999 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
1061 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
- | 1062 | # define HDMI0_AUDIO_INFO_LINE_MASK (0x3f << 8) |
|
1000 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) |
1063 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) |
1001 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c |
1064 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c |
1002 | # define HDMI0_GENERIC0_SEND (1 << 0) |
1065 | # define HDMI0_GENERIC0_SEND (1 << 0) |
1003 | # define HDMI0_GENERIC0_CONT (1 << 1) |
1066 | # define HDMI0_GENERIC0_CONT (1 << 1) |
1004 | # define HDMI0_GENERIC0_UPDATE (1 << 2) |
1067 | # define HDMI0_GENERIC0_UPDATE (1 << 2) |
1005 | # define HDMI0_GENERIC1_SEND (1 << 4) |
1068 | # define HDMI0_GENERIC1_SEND (1 << 4) |
1006 | # define HDMI0_GENERIC1_CONT (1 << 5) |
1069 | # define HDMI0_GENERIC1_CONT (1 << 5) |
1007 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) |
1070 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) |
- | 1071 | # define HDMI0_GENERIC0_LINE_MASK (0x3f << 16) |
|
1008 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) |
1072 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) |
- | 1073 | # define HDMI0_GENERIC1_LINE_MASK (0x3f << 24) |
|
1009 | #define HDMI0_GC 0x7428 |
1074 | #define HDMI0_GC 0x7428 |
1010 | # define HDMI0_GC_AVMUTE (1 << 0) |
1075 | # define HDMI0_GC_AVMUTE (1 << 0) |
1011 | #define HDMI0_AVI_INFO0 0x7454 |
1076 | #define HDMI0_AVI_INFO0 0x7454 |
1012 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
1077 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
1013 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) |
1078 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) |
Line 1059... | Line 1124... | ||
1059 | #define HDMI0_GENERIC1_4 0x74a0 |
1124 | #define HDMI0_GENERIC1_4 0x74a0 |
1060 | #define HDMI0_GENERIC1_5 0x74a4 |
1125 | #define HDMI0_GENERIC1_5 0x74a4 |
1061 | #define HDMI0_GENERIC1_6 0x74a8 |
1126 | #define HDMI0_GENERIC1_6 0x74a8 |
1062 | #define HDMI0_ACR_32_0 0x74ac |
1127 | #define HDMI0_ACR_32_0 0x74ac |
1063 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) |
1128 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) |
- | 1129 | # define HDMI0_ACR_CTS_32_MASK (0xfffff << 12) |
|
1064 | #define HDMI0_ACR_32_1 0x74b0 |
1130 | #define HDMI0_ACR_32_1 0x74b0 |
1065 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) |
1131 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) |
- | 1132 | # define HDMI0_ACR_N_32_MASK (0xfffff << 0) |
|
1066 | #define HDMI0_ACR_44_0 0x74b4 |
1133 | #define HDMI0_ACR_44_0 0x74b4 |
1067 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) |
1134 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) |
- | 1135 | # define HDMI0_ACR_CTS_44_MASK (0xfffff << 12) |
|
1068 | #define HDMI0_ACR_44_1 0x74b8 |
1136 | #define HDMI0_ACR_44_1 0x74b8 |
1069 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) |
1137 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) |
- | 1138 | # define HDMI0_ACR_N_44_MASK (0xfffff << 0) |
|
1070 | #define HDMI0_ACR_48_0 0x74bc |
1139 | #define HDMI0_ACR_48_0 0x74bc |
1071 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) |
1140 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) |
- | 1141 | # define HDMI0_ACR_CTS_48_MASK (0xfffff << 12) |
|
1072 | #define HDMI0_ACR_48_1 0x74c0 |
1142 | #define HDMI0_ACR_48_1 0x74c0 |
1073 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) |
1143 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) |
- | 1144 | # define HDMI0_ACR_N_48_MASK (0xfffff << 0) |
|
1074 | #define HDMI0_ACR_STATUS_0 0x74c4 |
1145 | #define HDMI0_ACR_STATUS_0 0x74c4 |
1075 | #define HDMI0_ACR_STATUS_1 0x74c8 |
1146 | #define HDMI0_ACR_STATUS_1 0x74c8 |
1076 | #define HDMI0_AUDIO_INFO0 0x74cc |
1147 | #define HDMI0_AUDIO_INFO0 0x74cc |
1077 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
1148 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
1078 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) |
1149 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) |
Line 1088... | Line 1159... | ||
1088 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) |
1159 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) |
1089 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) |
1160 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) |
1090 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) |
1161 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) |
1091 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) |
1162 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) |
1092 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) |
1163 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) |
- | 1164 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK (0xf << 20) |
|
1093 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) |
1165 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) |
1094 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) |
1166 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) |
- | 1167 | # define HDMI0_60958_CS_CLOCK_ACCURACY_MASK (3 << 28) |
|
1095 | #define HDMI0_60958_1 0x74d8 |
1168 | #define HDMI0_60958_1 0x74d8 |
1096 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) |
1169 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) |
1097 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) |
1170 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) |
1098 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) |
1171 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) |
1099 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) |
1172 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) |
1100 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) |
1173 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) |
- | 1174 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK (0xf << 20) |
|
1101 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc |
1175 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc |
1102 | # define HDMI0_ACR_SEND (1 << 0) |
1176 | # define HDMI0_ACR_SEND (1 << 0) |
1103 | # define HDMI0_ACR_CONT (1 << 1) |
1177 | # define HDMI0_ACR_CONT (1 << 1) |
1104 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) |
1178 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) |
1105 | # define HDMI0_ACR_HW 0 |
1179 | # define HDMI0_ACR_HW 0 |
1106 | # define HDMI0_ACR_32 1 |
1180 | # define HDMI0_ACR_32 1 |
1107 | # define HDMI0_ACR_44 2 |
1181 | # define HDMI0_ACR_44 2 |
1108 | # define HDMI0_ACR_48 3 |
1182 | # define HDMI0_ACR_48 3 |
1109 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ |
1183 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ |
1110 | # define HDMI0_ACR_AUTO_SEND (1 << 12) |
1184 | # define HDMI0_ACR_AUTO_SEND (1 << 12) |
- | 1185 | #define DCE3_HDMI0_AUDIO_CRC_CONTROL 0x74dc |
|
1111 | #define HDMI0_RAMP_CONTROL0 0x74e0 |
1186 | #define HDMI0_RAMP_CONTROL0 0x74e0 |
1112 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) |
1187 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) |
1113 | #define HDMI0_RAMP_CONTROL1 0x74e4 |
1188 | #define HDMI0_RAMP_CONTROL1 0x74e4 |
1114 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) |
1189 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) |
1115 | #define HDMI0_RAMP_CONTROL2 0x74e8 |
1190 | #define HDMI0_RAMP_CONTROL2 0x74e8 |
Line 1146... | Line 1221... | ||
1146 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) |
1221 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) |
1147 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
1222 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
1148 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
1223 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
1149 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
1224 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
Line -... | Line 1225... | ||
- | 1225 | ||
- | 1226 | /* DCE3 FMT blocks */ |
|
- | 1227 | #define FMT_CONTROL 0x6700 |
|
- | 1228 | # define FMT_PIXEL_ENCODING (1 << 16) |
|
- | 1229 | /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ |
|
- | 1230 | #define FMT_BIT_DEPTH_CONTROL 0x6710 |
|
- | 1231 | # define FMT_TRUNCATE_EN (1 << 0) |
|
- | 1232 | # define FMT_TRUNCATE_DEPTH (1 << 4) |
|
- | 1233 | # define FMT_SPATIAL_DITHER_EN (1 << 8) |
|
- | 1234 | # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) |
|
- | 1235 | # define FMT_SPATIAL_DITHER_DEPTH (1 << 12) |
|
- | 1236 | # define FMT_FRAME_RANDOM_ENABLE (1 << 13) |
|
- | 1237 | # define FMT_RGB_RANDOM_ENABLE (1 << 14) |
|
- | 1238 | # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) |
|
- | 1239 | # define FMT_TEMPORAL_DITHER_EN (1 << 16) |
|
- | 1240 | # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) |
|
- | 1241 | # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) |
|
- | 1242 | # define FMT_TEMPORAL_LEVEL (1 << 24) |
|
- | 1243 | # define FMT_TEMPORAL_DITHER_RESET (1 << 25) |
|
- | 1244 | # define FMT_25FRC_SEL(x) ((x) << 26) |
|
- | 1245 | # define FMT_50FRC_SEL(x) ((x) << 28) |
|
- | 1246 | # define FMT_75FRC_SEL(x) ((x) << 30) |
|
- | 1247 | #define FMT_CLAMP_CONTROL 0x672c |
|
- | 1248 | # define FMT_CLAMP_DATA_EN (1 << 0) |
|
- | 1249 | # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) |
|
- | 1250 | # define FMT_CLAMP_6BPC 0 |
|
- | 1251 | # define FMT_CLAMP_8BPC 1 |
|
- | 1252 | # define FMT_CLAMP_10BPC 2 |
|
- | 1253 | ||
- | 1254 | /* Power management */ |
|
- | 1255 | #define CG_SPLL_FUNC_CNTL 0x600 |
|
- | 1256 | # define SPLL_RESET (1 << 0) |
|
- | 1257 | # define SPLL_SLEEP (1 << 1) |
|
- | 1258 | # define SPLL_REF_DIV(x) ((x) << 2) |
|
- | 1259 | # define SPLL_REF_DIV_MASK (7 << 2) |
|
- | 1260 | # define SPLL_FB_DIV(x) ((x) << 5) |
|
- | 1261 | # define SPLL_FB_DIV_MASK (0xff << 5) |
|
- | 1262 | # define SPLL_PULSEEN (1 << 13) |
|
- | 1263 | # define SPLL_PULSENUM(x) ((x) << 14) |
|
- | 1264 | # define SPLL_PULSENUM_MASK (3 << 14) |
|
- | 1265 | # define SPLL_SW_HILEN(x) ((x) << 16) |
|
- | 1266 | # define SPLL_SW_HILEN_MASK (0xf << 16) |
|
- | 1267 | # define SPLL_SW_LOLEN(x) ((x) << 20) |
|
- | 1268 | # define SPLL_SW_LOLEN_MASK (0xf << 20) |
|
- | 1269 | # define SPLL_DIVEN (1 << 24) |
|
- | 1270 | # define SPLL_BYPASS_EN (1 << 25) |
|
- | 1271 | # define SPLL_CHG_STATUS (1 << 29) |
|
- | 1272 | # define SPLL_CTLREQ (1 << 30) |
|
- | 1273 | # define SPLL_CTLACK (1 << 31) |
|
- | 1274 | ||
- | 1275 | #define GENERAL_PWRMGT 0x618 |
|
- | 1276 | # define GLOBAL_PWRMGT_EN (1 << 0) |
|
- | 1277 | # define STATIC_PM_EN (1 << 1) |
|
- | 1278 | # define MOBILE_SU (1 << 2) |
|
- | 1279 | # define THERMAL_PROTECTION_DIS (1 << 3) |
|
- | 1280 | # define THERMAL_PROTECTION_TYPE (1 << 4) |
|
- | 1281 | # define ENABLE_GEN2PCIE (1 << 5) |
|
- | 1282 | # define SW_GPIO_INDEX(x) ((x) << 6) |
|
- | 1283 | # define SW_GPIO_INDEX_MASK (3 << 6) |
|
- | 1284 | # define LOW_VOLT_D2_ACPI (1 << 8) |
|
- | 1285 | # define LOW_VOLT_D3_ACPI (1 << 9) |
|
- | 1286 | # define VOLT_PWRMGT_EN (1 << 10) |
|
- | 1287 | #define CG_TPC 0x61c |
|
- | 1288 | # define TPCC(x) ((x) << 0) |
|
- | 1289 | # define TPCC_MASK (0x7fffff << 0) |
|
- | 1290 | # define TPU(x) ((x) << 23) |
|
- | 1291 | # define TPU_MASK (0x1f << 23) |
|
- | 1292 | #define SCLK_PWRMGT_CNTL 0x620 |
|
- | 1293 | # define SCLK_PWRMGT_OFF (1 << 0) |
|
- | 1294 | # define SCLK_TURNOFF (1 << 1) |
|
- | 1295 | # define SPLL_TURNOFF (1 << 2) |
|
- | 1296 | # define SU_SCLK_USE_BCLK (1 << 3) |
|
- | 1297 | # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4) |
|
- | 1298 | # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5) |
|
- | 1299 | # define CLK_TURN_ON_STAGGER (1 << 6) |
|
- | 1300 | # define CLK_TURN_OFF_STAGGER (1 << 7) |
|
- | 1301 | # define FIR_FORCE_TREND_SEL (1 << 8) |
|
- | 1302 | # define FIR_TREND_MODE (1 << 9) |
|
- | 1303 | # define DYN_GFX_CLK_OFF_EN (1 << 10) |
|
- | 1304 | # define VDDC3D_TURNOFF_D1 (1 << 11) |
|
- | 1305 | # define VDDC3D_TURNOFF_D2 (1 << 12) |
|
- | 1306 | # define VDDC3D_TURNOFF_D3 (1 << 13) |
|
- | 1307 | # define SPLL_TURNOFF_D2 (1 << 14) |
|
- | 1308 | # define SCLK_LOW_D1 (1 << 15) |
|
- | 1309 | # define DYN_GFX_CLK_OFF_MC_EN (1 << 16) |
|
- | 1310 | #define MCLK_PWRMGT_CNTL 0x624 |
|
- | 1311 | # define MPLL_PWRMGT_OFF (1 << 0) |
|
- | 1312 | # define YCLK_TURNOFF (1 << 1) |
|
- | 1313 | # define MPLL_TURNOFF (1 << 2) |
|
- | 1314 | # define SU_MCLK_USE_BCLK (1 << 3) |
|
- | 1315 | # define DLL_READY (1 << 4) |
|
- | 1316 | # define MC_BUSY (1 << 5) |
|
- | 1317 | # define MC_INT_CNTL (1 << 7) |
|
- | 1318 | # define MRDCKA_SLEEP (1 << 8) |
|
- | 1319 | # define MRDCKB_SLEEP (1 << 9) |
|
- | 1320 | # define MRDCKC_SLEEP (1 << 10) |
|
- | 1321 | # define MRDCKD_SLEEP (1 << 11) |
|
- | 1322 | # define MRDCKE_SLEEP (1 << 12) |
|
- | 1323 | # define MRDCKF_SLEEP (1 << 13) |
|
- | 1324 | # define MRDCKG_SLEEP (1 << 14) |
|
- | 1325 | # define MRDCKH_SLEEP (1 << 15) |
|
- | 1326 | # define MRDCKA_RESET (1 << 16) |
|
- | 1327 | # define MRDCKB_RESET (1 << 17) |
|
- | 1328 | # define MRDCKC_RESET (1 << 18) |
|
- | 1329 | # define MRDCKD_RESET (1 << 19) |
|
- | 1330 | # define MRDCKE_RESET (1 << 20) |
|
- | 1331 | # define MRDCKF_RESET (1 << 21) |
|
- | 1332 | # define MRDCKG_RESET (1 << 22) |
|
- | 1333 | # define MRDCKH_RESET (1 << 23) |
|
- | 1334 | # define DLL_READY_READ (1 << 24) |
|
- | 1335 | # define USE_DISPLAY_GAP (1 << 25) |
|
- | 1336 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
|
- | 1337 | # define USE_DISPLAY_GAP_CTXSW (1 << 27) |
|
- | 1338 | # define MPLL_TURNOFF_D2 (1 << 28) |
|
- | 1339 | # define USE_DISPLAY_URGENT_CTXSW (1 << 29) |
|
- | 1340 | ||
- | 1341 | #define MPLL_TIME 0x634 |
|
- | 1342 | # define MPLL_LOCK_TIME(x) ((x) << 0) |
|
- | 1343 | # define MPLL_LOCK_TIME_MASK (0xffff << 0) |
|
- | 1344 | # define MPLL_RESET_TIME(x) ((x) << 16) |
|
- | 1345 | # define MPLL_RESET_TIME_MASK (0xffff << 16) |
|
- | 1346 | ||
- | 1347 | #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 |
|
- | 1348 | # define STEP_0_SPLL_POST_DIV(x) ((x) << 0) |
|
- | 1349 | # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0) |
|
- | 1350 | # define STEP_0_SPLL_FB_DIV(x) ((x) << 8) |
|
- | 1351 | # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) |
|
- | 1352 | # define STEP_0_SPLL_REF_DIV(x) ((x) << 16) |
|
- | 1353 | # define STEP_0_SPLL_REF_DIV_MASK (7 << 16) |
|
- | 1354 | # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19) |
|
- | 1355 | # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19) |
|
- | 1356 | #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c |
|
- | 1357 | # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0) |
|
- | 1358 | # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0) |
|
- | 1359 | # define STEP_0_POST_DIV_EN (1 << 9) |
|
- | 1360 | # define STEP_0_SPLL_STEP_ENABLE (1 << 30) |
|
- | 1361 | # define STEP_0_SPLL_ENTRY_VALID (1 << 31) |
|
- | 1362 | ||
- | 1363 | #define VID_RT 0x6f8 |
|
- | 1364 | # define VID_CRT(x) ((x) << 0) |
|
- | 1365 | # define VID_CRT_MASK (0x1fff << 0) |
|
- | 1366 | # define VID_CRTU(x) ((x) << 13) |
|
- | 1367 | # define VID_CRTU_MASK (7 << 13) |
|
- | 1368 | # define SSTU(x) ((x) << 16) |
|
- | 1369 | # define SSTU_MASK (7 << 16) |
|
- | 1370 | #define CTXSW_PROFILE_INDEX 0x6fc |
|
- | 1371 | # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0) |
|
- | 1372 | # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0) |
|
- | 1373 | # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0 |
|
- | 1374 | # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2) |
|
- | 1375 | # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2) |
|
- | 1376 | # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2 |
|
- | 1377 | # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4) |
|
- | 1378 | # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4) |
|
- | 1379 | # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4 |
|
- | 1380 | # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9) |
|
- | 1381 | # define CTXSW_FREQ_STATE_ENABLE (1 << 10) |
|
- | 1382 | # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11) |
|
- | 1383 | # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12) |
|
- | 1384 | ||
- | 1385 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c |
|
- | 1386 | # define TARGET_PROFILE_INDEX_MASK (3 << 0) |
|
- | 1387 | # define TARGET_PROFILE_INDEX_SHIFT 0 |
|
- | 1388 | # define CURRENT_PROFILE_INDEX_MASK (3 << 2) |
|
- | 1389 | # define CURRENT_PROFILE_INDEX_SHIFT 2 |
|
- | 1390 | # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) |
|
- | 1391 | # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) |
|
- | 1392 | # define DYN_PWR_ENTER_INDEX_SHIFT 4 |
|
- | 1393 | # define CURR_MCLK_INDEX_MASK (3 << 6) |
|
- | 1394 | # define CURR_MCLK_INDEX_SHIFT 6 |
|
- | 1395 | # define CURR_SCLK_INDEX_MASK (0x1f << 8) |
|
- | 1396 | # define CURR_SCLK_INDEX_SHIFT 8 |
|
- | 1397 | # define CURR_VID_INDEX_MASK (3 << 13) |
|
- | 1398 | # define CURR_VID_INDEX_SHIFT 13 |
|
- | 1399 | ||
- | 1400 | #define LOWER_GPIO_ENABLE 0x710 |
|
- | 1401 | #define UPPER_GPIO_ENABLE 0x714 |
|
- | 1402 | #define CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
|
- | 1403 | ||
- | 1404 | #define VID_UPPER_GPIO_CNTL 0x740 |
|
- | 1405 | #define CG_CTX_CGTT3D_R 0x744 |
|
- | 1406 | # define PHC(x) ((x) << 0) |
|
- | 1407 | # define PHC_MASK (0x1ff << 0) |
|
- | 1408 | # define SDC(x) ((x) << 9) |
|
- | 1409 | # define SDC_MASK (0x3fff << 9) |
|
- | 1410 | #define CG_VDDC3D_OOR 0x748 |
|
- | 1411 | # define SU(x) ((x) << 23) |
|
- | 1412 | # define SU_MASK (0xf << 23) |
|
- | 1413 | #define CG_FTV 0x74c |
|
- | 1414 | #define CG_FFCT_0 0x750 |
|
- | 1415 | # define UTC_0(x) ((x) << 0) |
|
- | 1416 | # define UTC_0_MASK (0x3ff << 0) |
|
- | 1417 | # define DTC_0(x) ((x) << 10) |
|
- | 1418 | # define DTC_0_MASK (0x3ff << 10) |
|
- | 1419 | ||
- | 1420 | #define CG_BSP 0x78c |
|
- | 1421 | # define BSP(x) ((x) << 0) |
|
- | 1422 | # define BSP_MASK (0xffff << 0) |
|
- | 1423 | # define BSU(x) ((x) << 16) |
|
- | 1424 | # define BSU_MASK (0xf << 16) |
|
- | 1425 | #define CG_RT 0x790 |
|
- | 1426 | # define FLS(x) ((x) << 0) |
|
- | 1427 | # define FLS_MASK (0xffff << 0) |
|
- | 1428 | # define FMS(x) ((x) << 16) |
|
- | 1429 | # define FMS_MASK (0xffff << 16) |
|
- | 1430 | #define CG_LT 0x794 |
|
- | 1431 | # define FHS(x) ((x) << 0) |
|
- | 1432 | # define FHS_MASK (0xffff << 0) |
|
- | 1433 | #define CG_GIT 0x798 |
|
- | 1434 | # define CG_GICST(x) ((x) << 0) |
|
- | 1435 | # define CG_GICST_MASK (0xffff << 0) |
|
- | 1436 | # define CG_GIPOT(x) ((x) << 16) |
|
- | 1437 | # define CG_GIPOT_MASK (0xffff << 16) |
|
- | 1438 | ||
- | 1439 | #define CG_SSP 0x7a8 |
|
- | 1440 | # define CG_SST(x) ((x) << 0) |
|
- | 1441 | # define CG_SST_MASK (0xffff << 0) |
|
- | 1442 | # define CG_SSTU(x) ((x) << 16) |
|
- | 1443 | # define CG_SSTU_MASK (0xf << 16) |
|
- | 1444 | ||
- | 1445 | #define CG_RLC_REQ_AND_RSP 0x7c4 |
|
- | 1446 | # define RLC_CG_REQ_TYPE_MASK 0xf |
|
- | 1447 | # define RLC_CG_REQ_TYPE_SHIFT 0 |
|
- | 1448 | # define CG_RLC_RSP_TYPE_MASK 0xf0 |
|
- | 1449 | # define CG_RLC_RSP_TYPE_SHIFT 4 |
|
- | 1450 | ||
- | 1451 | #define CG_FC_T 0x7cc |
|
- | 1452 | # define FC_T(x) ((x) << 0) |
|
- | 1453 | # define FC_T_MASK (0xffff << 0) |
|
- | 1454 | # define FC_TU(x) ((x) << 16) |
|
- | 1455 | # define FC_TU_MASK (0x1f << 16) |
|
- | 1456 | ||
- | 1457 | #define GPIOPAD_MASK 0x1798 |
|
- | 1458 | #define GPIOPAD_A 0x179c |
|
- | 1459 | #define GPIOPAD_EN 0x17a0 |
|
- | 1460 | ||
- | 1461 | #define GRBM_PWR_CNTL 0x800c |
|
- | 1462 | # define REQ_TYPE_MASK 0xf |
|
- | 1463 | # define REQ_TYPE_SHIFT 0 |
|
- | 1464 | # define RSP_TYPE_MASK 0xf0 |
|
- | 1465 | # define RSP_TYPE_SHIFT 4 |
|
1150 | 1466 | ||
1151 | /* |
1467 | /* |
1152 | * UVD |
1468 | * UVD |
1153 | */ |
1469 | */ |
1154 | #define UVD_SEMA_ADDR_LOW 0xef00 |
1470 | #define UVD_SEMA_ADDR_LOW 0xef00 |
Line 1257... | Line 1573... | ||
1257 | * 5. DST_ADDR_HI [7:0] |
1573 | * 5. DST_ADDR_HI [7:0] |
1258 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
1574 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
1259 | */ |
1575 | */ |
1260 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
1576 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
1261 | /* COMMAND */ |
1577 | /* COMMAND */ |
1262 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) |
1578 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) |
1263 | /* 0 - none |
1579 | /* 0 - none |
1264 | * 1 - 8 in 16 |
1580 | * 1 - 8 in 16 |
1265 | * 2 - 8 in 32 |
1581 | * 2 - 8 in 32 |
1266 | * 3 - 8 in 64 |
1582 | * 3 - 8 in 64 |
1267 | */ |
1583 | */ |
Line 1279... | Line 1595... | ||
1279 | /* 0 - memory |
1595 | /* 0 - memory |
1280 | * 1 - register |
1596 | * 1 - register |
1281 | */ |
1597 | */ |
1282 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
1598 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
1283 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
1599 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
- | 1600 | #define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */ |
|
1284 | #define PACKET3_SURFACE_SYNC 0x43 |
1601 | #define PACKET3_SURFACE_SYNC 0x43 |
1285 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
1602 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
- | 1603 | # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ |
|
1286 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
1604 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
1287 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
1605 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
1288 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
1606 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
1289 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
1607 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
1290 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
1608 | # define PACKET3_SH_ACTION_ENA (1 << 27) |