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Rev 3192 | Rev 3764 | ||
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Line 180... | Line 180... | ||
180 | #define CP_BUSY_STAT 0x867C |
180 | #define CP_BUSY_STAT 0x867C |
181 | #define CP_STAT 0x8680 |
181 | #define CP_STAT 0x8680 |
182 | #define CP_COHER_BASE 0x85F8 |
182 | #define CP_COHER_BASE 0x85F8 |
183 | #define CP_DEBUG 0xC1FC |
183 | #define CP_DEBUG 0xC1FC |
184 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
184 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
- | 185 | #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) |
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- | 186 | #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) |
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185 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) |
187 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) |
186 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) |
188 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) |
187 | #define CP_ME_RAM_DATA 0xC160 |
189 | #define CP_ME_RAM_DATA 0xC160 |
188 | #define CP_ME_RAM_RADDR 0xC158 |
190 | #define CP_ME_RAM_RADDR 0xC158 |
189 | #define CP_ME_RAM_WADDR 0xC15C |
191 | #define CP_ME_RAM_WADDR 0xC15C |
Line 687... | Line 689... | ||
687 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
689 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
Line 688... | Line 690... | ||
688 | 690 | ||
689 | #define SRBM_SOFT_RESET 0xe60 |
691 | #define SRBM_SOFT_RESET 0xe60 |
690 | # define SOFT_RESET_DMA (1 << 12) |
692 | # define SOFT_RESET_DMA (1 << 12) |
- | 693 | # define SOFT_RESET_RLC (1 << 13) |
|
691 | # define SOFT_RESET_RLC (1 << 13) |
694 | # define SOFT_RESET_UVD (1 << 18) |
Line 692... | Line 695... | ||
692 | # define RV770_SOFT_RESET_DMA (1 << 20) |
695 | # define RV770_SOFT_RESET_DMA (1 << 20) |
693 | 696 | ||
694 | #define CP_INT_CNTL 0xc124 |
697 | #define CP_INT_CNTL 0xc124 |
Line 905... | Line 908... | ||
905 | # define MM_WR_TO_CFG_EN (1 << 3) |
908 | # define MM_WR_TO_CFG_EN (1 << 3) |
906 | #define LINK_CNTL2 0x88 /* F0 */ |
909 | #define LINK_CNTL2 0x88 /* F0 */ |
907 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
910 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
908 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
911 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
Line -... | Line 912... | ||
- | 912 | ||
- | 913 | /* Audio clocks DCE 2.0/3.0 */ |
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- | 914 | #define AUDIO_DTO 0x7340 |
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- | 915 | # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) |
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- | 916 | # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16) |
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909 | 917 | ||
910 | /* Audio clocks */ |
918 | /* Audio clocks DCE 3.2 */ |
911 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
919 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
912 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
920 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
913 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
921 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
914 | # define DTO_LOAD (1 << 31) |
922 | # define DTO_LOAD (1 << 31) |
Line 1139... | Line 1147... | ||
1139 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
1147 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
1140 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
1148 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
1141 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
1149 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
Line 1142... | Line 1150... | ||
1142 | 1150 | ||
- | 1151 | /* |
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- | 1152 | * UVD |
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- | 1153 | */ |
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- | 1154 | #define UVD_SEMA_ADDR_LOW 0xef00 |
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- | 1155 | #define UVD_SEMA_ADDR_HIGH 0xef04 |
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- | 1156 | #define UVD_SEMA_CMD 0xef08 |
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- | 1157 | ||
- | 1158 | #define UVD_GPCOM_VCPU_CMD 0xef0c |
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- | 1159 | #define UVD_GPCOM_VCPU_DATA0 0xef10 |
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- | 1160 | #define UVD_GPCOM_VCPU_DATA1 0xef14 |
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- | 1161 | #define UVD_ENGINE_CNTL 0xef18 |
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- | 1162 | ||
- | 1163 | #define UVD_SEMA_CNTL 0xf400 |
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- | 1164 | #define UVD_RB_ARB_CTRL 0xf480 |
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- | 1165 | ||
- | 1166 | #define UVD_LMI_EXT40_ADDR 0xf498 |
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- | 1167 | #define UVD_CGC_GATE 0xf4a8 |
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- | 1168 | #define UVD_LMI_CTRL2 0xf4f4 |
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- | 1169 | #define UVD_MASTINT_EN 0xf500 |
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- | 1170 | #define UVD_LMI_ADDR_EXT 0xf594 |
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- | 1171 | #define UVD_LMI_CTRL 0xf598 |
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- | 1172 | #define UVD_LMI_SWAP_CNTL 0xf5b4 |
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- | 1173 | #define UVD_MP_SWAP_CNTL 0xf5bC |
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- | 1174 | #define UVD_MPC_CNTL 0xf5dC |
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- | 1175 | #define UVD_MPC_SET_MUXA0 0xf5e4 |
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- | 1176 | #define UVD_MPC_SET_MUXA1 0xf5e8 |
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- | 1177 | #define UVD_MPC_SET_MUXB0 0xf5eC |
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- | 1178 | #define UVD_MPC_SET_MUXB1 0xf5f0 |
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- | 1179 | #define UVD_MPC_SET_MUX 0xf5f4 |
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- | 1180 | #define UVD_MPC_SET_ALU 0xf5f8 |
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- | 1181 | ||
- | 1182 | #define UVD_VCPU_CNTL 0xf660 |
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- | 1183 | #define UVD_SOFT_RESET 0xf680 |
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- | 1184 | #define RBC_SOFT_RESET (1<<0) |
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- | 1185 | #define LBSI_SOFT_RESET (1<<1) |
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- | 1186 | #define LMI_SOFT_RESET (1<<2) |
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- | 1187 | #define VCPU_SOFT_RESET (1<<3) |
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- | 1188 | #define CSM_SOFT_RESET (1<<5) |
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- | 1189 | #define CXW_SOFT_RESET (1<<6) |
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- | 1190 | #define TAP_SOFT_RESET (1<<7) |
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- | 1191 | #define LMI_UMC_SOFT_RESET (1<<13) |
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- | 1192 | #define UVD_RBC_IB_BASE 0xf684 |
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- | 1193 | #define UVD_RBC_IB_SIZE 0xf688 |
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- | 1194 | #define UVD_RBC_RB_BASE 0xf68c |
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- | 1195 | #define UVD_RBC_RB_RPTR 0xf690 |
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- | 1196 | #define UVD_RBC_RB_WPTR 0xf694 |
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- | 1197 | #define UVD_RBC_RB_WPTR_CNTL 0xf698 |
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- | 1198 | ||
- | 1199 | #define UVD_STATUS 0xf6bc |
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- | 1200 | ||
- | 1201 | #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0 |
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- | 1202 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4 |
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- | 1203 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8 |
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- | 1204 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc |
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- | 1205 | ||
- | 1206 | #define UVD_RBC_RB_CNTL 0xf6a4 |
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- | 1207 | #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 |
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- | 1208 | ||
- | 1209 | #define UVD_CONTEXT_ID 0xf6f4 |
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- | 1210 | ||
- | 1211 | # define UPLL_CTLREQ_MASK 0x00000008 |
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- | 1212 | # define UPLL_CTLACK_MASK 0x40000000 |
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- | 1213 | # define UPLL_CTLACK2_MASK 0x80000000 |
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- | 1214 | ||
1143 | /* |
1215 | /* |
1144 | * PM4 |
1216 | * PM4 |
1145 | */ |
- | |
1146 | #define PACKET_TYPE0 0 |
- | |
1147 | #define PACKET_TYPE1 1 |
- | |
1148 | #define PACKET_TYPE2 2 |
- | |
1149 | #define PACKET_TYPE3 3 |
- | |
1150 | - | ||
1151 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
- | |
1152 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
- | |
1153 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
- | |
1154 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
1217 | */ |
1155 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
1218 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
1156 | (((reg) >> 2) & 0xFFFF) | \ |
1219 | (((reg) >> 2) & 0xFFFF) | \ |
1157 | ((n) & 0x3FFF) << 16) |
1220 | ((n) & 0x3FFF) << 16) |
1158 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
1221 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
1159 | (((op) & 0xFF) << 8) | \ |
1222 | (((op) & 0xFF) << 8) | \ |
Line 1160... | Line 1223... | ||
1160 | ((n) & 0x3FFF) << 16) |
1223 | ((n) & 0x3FFF) << 16) |
1161 | 1224 | ||
Line 1277... | Line 1340... | ||
1277 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
1340 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
1278 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
1341 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
1279 | #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ |
1342 | #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ |
1280 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
1343 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
Line -... | Line 1344... | ||
- | 1344 | ||
- | 1345 | #define R_000011_K8_FB_LOCATION 0x11 |
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- | 1346 | #define R_000012_MC_MISC_UMA_CNTL 0x12 |
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- | 1347 | #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) |
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- | 1348 | #define R_0028F8_MC_INDEX 0x28F8 |
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- | 1349 | #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) |
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- | 1350 | #define C_0028F8_MC_IND_ADDR 0xFFFFFE00 |
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- | 1351 | #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9) |
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Line 1281... | Line 1352... | ||
1281 | 1352 | #define R_0028FC_MC_DATA 0x28FC |
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1282 | 1353 | ||
1283 | #define R_008020_GRBM_SOFT_RESET 0x8020 |
1354 | #define R_008020_GRBM_SOFT_RESET 0x8020 |
1284 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) |
1355 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) |
Line 1326... | Line 1397... | ||
1326 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) |
1397 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) |
1327 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) |
1398 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) |
1328 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) |
1399 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) |
1329 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) |
1400 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) |
1330 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) |
1401 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) |
- | 1402 | #define G_008010_TA_BUSY(x) (((x) >> 14) & 1) |
|
1331 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) |
1403 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) |
1332 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) |
1404 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) |
1333 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) |
1405 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) |
1334 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) |
1406 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) |
1335 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) |
1407 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) |
Line 1393... | Line 1465... | ||
1393 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) |
1465 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) |
1394 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) |
1466 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) |
1395 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) |
1467 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) |
1396 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) |
1468 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) |
1397 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) |
1469 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) |
- | 1470 | #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) |
|
1398 | #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) |
1471 | #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) |
1399 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 |
1472 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 |
1400 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) |
1473 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) |
1401 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) |
1474 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) |
1402 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) |
1475 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) |