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Rev 2997 Rev 3192
Line 588... Line 588...
588 
#define         WAIT_2D_IDLE_bit                                (1 << 14)
 588 
#define         WAIT_2D_IDLE_bit                                (1 << 14)
589 
#define         WAIT_3D_IDLE_bit                                (1 << 15)
 589 
#define         WAIT_3D_IDLE_bit                                (1 << 15)
590 
#define         WAIT_2D_IDLECLEAN_bit                           (1 << 16)
 590 
#define         WAIT_2D_IDLECLEAN_bit                           (1 << 16)
591 
#define         WAIT_3D_IDLECLEAN_bit                           (1 << 17)
 591 
#define         WAIT_3D_IDLECLEAN_bit                           (1 << 17)
Line -... Line 592...
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 592 
 
- 
 
 593 
/* async DMA */
- 
 
 594 
#define DMA_TILING_CONFIG                                 0x3ec4
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 595 
#define DMA_CONFIG                                        0x3e4c
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 596 
 
- 
 
 597 
#define DMA_RB_CNTL                                       0xd000
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 598 
#       define DMA_RB_ENABLE                              (1 << 0)
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 599 
#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
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 600 
#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
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 601 
#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
- 
 
 602 
#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
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 603 
#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
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 604 
#define DMA_RB_BASE                                       0xd004
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 605 
#define DMA_RB_RPTR                                       0xd008
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 606 
#define DMA_RB_WPTR                                       0xd00c
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 607 
 
- 
 
 608 
#define DMA_RB_RPTR_ADDR_HI                               0xd01c
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 609 
#define DMA_RB_RPTR_ADDR_LO                               0xd020
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 610 
 
- 
 
 611 
#define DMA_IB_CNTL                                       0xd024
- 
 
 612 
#       define DMA_IB_ENABLE                              (1 << 0)
- 
 
 613 
#       define DMA_IB_SWAP_ENABLE                         (1 << 4)
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 614 
#define DMA_IB_RPTR                                       0xd028
- 
 
 615 
#define DMA_CNTL                                          0xd02c
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 616 
#       define TRAP_ENABLE                                (1 << 0)
- 
 
 617 
#       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
- 
 
 618 
#       define SEM_WAIT_INT_ENABLE                        (1 << 2)
- 
 
 619 
#       define DATA_SWAP_ENABLE                           (1 << 3)
- 
 
 620 
#       define FENCE_SWAP_ENABLE                          (1 << 4)
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 621 
#       define CTXEMPTY_INT_ENABLE                        (1 << 28)
- 
 
 622 
#define DMA_STATUS_REG                                    0xd034
- 
 
 623 
#       define DMA_IDLE                                   (1 << 0)
- 
 
 624 
#define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0xd044
- 
 
 625 
#define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0xd048
- 
 
 626 
#define DMA_MODE                                          0xd0bc
- 
 
 627 
 
- 
 
 628 
/* async DMA packets */
- 
 
 629 
#define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
- 
 
 630 
					 (((t) & 0x1) << 23) |		\
- 
 
 631 
					 (((s) & 0x1) << 22) |		\
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 632 
					 (((n) & 0xFFFF) << 0))
- 
 
 633 
/* async DMA Packet types */
- 
 
 634 
#define	DMA_PACKET_WRITE				  0x2
- 
 
 635 
#define	DMA_PACKET_COPY					  0x3
- 
 
 636 
#define	DMA_PACKET_INDIRECT_BUFFER			  0x4
- 
 
 637 
#define	DMA_PACKET_SEMAPHORE				  0x5
- 
 
 638 
#define	DMA_PACKET_FENCE				  0x6
- 
 
 639 
#define	DMA_PACKET_TRAP					  0x7
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 640 
#define	DMA_PACKET_CONSTANT_FILL			  0xd /* 7xx only */
- 
 
 641 
#define	DMA_PACKET_NOP					  0xf
592 
 
 642 
 
593 
#define IH_RB_CNTL                                        0x3e00
 643 
#define IH_RB_CNTL                                        0x3e00
594 
#       define IH_RB_ENABLE                               (1 << 0)
 644 
#       define IH_RB_ENABLE                               (1 << 0)
595 
#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
 645 
#       define IH_RB_SIZE(x)                              ((x) << 1) /* log2 */
596 
#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
 646 
#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
597 
#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
 647 
#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
598 
#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
 648 
#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
599 
#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
 649 
#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
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635 
/* new for TN */
 685 
/* new for TN */
636 
#define TN_RLC_SAVE_AND_RESTORE_BASE                      0x3f10
 686 
#define TN_RLC_SAVE_AND_RESTORE_BASE                      0x3f10
637 
#define TN_RLC_CLEAR_STATE_RESTORE_BASE                   0x3f20
 687 
#define TN_RLC_CLEAR_STATE_RESTORE_BASE                   0x3f20
Line 638... Line 688...
638 
 
 688 
 
- 
 
 689 
#define SRBM_SOFT_RESET                                   0xe60
639 
#define SRBM_SOFT_RESET                                   0xe60
 690 
#       define SOFT_RESET_DMA                             (1 << 12)
- 
 
 691 
#       define SOFT_RESET_RLC                             (1 << 13)
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640 
#       define SOFT_RESET_RLC                             (1 << 13)
 692 
#       define RV770_SOFT_RESET_DMA                       (1 << 20)
641 
 
 693 
 
642 
#define CP_INT_CNTL                                       0xc124
 694 
#define CP_INT_CNTL                                       0xc124
643 
#       define CNTX_BUSY_INT_ENABLE                       (1 << 19)
 695 
#       define CNTX_BUSY_INT_ENABLE                       (1 << 19)
Line 1132... Line 1184...
1132 
#define	PACKET3_MPEG_INDEX				0x3A
 1184 
#define	PACKET3_MPEG_INDEX				0x3A
1133 
#define	PACKET3_COPY_DW					0x3B
 1185 
#define	PACKET3_COPY_DW					0x3B
1134 
#define	PACKET3_WAIT_REG_MEM				0x3C
 1186 
#define	PACKET3_WAIT_REG_MEM				0x3C
1135 
#define	PACKET3_MEM_WRITE				0x3D
 1187 
#define	PACKET3_MEM_WRITE				0x3D
1136 
#define	PACKET3_INDIRECT_BUFFER				0x32
 1188 
#define	PACKET3_INDIRECT_BUFFER				0x32
- 
 
 1189 
#define	PACKET3_CP_DMA					0x41
- 
 
 1190 
/* 1. header
- 
 
 1191 
 * 2. SRC_ADDR_LO [31:0]
- 
 
 1192 
 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]
- 
 
 1193 
 * 4. DST_ADDR_LO [31:0]
- 
 
 1194 
 * 5. DST_ADDR_HI [7:0]
- 
 
 1195 
 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
- 
 
 1196 
 */
- 
 
 1197 
#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
- 
 
 1198 
/* COMMAND */
- 
 
 1199 
#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
- 
 
 1200 
                /* 0 - none
- 
 
 1201 
		 * 1 - 8 in 16
- 
 
 1202 
		 * 2 - 8 in 32
- 
 
 1203 
		 * 3 - 8 in 64
- 
 
 1204 
		 */
- 
 
 1205 
#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
- 
 
 1206 
                /* 0 - none
- 
 
 1207 
		 * 1 - 8 in 16
- 
 
 1208 
		 * 2 - 8 in 32
- 
 
 1209 
		 * 3 - 8 in 64
- 
 
 1210 
		 */
- 
 
 1211 
#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
- 
 
 1212 
                /* 0 - memory
- 
 
 1213 
		 * 1 - register
- 
 
 1214 
		 */
- 
 
 1215 
#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
- 
 
 1216 
                /* 0 - memory
- 
 
 1217 
		 * 1 - register
- 
 
 1218 
		 */
- 
 
 1219 
#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
- 
 
 1220 
#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
1137 
#define	PACKET3_SURFACE_SYNC				0x43
 1221 
#define	PACKET3_SURFACE_SYNC				0x43
1138 
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 1222 
#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
1139 
#              define PACKET3_TC_ACTION_ENA        (1 << 23)
 1223 
#              define PACKET3_TC_ACTION_ENA        (1 << 23)
1140 
#              define PACKET3_VC_ACTION_ENA        (1 << 24)
 1224 
#              define PACKET3_VC_ACTION_ENA        (1 << 24)
1141 
#              define PACKET3_CB_ACTION_ENA        (1 << 25)
 1225 
#              define PACKET3_CB_ACTION_ENA        (1 << 25)