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Rev 1430 | Rev 1963 | ||
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Line 49... | Line 49... | ||
49 | #define PTE_SYSTEM (1 << 1) |
49 | #define PTE_SYSTEM (1 << 1) |
50 | #define PTE_SNOOPED (1 << 2) |
50 | #define PTE_SNOOPED (1 << 2) |
51 | #define PTE_READABLE (1 << 5) |
51 | #define PTE_READABLE (1 << 5) |
52 | #define PTE_WRITEABLE (1 << 6) |
52 | #define PTE_WRITEABLE (1 << 6) |
Line -... | Line 53... | ||
- | 53 | ||
- | 54 | /* tiling bits */ |
|
- | 55 | #define ARRAY_LINEAR_GENERAL 0x00000000 |
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- | 56 | #define ARRAY_LINEAR_ALIGNED 0x00000001 |
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- | 57 | #define ARRAY_1D_TILED_THIN1 0x00000002 |
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- | 58 | #define ARRAY_2D_TILED_THIN1 0x00000004 |
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53 | 59 | ||
54 | /* Registers */ |
60 | /* Registers */ |
55 | #define ARB_POP 0x2418 |
61 | #define ARB_POP 0x2418 |
56 | #define ENABLE_TC128 (1 << 30) |
62 | #define ENABLE_TC128 (1 << 30) |
Line 75... | Line 81... | ||
75 | #define CB_COLOR0_INFO 0x280a0 |
81 | #define CB_COLOR0_INFO 0x280a0 |
76 | #define CB_COLOR0_TILE 0x280c0 |
82 | #define CB_COLOR0_TILE 0x280c0 |
77 | #define CB_COLOR0_FRAG 0x280e0 |
83 | #define CB_COLOR0_FRAG 0x280e0 |
78 | #define CB_COLOR0_MASK 0x28100 |
84 | #define CB_COLOR0_MASK 0x28100 |
Line -... | Line 85... | ||
- | 85 | ||
- | 86 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
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- | 87 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
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- | 88 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
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- | 89 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
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- | 90 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
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- | 91 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
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- | 92 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
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- | 93 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
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- | 94 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
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- | 95 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
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- | 96 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
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- | 97 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
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- | 98 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
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- | 99 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
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- | 100 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
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- | 101 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
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- | 102 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
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- | 103 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
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- | 104 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
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- | 105 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
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- | 106 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
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- | 107 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
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- | 108 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
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- | 109 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
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- | 110 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
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- | 111 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
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- | 112 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
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- | 113 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
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- | 114 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
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- | 115 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
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- | 116 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
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- | 117 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
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- | 118 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
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- | 119 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
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- | 120 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
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- | 121 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
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- | 122 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
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- | 123 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
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- | 124 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
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- | 125 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
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- | 126 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
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- | 127 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
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- | 128 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
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- | 129 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
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- | 130 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
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- | 131 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
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- | 132 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
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- | 133 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
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79 | 134 | ||
80 | #define CONFIG_MEMSIZE 0x5428 |
135 | #define CONFIG_MEMSIZE 0x5428 |
81 | #define CONFIG_CNTL 0x5424 |
136 | #define CONFIG_CNTL 0x5424 |
82 | #define CP_STAT 0x8680 |
137 | #define CP_STAT 0x8680 |
83 | #define CP_COHER_BASE 0x85F8 |
138 | #define CP_COHER_BASE 0x85F8 |
Line 104... | Line 159... | ||
104 | #define RB_NO_UPDATE (1<<27) |
159 | #define RB_NO_UPDATE (1 << 27) |
105 | #define RB_RPTR_WR_ENA (1<<31) |
160 | #define RB_RPTR_WR_ENA (1 << 31) |
106 | #define BUF_SWAP_32BIT (2 << 16) |
161 | #define BUF_SWAP_32BIT (2 << 16) |
107 | #define CP_RB_RPTR 0x8700 |
162 | #define CP_RB_RPTR 0x8700 |
108 | #define CP_RB_RPTR_ADDR 0xC10C |
163 | #define CP_RB_RPTR_ADDR 0xC10C |
- | 164 | #define RB_RPTR_SWAP(x) ((x) << 0) |
|
109 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
165 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
110 | #define CP_RB_RPTR_WR 0xC108 |
166 | #define CP_RB_RPTR_WR 0xC108 |
111 | #define CP_RB_WPTR 0xC114 |
167 | #define CP_RB_WPTR 0xC114 |
112 | #define CP_RB_WPTR_ADDR 0xC118 |
168 | #define CP_RB_WPTR_ADDR 0xC118 |
113 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
169 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
Line 188... | Line 244... | ||
188 | #define GUI_ACTIVE (1<<31) |
244 | #define GUI_ACTIVE (1<<31) |
189 | #define GRBM_STATUS2 0x8014 |
245 | #define GRBM_STATUS2 0x8014 |
190 | #define GRBM_SOFT_RESET 0x8020 |
246 | #define GRBM_SOFT_RESET 0x8020 |
191 | #define SOFT_RESET_CP (1<<0) |
247 | #define SOFT_RESET_CP (1<<0) |
Line -... | Line 248... | ||
- | 248 | ||
- | 249 | #define CG_THERMAL_STATUS 0x7F4 |
|
- | 250 | #define ASIC_T(x) ((x) << 0) |
|
- | 251 | #define ASIC_T_MASK 0x1FF |
|
- | 252 | #define ASIC_T_SHIFT 0 |
|
192 | 253 | ||
193 | #define HDP_HOST_PATH_CNTL 0x2C00 |
254 | #define HDP_HOST_PATH_CNTL 0x2C00 |
194 | #define HDP_NONSURFACE_BASE 0x2C04 |
255 | #define HDP_NONSURFACE_BASE 0x2C04 |
195 | #define HDP_NONSURFACE_INFO 0x2C08 |
256 | #define HDP_NONSURFACE_INFO 0x2C08 |
196 | #define HDP_NONSURFACE_SIZE 0x2C0C |
257 | #define HDP_NONSURFACE_SIZE 0x2C0C |
197 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
258 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
- | 259 | #define HDP_TILING_CONFIG 0x2F3C |
|
Line 198... | Line 260... | ||
198 | #define HDP_TILING_CONFIG 0x2F3C |
260 | #define HDP_DEBUG1 0x2F34 |
199 | 261 | ||
200 | #define MC_VM_AGP_TOP 0x2184 |
262 | #define MC_VM_AGP_TOP 0x2184 |
201 | #define MC_VM_AGP_BOT 0x2188 |
263 | #define MC_VM_AGP_BOT 0x2188 |
Line 417... | Line 479... | ||
417 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
479 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
418 | #define VGT_STRMOUT_EN 0x28AB0 |
480 | #define VGT_STRMOUT_EN 0x28AB0 |
419 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
481 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
420 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
482 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
421 | #define VGT_EVENT_INITIATOR 0x28a90 |
483 | #define VGT_EVENT_INITIATOR 0x28a90 |
- | 484 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
|
422 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
485 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
Line 423... | Line 486... | ||
423 | 486 | ||
424 | #define VM_CONTEXT0_CNTL 0x1410 |
487 | #define VM_CONTEXT0_CNTL 0x1410 |
425 | #define ENABLE_CONTEXT (1 << 0) |
488 | #define ENABLE_CONTEXT (1 << 0) |
Line 664... | Line 727... | ||
664 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
727 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
665 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
728 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
666 | /* DCE 3.2 */ |
729 | /* DCE 3.2 */ |
667 | # define DC_HPDx_EN (1 << 28) |
730 | # define DC_HPDx_EN (1 << 28) |
Line -... | Line 731... | ||
- | 731 | ||
- | 732 | #define D1GRPH_INTERRUPT_STATUS 0x6158 |
|
- | 733 | #define D2GRPH_INTERRUPT_STATUS 0x6958 |
|
- | 734 | # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) |
|
- | 735 | # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) |
|
- | 736 | #define D1GRPH_INTERRUPT_CONTROL 0x615c |
|
- | 737 | #define D2GRPH_INTERRUPT_CONTROL 0x695c |
|
- | 738 | # define DxGRPH_PFLIP_INT_MASK (1 << 0) |
|
- | 739 | # define DxGRPH_PFLIP_INT_TYPE (1 << 8) |
|
- | 740 | ||
- | 741 | /* PCIE link stuff */ |
|
- | 742 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
|
- | 743 | # define LC_POINT_7_PLUS_EN (1 << 6) |
|
- | 744 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
|
- | 745 | # define LC_LINK_WIDTH_SHIFT 0 |
|
- | 746 | # define LC_LINK_WIDTH_MASK 0x7 |
|
- | 747 | # define LC_LINK_WIDTH_X0 0 |
|
- | 748 | # define LC_LINK_WIDTH_X1 1 |
|
- | 749 | # define LC_LINK_WIDTH_X2 2 |
|
- | 750 | # define LC_LINK_WIDTH_X4 3 |
|
- | 751 | # define LC_LINK_WIDTH_X8 4 |
|
- | 752 | # define LC_LINK_WIDTH_X16 6 |
|
- | 753 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
|
- | 754 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
|
- | 755 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
|
- | 756 | # define LC_RECONFIG_NOW (1 << 8) |
|
- | 757 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
|
- | 758 | # define LC_RENEGOTIATE_EN (1 << 10) |
|
- | 759 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
|
- | 760 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
|
- | 761 | # define LC_UPCONFIGURE_DIS (1 << 13) |
|
- | 762 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
|
- | 763 | # define LC_GEN2_EN_STRAP (1 << 0) |
|
- | 764 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
|
- | 765 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
|
- | 766 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
|
- | 767 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
|
- | 768 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
|
- | 769 | # define LC_CURRENT_DATA_RATE (1 << 11) |
|
- | 770 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
|
- | 771 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
|
- | 772 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
|
- | 773 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
|
- | 774 | #define MM_CFGREGS_CNTL 0x544c |
|
- | 775 | # define MM_WR_TO_CFG_EN (1 << 3) |
|
- | 776 | #define LINK_CNTL2 0x88 /* F0 */ |
|
- | 777 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
|
- | 778 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
|
668 | 779 | ||
669 | /* |
780 | /* |
670 | * PM4 |
781 | * PM4 |
671 | */ |
782 | */ |
672 | #define PACKET_TYPE0 0 |
783 | #define PACKET_TYPE0 0 |
Line 718... | Line 829... | ||
718 | # define PACKET3_SMX_ACTION_ENA (1 << 28) |
829 | # define PACKET3_SMX_ACTION_ENA (1 << 28) |
719 | #define PACKET3_ME_INITIALIZE 0x44 |
830 | #define PACKET3_ME_INITIALIZE 0x44 |
720 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
831 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
721 | #define PACKET3_COND_WRITE 0x45 |
832 | #define PACKET3_COND_WRITE 0x45 |
722 | #define PACKET3_EVENT_WRITE 0x46 |
833 | #define PACKET3_EVENT_WRITE 0x46 |
- | 834 | #define EVENT_TYPE(x) ((x) << 0) |
|
- | 835 | #define EVENT_INDEX(x) ((x) << 8) |
|
- | 836 | /* 0 - any non-TS event |
|
- | 837 | * 1 - ZPASS_DONE |
|
- | 838 | * 2 - SAMPLE_PIPELINESTAT |
|
- | 839 | * 3 - SAMPLE_STREAMOUTSTAT* |
|
- | 840 | * 4 - *S_PARTIAL_FLUSH |
|
- | 841 | * 5 - TS events |
|
- | 842 | */ |
|
723 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
843 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
- | 844 | #define DATA_SEL(x) ((x) << 29) |
|
- | 845 | /* 0 - discard |
|
- | 846 | * 1 - send low 32bit data |
|
- | 847 | * 2 - send 64bit data |
|
- | 848 | * 3 - send 64bit counter value |
|
- | 849 | */ |
|
- | 850 | #define INT_SEL(x) ((x) << 24) |
|
- | 851 | /* 0 - none |
|
- | 852 | * 1 - interrupt only (DATA_SEL = 0) |
|
- | 853 | * 2 - interrupt when data write is confirmed |
|
- | 854 | */ |
|
724 | #define PACKET3_ONE_REG_WRITE 0x57 |
855 | #define PACKET3_ONE_REG_WRITE 0x57 |
725 | #define PACKET3_SET_CONFIG_REG 0x68 |
856 | #define PACKET3_SET_CONFIG_REG 0x68 |
726 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 |
857 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 |
727 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
858 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
728 | #define PACKET3_SET_CONTEXT_REG 0x69 |
859 | #define PACKET3_SET_CONTEXT_REG 0x69 |
Line 1103... | Line 1234... | ||
1103 | #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 |
1234 | #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 |
1104 | #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 |
1235 | #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 |
1105 | #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) |
1236 | #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) |
1106 | #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) |
1237 | #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) |
1107 | #define C_038000_TILE_MODE 0xFFFFFF87 |
1238 | #define C_038000_TILE_MODE 0xFFFFFF87 |
- | 1239 | #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 |
|
- | 1240 | #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 |
|
- | 1241 | #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 |
|
- | 1242 | #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 |
|
1108 | #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) |
1243 | #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) |
1109 | #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) |
1244 | #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) |
1110 | #define C_038000_TILE_TYPE 0xFFFFFF7F |
1245 | #define C_038000_TILE_TYPE 0xFFFFFF7F |
1111 | #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) |
1246 | #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) |
1112 | #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) |
1247 | #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) |
Line 1167... | Line 1302... | ||
1167 | #define V_038004_FMT_8_8_8 0x0000002C |
1302 | #define V_038004_FMT_8_8_8 0x0000002C |
1168 | #define V_038004_FMT_16_16_16 0x0000002D |
1303 | #define V_038004_FMT_16_16_16 0x0000002D |
1169 | #define V_038004_FMT_16_16_16_FLOAT 0x0000002E |
1304 | #define V_038004_FMT_16_16_16_FLOAT 0x0000002E |
1170 | #define V_038004_FMT_32_32_32 0x0000002F |
1305 | #define V_038004_FMT_32_32_32 0x0000002F |
1171 | #define V_038004_FMT_32_32_32_FLOAT 0x00000030 |
1306 | #define V_038004_FMT_32_32_32_FLOAT 0x00000030 |
- | 1307 | #define V_038004_FMT_BC1 0x00000031 |
|
- | 1308 | #define V_038004_FMT_BC2 0x00000032 |
|
- | 1309 | #define V_038004_FMT_BC3 0x00000033 |
|
- | 1310 | #define V_038004_FMT_BC4 0x00000034 |
|
- | 1311 | #define V_038004_FMT_BC5 0x00000035 |
|
- | 1312 | #define V_038004_FMT_BC6 0x00000036 |
|
- | 1313 | #define V_038004_FMT_BC7 0x00000037 |
|
- | 1314 | #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 |
|
1172 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
1315 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
1173 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
1316 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
1174 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |
1317 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |
1175 | #define C_038010_FORMAT_COMP_X 0xFFFFFFFC |
1318 | #define C_038010_FORMAT_COMP_X 0xFFFFFFFC |
1176 | #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) |
1319 | #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) |
Line 1306... | Line 1449... | ||
1306 | #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) |
1449 | #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) |
1307 | #define C_028010_READ_SIZE 0xFFFFFFF7 |
1450 | #define C_028010_READ_SIZE 0xFFFFFFF7 |
1308 | #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) |
1451 | #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) |
1309 | #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) |
1452 | #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) |
1310 | #define C_028010_ARRAY_MODE 0xFFF87FFF |
1453 | #define C_028010_ARRAY_MODE 0xFFF87FFF |
- | 1454 | #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 |
|
- | 1455 | #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 |
|
1311 | #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) |
1456 | #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) |
1312 | #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) |
1457 | #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) |
1313 | #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF |
1458 | #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF |
1314 | #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) |
1459 | #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) |
1315 | #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) |
1460 | #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) |