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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __R600_REG_H__ |
28 | #ifndef __R600_REG_H__ |
29 | #define __R600_REG_H__ |
29 | #define __R600_REG_H__ |
30 | 30 | ||
31 | #define R600_PCIE_PORT_INDEX 0x0038 |
31 | #define R600_PCIE_PORT_INDEX 0x0038 |
32 | #define R600_PCIE_PORT_DATA 0x003c |
32 | #define R600_PCIE_PORT_DATA 0x003c |
33 | 33 | ||
34 | #define R600_MC_VM_FB_LOCATION 0x2180 |
34 | #define R600_MC_VM_FB_LOCATION 0x2180 |
35 | #define R600_MC_FB_BASE_MASK 0x0000FFFF |
35 | #define R600_MC_FB_BASE_MASK 0x0000FFFF |
36 | #define R600_MC_FB_BASE_SHIFT 0 |
36 | #define R600_MC_FB_BASE_SHIFT 0 |
37 | #define R600_MC_FB_TOP_MASK 0xFFFF0000 |
37 | #define R600_MC_FB_TOP_MASK 0xFFFF0000 |
38 | #define R600_MC_FB_TOP_SHIFT 16 |
38 | #define R600_MC_FB_TOP_SHIFT 16 |
39 | #define R600_MC_VM_AGP_TOP 0x2184 |
39 | #define R600_MC_VM_AGP_TOP 0x2184 |
40 | #define R600_MC_AGP_TOP_MASK 0x0003FFFF |
40 | #define R600_MC_AGP_TOP_MASK 0x0003FFFF |
41 | #define R600_MC_AGP_TOP_SHIFT 0 |
41 | #define R600_MC_AGP_TOP_SHIFT 0 |
42 | #define R600_MC_VM_AGP_BOT 0x2188 |
42 | #define R600_MC_VM_AGP_BOT 0x2188 |
43 | #define R600_MC_AGP_BOT_MASK 0x0003FFFF |
43 | #define R600_MC_AGP_BOT_MASK 0x0003FFFF |
44 | #define R600_MC_AGP_BOT_SHIFT 0 |
44 | #define R600_MC_AGP_BOT_SHIFT 0 |
45 | #define R600_MC_VM_AGP_BASE 0x218c |
45 | #define R600_MC_VM_AGP_BASE 0x218c |
46 | #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
46 | #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
47 | #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
47 | #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
48 | #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 |
48 | #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 |
49 | #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
49 | #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
50 | #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
50 | #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
51 | 51 | ||
52 | #define R700_MC_VM_FB_LOCATION 0x2024 |
52 | #define R700_MC_VM_FB_LOCATION 0x2024 |
53 | #define R700_MC_FB_BASE_MASK 0x0000FFFF |
53 | #define R700_MC_FB_BASE_MASK 0x0000FFFF |
54 | #define R700_MC_FB_BASE_SHIFT 0 |
54 | #define R700_MC_FB_BASE_SHIFT 0 |
55 | #define R700_MC_FB_TOP_MASK 0xFFFF0000 |
55 | #define R700_MC_FB_TOP_MASK 0xFFFF0000 |
56 | #define R700_MC_FB_TOP_SHIFT 16 |
56 | #define R700_MC_FB_TOP_SHIFT 16 |
57 | #define R700_MC_VM_AGP_TOP 0x2028 |
57 | #define R700_MC_VM_AGP_TOP 0x2028 |
58 | #define R700_MC_AGP_TOP_MASK 0x0003FFFF |
58 | #define R700_MC_AGP_TOP_MASK 0x0003FFFF |
59 | #define R700_MC_AGP_TOP_SHIFT 0 |
59 | #define R700_MC_AGP_TOP_SHIFT 0 |
60 | #define R700_MC_VM_AGP_BOT 0x202c |
60 | #define R700_MC_VM_AGP_BOT 0x202c |
61 | #define R700_MC_AGP_BOT_MASK 0x0003FFFF |
61 | #define R700_MC_AGP_BOT_MASK 0x0003FFFF |
62 | #define R700_MC_AGP_BOT_SHIFT 0 |
62 | #define R700_MC_AGP_BOT_SHIFT 0 |
63 | #define R700_MC_VM_AGP_BASE 0x2030 |
63 | #define R700_MC_VM_AGP_BASE 0x2030 |
64 | #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
64 | #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
65 | #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
65 | #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
66 | #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 |
66 | #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 |
67 | #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
67 | #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
68 | #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c |
68 | #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c |
69 | 69 | ||
70 | #define R600_RAMCFG 0x2408 |
70 | #define R600_RAMCFG 0x2408 |
71 | # define R600_CHANSIZE (1 << 7) |
71 | # define R600_CHANSIZE (1 << 7) |
72 | # define R600_CHANSIZE_OVERRIDE (1 << 10) |
72 | # define R600_CHANSIZE_OVERRIDE (1 << 10) |
73 | 73 | ||
74 | 74 | ||
75 | #define R600_GENERAL_PWRMGT 0x618 |
75 | #define R600_GENERAL_PWRMGT 0x618 |
76 | # define R600_OPEN_DRAIN_PADS (1 << 11) |
76 | # define R600_OPEN_DRAIN_PADS (1 << 11) |
77 | 77 | ||
78 | #define R600_LOWER_GPIO_ENABLE 0x710 |
78 | #define R600_LOWER_GPIO_ENABLE 0x710 |
79 | #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
79 | #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
80 | #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c |
80 | #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c |
81 | #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
81 | #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
82 | #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
82 | #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
83 | 83 | ||
84 | #define R600_D1GRPH_SWAP_CONTROL 0x610C |
84 | #define R600_D1GRPH_SWAP_CONTROL 0x610C |
85 | # define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) |
85 | # define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) |
86 | # define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) |
86 | # define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) |
87 | # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) |
87 | # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) |
88 | # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) |
88 | # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) |
89 | 89 | ||
90 | #define R600_HDP_NONSURFACE_BASE 0x2c04 |
90 | #define R600_HDP_NONSURFACE_BASE 0x2c04 |
91 | 91 | ||
92 | #define R600_BUS_CNTL 0x5420 |
92 | #define R600_BUS_CNTL 0x5420 |
93 | # define R600_BIOS_ROM_DIS (1 << 1) |
93 | # define R600_BIOS_ROM_DIS (1 << 1) |
94 | #define R600_CONFIG_CNTL 0x5424 |
94 | #define R600_CONFIG_CNTL 0x5424 |
95 | #define R600_CONFIG_MEMSIZE 0x5428 |
95 | #define R600_CONFIG_MEMSIZE 0x5428 |
96 | #define R600_CONFIG_F0_BASE 0x542C |
96 | #define R600_CONFIG_F0_BASE 0x542C |
97 | #define R600_CONFIG_APER_SIZE 0x5430 |
97 | #define R600_CONFIG_APER_SIZE 0x5430 |
98 | 98 | ||
99 | #define R600_ROM_CNTL 0x1600 |
99 | #define R600_ROM_CNTL 0x1600 |
100 | # define R600_SCK_OVERWRITE (1 << 1) |
100 | # define R600_SCK_OVERWRITE (1 << 1) |
101 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 |
101 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 |
102 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) |
102 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) |
103 | 103 | ||
104 | #define R600_CG_SPLL_FUNC_CNTL 0x600 |
104 | #define R600_CG_SPLL_FUNC_CNTL 0x600 |
105 | # define R600_SPLL_BYPASS_EN (1 << 3) |
105 | # define R600_SPLL_BYPASS_EN (1 << 3) |
106 | #define R600_CG_SPLL_STATUS 0x60c |
106 | #define R600_CG_SPLL_STATUS 0x60c |
107 | # define R600_SPLL_CHG_STATUS (1 << 1) |
107 | # define R600_SPLL_CHG_STATUS (1 << 1) |
108 | 108 | ||
109 | #define R600_BIOS_0_SCRATCH 0x1724 |
109 | #define R600_BIOS_0_SCRATCH 0x1724 |
110 | #define R600_BIOS_1_SCRATCH 0x1728 |
110 | #define R600_BIOS_1_SCRATCH 0x1728 |
111 | #define R600_BIOS_2_SCRATCH 0x172c |
111 | #define R600_BIOS_2_SCRATCH 0x172c |
112 | #define R600_BIOS_3_SCRATCH 0x1730 |
112 | #define R600_BIOS_3_SCRATCH 0x1730 |
113 | #define R600_BIOS_4_SCRATCH 0x1734 |
113 | #define R600_BIOS_4_SCRATCH 0x1734 |
114 | #define R600_BIOS_5_SCRATCH 0x1738 |
114 | #define R600_BIOS_5_SCRATCH 0x1738 |
115 | #define R600_BIOS_6_SCRATCH 0x173c |
115 | #define R600_BIOS_6_SCRATCH 0x173c |
116 | #define R600_BIOS_7_SCRATCH 0x1740 |
116 | #define R600_BIOS_7_SCRATCH 0x1740 |
117 | 117 | ||
118 | /* Audio, these regs were reverse enginered, |
118 | /* Audio, these regs were reverse enginered, |
119 | * so the chance is high that the naming is wrong |
119 | * so the chance is high that the naming is wrong |
120 | * R6xx+ ??? */ |
120 | * R6xx+ ??? */ |
121 | 121 | ||
122 | /* Audio clocks */ |
122 | /* Audio clocks */ |
123 | #define R600_AUDIO_PLL1_MUL 0x0514 |
123 | #define R600_AUDIO_PLL1_MUL 0x0514 |
124 | #define R600_AUDIO_PLL1_DIV 0x0518 |
124 | #define R600_AUDIO_PLL1_DIV 0x0518 |
125 | #define R600_AUDIO_PLL2_MUL 0x0524 |
125 | #define R600_AUDIO_PLL2_MUL 0x0524 |
126 | #define R600_AUDIO_PLL2_DIV 0x0528 |
126 | #define R600_AUDIO_PLL2_DIV 0x0528 |
127 | #define R600_AUDIO_CLK_SRCSEL 0x0534 |
127 | #define R600_AUDIO_CLK_SRCSEL 0x0534 |
128 | 128 | ||
129 | /* Audio general */ |
129 | /* Audio general */ |
130 | #define R600_AUDIO_ENABLE 0x7300 |
130 | #define R600_AUDIO_ENABLE 0x7300 |
131 | #define R600_AUDIO_TIMING 0x7344 |
131 | #define R600_AUDIO_TIMING 0x7344 |
132 | 132 | ||
133 | /* Audio params */ |
133 | /* Audio params */ |
134 | #define R600_AUDIO_VENDOR_ID 0x7380 |
134 | #define R600_AUDIO_VENDOR_ID 0x7380 |
135 | #define R600_AUDIO_REVISION_ID 0x7384 |
135 | #define R600_AUDIO_REVISION_ID 0x7384 |
136 | #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 |
136 | #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 |
137 | #define R600_AUDIO_NID1_NODE_COUNT 0x738c |
137 | #define R600_AUDIO_NID1_NODE_COUNT 0x738c |
138 | #define R600_AUDIO_NID1_TYPE 0x7390 |
138 | #define R600_AUDIO_NID1_TYPE 0x7390 |
139 | #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 |
139 | #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 |
140 | #define R600_AUDIO_SUPPORTED_CODEC 0x7398 |
140 | #define R600_AUDIO_SUPPORTED_CODEC 0x7398 |
141 | #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c |
141 | #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c |
142 | #define R600_AUDIO_NID2_CAPS 0x73a0 |
142 | #define R600_AUDIO_NID2_CAPS 0x73a0 |
143 | #define R600_AUDIO_NID3_CAPS 0x73a4 |
143 | #define R600_AUDIO_NID3_CAPS 0x73a4 |
144 | #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 |
144 | #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 |
145 | 145 | ||
146 | /* Audio conn list */ |
146 | /* Audio conn list */ |
147 | #define R600_AUDIO_CONN_LIST_LEN 0x73ac |
147 | #define R600_AUDIO_CONN_LIST_LEN 0x73ac |
148 | #define R600_AUDIO_CONN_LIST 0x73b0 |
148 | #define R600_AUDIO_CONN_LIST 0x73b0 |
149 | 149 | ||
150 | /* Audio verbs */ |
150 | /* Audio verbs */ |
151 | #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 |
151 | #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 |
152 | #define R600_AUDIO_PLAYING 0x73c4 |
152 | #define R600_AUDIO_PLAYING 0x73c4 |
153 | #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 |
153 | #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 |
154 | #define R600_AUDIO_CONFIG_DEFAULT 0x73cc |
154 | #define R600_AUDIO_CONFIG_DEFAULT 0x73cc |
155 | #define R600_AUDIO_PIN_SENSE 0x73d0 |
155 | #define R600_AUDIO_PIN_SENSE 0x73d0 |
156 | #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 |
156 | #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 |
157 | #define R600_AUDIO_STATUS_BITS 0x73d8 |
157 | #define R600_AUDIO_STATUS_BITS 0x73d8 |
158 | - | ||
159 | /* HDMI base register addresses */ |
158 | |
160 | #define R600_HDMI_BLOCK1 0x7400 |
- | |
161 | #define R600_HDMI_BLOCK2 0x7700 |
- | |
162 | #define R600_HDMI_BLOCK3 0x7800 |
- | |
163 | - | ||
164 | /* HDMI registers */ |
- | |
165 | #define R600_HDMI_ENABLE 0x00 |
- | |
166 | #define R600_HDMI_STATUS 0x04 |
- | |
167 | # define R600_HDMI_INT_PENDING (1 << 29) |
- | |
168 | #define R600_HDMI_CNTL 0x08 |
- | |
169 | # define R600_HDMI_INT_EN (1 << 28) |
- | |
170 | # define R600_HDMI_INT_ACK (1 << 29) |
- | |
171 | #define R600_HDMI_UNKNOWN_0 0x0C |
- | |
172 | #define R600_HDMI_AUDIOCNTL 0x10 |
- | |
173 | #define R600_HDMI_VIDEOCNTL 0x14 |
- | |
174 | #define R600_HDMI_VERSION 0x18 |
- | |
175 | #define R600_HDMI_UNKNOWN_1 0x28 |
- | |
176 | #define R600_HDMI_VIDEOINFOFRAME_0 0x54 |
- | |
177 | #define R600_HDMI_VIDEOINFOFRAME_1 0x58 |
- | |
178 | #define R600_HDMI_VIDEOINFOFRAME_2 0x5c |
- | |
179 | #define R600_HDMI_VIDEOINFOFRAME_3 0x60 |
- | |
180 | #define R600_HDMI_32kHz_CTS 0xac |
- | |
181 | #define R600_HDMI_32kHz_N 0xb0 |
- | |
182 | #define R600_HDMI_44_1kHz_CTS 0xb4 |
- | |
183 | #define R600_HDMI_44_1kHz_N 0xb8 |
- | |
184 | #define R600_HDMI_48kHz_CTS 0xbc |
- | |
185 | #define R600_HDMI_48kHz_N 0xc0 |
- | |
186 | #define R600_HDMI_AUDIOINFOFRAME_0 0xcc |
- | |
187 | #define R600_HDMI_AUDIOINFOFRAME_1 0xd0 |
- | |
188 | #define R600_HDMI_IEC60958_1 0xd4 |
- | |
189 | #define R600_HDMI_IEC60958_2 0xd8 |
- | |
190 | #define R600_HDMI_UNKNOWN_2 0xdc |
159 | #define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400) |
191 | #define R600_HDMI_AUDIO_DEBUG_0 0xe0 |
- | |
192 | #define R600_HDMI_AUDIO_DEBUG_1 0xe4 |
- | |
193 | #define R600_HDMI_AUDIO_DEBUG_2 0xe8 |
- | |
194 | #define R600_HDMI_AUDIO_DEBUG_3 0xec |
- | |
195 | 160 | #define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400) |
|
196 | /* HDMI additional config base register addresses */ |
161 | /* DCE3.2 second instance starts at 0x7800 */ |
197 | #define R600_HDMI_CONFIG1 0x7600 |
162 | #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400) |
198 | #define R600_HDMI_CONFIG2 0x7a00 |
163 | #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400) |
199 | 164 | ||
200 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
165 | #endif><>><>><>><>><>><>><>><>><>><>><>><> |