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Rev 1963 Rev 2997
Line 21... Line 21...
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
23
 *
24
 * Authors: Christian König
24
 * Authors: Christian König
25
 */
25
 */
26
#include "drmP.h"
26
#include 
27
#include "radeon_drm.h"
27
#include 
28
#include "radeon.h"
28
#include "radeon.h"
29
#include "radeon_asic.h"
29
#include "radeon_asic.h"
-
 
30
#include "r600d.h"
30
#include "atom.h"
31
#include "atom.h"
Line 31... Line 32...
31
 
32
 
32
/*
33
/*
33
 * HDMI color format
34
 * HDMI color format
Line 50... Line 51...
50
	AUDIO_STATUS_NONAUDIO     = 0x20,
51
	AUDIO_STATUS_NONAUDIO     = 0x20,
51
	AUDIO_STATUS_PROFESSIONAL = 0x40,
52
	AUDIO_STATUS_PROFESSIONAL = 0x40,
52
	AUDIO_STATUS_LEVEL	= 0x80
53
	AUDIO_STATUS_LEVEL	= 0x80
53
};
54
};
Line 54... Line -...
54
 
-
 
55
struct {
-
 
56
	uint32_t Clock;
-
 
57
 
-
 
58
	int N_32kHz;
-
 
59
	int CTS_32kHz;
-
 
60
 
-
 
61
	int N_44_1kHz;
-
 
62
	int CTS_44_1kHz;
-
 
63
 
-
 
64
	int N_48kHz;
-
 
65
	int CTS_48kHz;
-
 
66
 
55
 
67
} r600_hdmi_ACR[] = {
56
static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
68
    /*	     32kHz	  44.1kHz	48kHz    */
57
    /*	     32kHz	  44.1kHz	48kHz    */
69
    /* Clock      N     CTS      N     CTS      N     CTS */
58
    /* Clock      N     CTS      N     CTS      N     CTS */
70
    {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
59
    {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
71
    {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
60
    {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
Line 81... Line 70...
81
};
70
};
Line 82... Line 71...
82
 
71
 
83
/*
72
/*
84
 * calculate CTS value if it's not found in the table
73
 * calculate CTS value if it's not found in the table
85
 */
74
 */
86
static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
75
static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
87
{
76
{
88
	if (*CTS == 0)
77
	if (*CTS == 0)
89
		*CTS = clock * N / (128 * freq) * 1000;
78
		*CTS = clock * N / (128 * freq) * 1000;
90
	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
79
	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
91
		  N, *CTS, freq);
80
		  N, *CTS, freq);
Line -... Line 81...
-
 
81
}
-
 
82
 
-
 
83
struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
-
 
84
{
-
 
85
	struct radeon_hdmi_acr res;
-
 
86
	u8 i;
-
 
87
 
-
 
88
	for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
-
 
89
	     r600_hdmi_predefined_acr[i].clock != 0; i++)
-
 
90
		;
-
 
91
	res = r600_hdmi_predefined_acr[i];
-
 
92
 
-
 
93
	/* In case some CTS are missing */
-
 
94
	r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
-
 
95
	r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
-
 
96
	r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
-
 
97
 
-
 
98
	return res;
92
}
99
}
93
 
100
 
94
/*
101
/*
95
 * update the N and CTS parameters for a given pixel clock rate
102
 * update the N and CTS parameters for a given pixel clock rate
96
 */
103
 */
97
static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
104
static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
98
{
105
{
-
 
106
	struct drm_device *dev = encoder->dev;
99
	struct drm_device *dev = encoder->dev;
107
	struct radeon_device *rdev = dev->dev_private;
100
	struct radeon_device *rdev = dev->dev_private;
108
	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
101
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
-
 
102
	int CTS;
109
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
Line 103... Line 110...
103
	int N;
110
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-
 
111
	uint32_t offset = dig->afmt->offset;
Line 104... Line -...
104
	int i;
-
 
105
 
-
 
106
	for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
-
 
107
 
112
 
108
	CTS = r600_hdmi_ACR[i].CTS_32kHz;
-
 
109
	N = r600_hdmi_ACR[i].N_32kHz;
-
 
110
	r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
-
 
111
	WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
-
 
112
	WREG32(offset+R600_HDMI_32kHz_N, N);
-
 
113
 
113
	WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
114
	CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
-
 
115
	N = r600_hdmi_ACR[i].N_44_1kHz;
114
	WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
116
	r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
-
 
117
	WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
-
 
118
	WREG32(offset+R600_HDMI_44_1kHz_N, N);
-
 
119
 
115
 
120
	CTS = r600_hdmi_ACR[i].CTS_48kHz;
116
	WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
121
	N = r600_hdmi_ACR[i].N_48kHz;
117
	WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
Line 122... Line 118...
122
	r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
118
 
123
	WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
119
	WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
124
	WREG32(offset+R600_HDMI_48kHz_N, N);
120
	WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
Line 163... Line 159...
163
	uint16_t right_bar
159
	uint16_t right_bar
164
)
160
)
165
{
161
{
166
	struct drm_device *dev = encoder->dev;
162
	struct drm_device *dev = encoder->dev;
167
	struct radeon_device *rdev = dev->dev_private;
163
	struct radeon_device *rdev = dev->dev_private;
-
 
164
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-
 
165
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
168
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
166
	uint32_t offset = dig->afmt->offset;
Line 169... Line 167...
169
 
167
 
Line 170... Line 168...
170
	uint8_t frame[14];
168
	uint8_t frame[14];
171
 
169
 
Line 194... Line 192...
194
	frame[0xB] = (left_bar >> 8);
192
	frame[0xB] = (left_bar >> 8);
195
	frame[0xC] = (right_bar & 0xFF);
193
	frame[0xC] = (right_bar & 0xFF);
196
	frame[0xD] = (right_bar >> 8);
194
	frame[0xD] = (right_bar >> 8);
Line 197... Line 195...
197
 
195
 
-
 
196
	r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
-
 
197
	/* Our header values (type, version, length) should be alright, Intel
-
 
198
	 * is using the same. Checksum function also seems to be OK, it works
-
 
199
	 * fine for audio infoframe. However calculated value is always lower
-
 
200
	 * by 2 in comparison to fglrx. It breaks displaying anything in case
-
 
201
	 * of TVs that strictly check the checksum. Hack it manually here to
-
 
202
	 * workaround this issue. */
Line 198... Line 203...
198
	r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
203
	frame[0x0] += 2;
199
 
204
 
200
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
205
	WREG32(HDMI0_AVI_INFO0 + offset,
201
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
206
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
202
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
207
	WREG32(HDMI0_AVI_INFO1 + offset,
203
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
208
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
204
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
209
	WREG32(HDMI0_AVI_INFO2 + offset,
205
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
210
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
206
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
211
	WREG32(HDMI0_AVI_INFO3 + offset,
Line 207... Line 212...
207
		frame[0xC] | (frame[0xD] << 8));
212
		frame[0xC] | (frame[0xD] << 8));
208
}
213
}
Line 222... Line 227...
222
	int downmix_inhibit
227
	int downmix_inhibit
223
)
228
)
224
{
229
{
225
	struct drm_device *dev = encoder->dev;
230
	struct drm_device *dev = encoder->dev;
226
	struct radeon_device *rdev = dev->dev_private;
231
	struct radeon_device *rdev = dev->dev_private;
-
 
232
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-
 
233
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
227
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
234
	uint32_t offset = dig->afmt->offset;
Line 228... Line 235...
228
 
235
 
Line 229... Line 236...
229
	uint8_t frame[11];
236
	uint8_t frame[11];
230
 
237
 
Line 240... Line 247...
240
	frame[0x9] = 0;
247
	frame[0x9] = 0;
241
	frame[0xA] = 0;
248
	frame[0xA] = 0;
Line 242... Line 249...
242
 
249
 
Line 243... Line 250...
243
	r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
250
	r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
244
 
251
 
245
	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
252
	WREG32(HDMI0_AUDIO_INFO0 + offset,
246
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
253
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
247
	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
254
	WREG32(HDMI0_AUDIO_INFO1 + offset,
Line 248... Line 255...
248
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
255
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
249
}
256
}
250
 
257
 
251
/*
258
/*
252
 * test if audio buffer is filled enough to start playing
259
 * test if audio buffer is filled enough to start playing
253
 */
260
 */
254
static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
261
static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
-
 
262
{
-
 
263
	struct drm_device *dev = encoder->dev;
255
{
264
	struct radeon_device *rdev = dev->dev_private;
Line 256... Line 265...
256
	struct drm_device *dev = encoder->dev;
265
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
257
	struct radeon_device *rdev = dev->dev_private;
266
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Line 258... Line 267...
258
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
267
	uint32_t offset = dig->afmt->offset;
259
 
268
 
260
	return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
269
	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
261
}
270
}
262
 
271
 
263
/*
272
/*
-
 
273
 * have buffer status changed since last call?
264
 * have buffer status changed since last call?
274
 */
Line 265... Line 275...
265
 */
275
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
266
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
276
{
Line 267... Line 277...
267
{
277
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
268
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
278
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
269
	int status, result;
279
	int status, result;
Line 270... Line 280...
270
 
280
 
271
	if (!radeon_encoder->hdmi_offset)
281
	if (!dig->afmt || !dig->afmt->enabled)
Line 272... Line 282...
272
		return 0;
282
		return 0;
273
 
283
 
274
	status = r600_hdmi_is_audio_buffer_filled(encoder);
284
	status = r600_hdmi_is_audio_buffer_filled(encoder);
275
	result = radeon_encoder->hdmi_buffer_status != status;
285
	result = dig->afmt->last_buffer_filled_status != status;
276
	radeon_encoder->hdmi_buffer_status = status;
286
	dig->afmt->last_buffer_filled_status = status;
277
 
287
 
278
	return result;
288
	return result;
279
}
289
}
-
 
290
 
280
 
291
/*
281
/*
-
 
282
 * write the audio workaround status to the hardware
292
 * write the audio workaround status to the hardware
283
 */
293
 */
284
void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
294
static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
285
{
295
{
286
	struct drm_device *dev = encoder->dev;
296
	struct drm_device *dev = encoder->dev;
287
	struct radeon_device *rdev = dev->dev_private;
-
 
288
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
297
	struct radeon_device *rdev = dev->dev_private;
289
	uint32_t offset = radeon_encoder->hdmi_offset;
-
 
290
 
-
 
291
	if (!offset)
298
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
292
		return;
299
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
293
 
300
	uint32_t offset = dig->afmt->offset;
294
	if (!radeon_encoder->hdmi_audio_workaround ||
-
 
-
 
301
	bool hdmi_audio_workaround = false; /* FIXME */
295
		r600_hdmi_is_audio_buffer_filled(encoder)) {
302
	u32 value;
Line 296... Line 303...
296
 
303
 
297
		/* disable audio workaround */
304
	if (!hdmi_audio_workaround ||
298
		WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);
305
	    r600_hdmi_is_audio_buffer_filled(encoder))
299
 
306
		value = 0; /* disable workaround */
300
	} else {
307
	else
301
		/* enable audio workaround */
308
		value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
302
		WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
309
	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
303
	}
310
		 value, ~HDMI0_AUDIO_TEST_EN);
304
}
-
 
305
 
311
}
306
 
312
 
Line -... Line 313...
-
 
313
 
307
/*
314
/*
308
 * update the info frames with the data from the current display mode
315
 * update the info frames with the data from the current display mode
-
 
316
 */
Line 309... Line 317...
309
 */
317
void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
Line 310... Line -...
310
void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
-
 
311
{
318
{
312
	struct drm_device *dev = encoder->dev;
319
	struct drm_device *dev = encoder->dev;
Line 313... Line 320...
313
	struct radeon_device *rdev = dev->dev_private;
320
	struct radeon_device *rdev = dev->dev_private;
Line -... Line 321...
-
 
321
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-
 
322
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-
 
323
	uint32_t offset;
-
 
324
 
-
 
325
	/* Silent, r600_hdmi_enable will raise WARN for us */
-
 
326
	if (!dig->afmt->enabled)
-
 
327
		return;
-
 
328
	offset = dig->afmt->offset;
-
 
329
 
-
 
330
//	r600_audio_set_clock(encoder, mode->clock);
-
 
331
 
-
 
332
	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
-
 
333
	       HDMI0_NULL_SEND); /* send null packets when required */
-
 
334
 
-
 
335
	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
-
 
336
 
-
 
337
	if (ASIC_IS_DCE32(rdev)) {
-
 
338
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
-
 
339
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
314
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
340
		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
-
 
341
		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
-
 
342
		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
-
 
343
		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
-
 
344
	} else {
-
 
345
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
-
 
346
		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
-
 
347
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
-
 
348
		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
-
 
349
		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
-
 
350
	}
-
 
351
 
-
 
352
	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
-
 
353
	       HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
-
 
354
	       HDMI0_ACR_SOURCE); /* select SW CTS value */
Line 315... Line 355...
315
 
355
 
Line 316... Line 356...
316
	if (ASIC_IS_DCE4(rdev))
356
	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
317
		return;
357
	       HDMI0_NULL_SEND | /* send null packets when required */
Line -... Line 358...
-
 
358
	       HDMI0_GC_SEND | /* send general control packets */
-
 
359
	       HDMI0_GC_CONT); /* send general control packets every frame */
318
 
360
 
319
	if (!offset)
361
	/* TODO: HDMI0_AUDIO_INFO_UPDATE */
320
		return;
362
	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
321
 
363
	       HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
322
	r600_audio_set_clock(encoder, mode->clock);
364
	       HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
Line 323... Line 365...
323
 
365
	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
324
	WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
-
 
325
	WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
-
 
326
	WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);
-
 
327
 
366
	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
Line -... Line 367...
-
 
367
 
328
	r600_hdmi_update_ACR(encoder, mode->clock);
368
	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
329
 
369
	       HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
330
	WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);
370
	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
331
 
371
 
332
	WREG32(offset+R600_HDMI_VERSION, 0x202);
372
	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
333
 
373
 
334
	r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
374
	r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
335
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
375
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
336
 
-
 
337
	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
376
 
338
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
377
	r600_hdmi_update_ACR(encoder, mode->clock);
339
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
-
 
340
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
378
 
341
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);
-
 
342
 
-
 
343
	r600_hdmi_audio_workaround(encoder);
379
	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
Line 344... Line 380...
344
 
380
	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
345
	/* audio packets per line, does anyone know how to calc this ? */
381
	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
-
 
382
	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
Line 346... Line 383...
346
	WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
383
	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
347
}
384
 
348
 
385
	r600_hdmi_audio_workaround(encoder);
349
/*
386
}
350
 * update settings with current parameters from audio engine
387
 
Line 351... Line 388...
351
 */
388
#if 0
352
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
389
/*
353
{
390
 * update settings with current parameters from audio engine
354
	struct drm_device *dev = encoder->dev;
391
 */
355
	struct radeon_device *rdev = dev->dev_private;
392
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
356
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
393
{
357
 
394
	struct drm_device *dev = encoder->dev;
358
	int channels = r600_audio_channels(rdev);
395
	struct radeon_device *rdev = dev->dev_private;
359
	int rate = r600_audio_rate(rdev);
396
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
Line 360... Line 397...
360
	int bps = r600_audio_bits_per_sample(rdev);
397
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Line 361... Line 398...
361
	uint8_t status_bits = r600_audio_status_bits(rdev);
398
	struct r600_audio audio = r600_audio_status(rdev);
-
 
399
	uint32_t offset;
362
	uint8_t category_code = r600_audio_category_code(rdev);
400
	uint32_t iec;
-
 
401
 
-
 
402
	if (!dig->afmt || !dig->afmt->enabled)
363
 
403
		return;
-
 
404
	offset = dig->afmt->offset;
-
 
405
 
364
	uint32_t iec;
406
	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
-
 
407
		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
-
 
408
		  audio.channels, audio.rate, audio.bits_per_sample);
365
 
409
	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
-
 
410
		  (int)audio.status_bits, (int)audio.category_code);
-
 
411
 
366
	if (!offset)
412
	iec = 0;
-
 
413
	if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
-
 
414
		iec |= 1 << 0;
367
		return;
415
	if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
-
 
416
		iec |= 1 << 1;
368
 
417
	if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
-
 
418
		iec |= 1 << 2;
-
 
419
	if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
369
	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
420
		iec |= 1 << 3;
Line 370... Line 421...
370
		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
421
 
Line 371... Line 422...
371
		channels, rate, bps);
422
	iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
372
	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
423
 
373
		  (int)status_bits, (int)category_code);
-
 
374
 
-
 
375
	iec = 0;
-
 
376
	if (status_bits & AUDIO_STATUS_PROFESSIONAL)
-
 
377
		iec |= 1 << 0;
-
 
378
	if (status_bits & AUDIO_STATUS_NONAUDIO)
424
	switch (audio.rate) {
379
		iec |= 1 << 1;
-
 
380
	if (status_bits & AUDIO_STATUS_COPYRIGHT)
-
 
381
		iec |= 1 << 2;
-
 
382
	if (status_bits & AUDIO_STATUS_EMPHASIS)
-
 
383
		iec |= 1 << 3;
425
	case 32000:
384
 
-
 
385
	iec |= category_code << 8;
-
 
386
 
-
 
387
	switch (rate) {
-
 
388
	case  32000: iec |= 0x3 << 24; break;
-
 
389
	case  44100: iec |= 0x0 << 24; break;
-
 
390
	case  88200: iec |= 0x8 << 24; break;
-
 
391
	case 176400: iec |= 0xc << 24; break;
-
 
392
	case  48000: iec |= 0x2 << 24; break;
-
 
393
	case  96000: iec |= 0xa << 24; break;
-
 
394
	case 192000: iec |= 0xe << 24; break;
-
 
395
	}
-
 
396
 
-
 
397
	WREG32(offset+R600_HDMI_IEC60958_1, iec);
-
 
398
 
-
 
399
	iec = 0;
-
 
400
	switch (bps) {
-
 
401
	case 16: iec |= 0x2; break;
426
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
402
	case 20: iec |= 0x3; break;
427
		break;
403
	case 24: iec |= 0xb; break;
428
	case 44100:
404
	}
429
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
405
	if (status_bits & AUDIO_STATUS_V)
430
		break;
406
		iec |= 0x5 << 16;
431
	case 48000:
407
 
432
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
408
	WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);
433
		break;
409
 
-
 
410
	/* 0x021 or 0x031 sets the audio frame length */
-
 
411
	WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
-
 
412
	r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
434
	case 88200:
413
 
-
 
414
	r600_hdmi_audio_workaround(encoder);
-
 
415
}
435
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
416
 
-
 
417
static int r600_hdmi_find_free_block(struct drm_device *dev)
-
 
418
{
-
 
419
	struct radeon_device *rdev = dev->dev_private;
-
 
420
	struct drm_encoder *encoder;
-
 
421
	struct radeon_encoder *radeon_encoder;
-
 
422
	bool free_blocks[3] = { true, true, true };
-
 
423
 
-
 
424
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-
 
425
		radeon_encoder = to_radeon_encoder(encoder);
-
 
426
		switch (radeon_encoder->hdmi_offset) {
436
		break;
427
		case R600_HDMI_BLOCK1:
-
 
428
			free_blocks[0] = false;
-
 
Line 429... Line -...
429
			break;
-
 
430
		case R600_HDMI_BLOCK2:
437
	case 96000:
431
			free_blocks[1] = false;
438
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
432
			break;
-
 
Line 433... Line -...
433
		case R600_HDMI_BLOCK3:
-
 
434
			free_blocks[2] = false;
-
 
435
			break;
-
 
436
		}
439
		break;
437
	}
-
 
438
 
-
 
439
	if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
-
 
440
	    rdev->family == CHIP_RS740) {
-
 
441
		return free_blocks[0] ? R600_HDMI_BLOCK1 : 0;
-
 
442
	} else if (rdev->family >= CHIP_R600) {
-
 
443
		if (free_blocks[0])
-
 
444
			return R600_HDMI_BLOCK1;
-
 
445
		else if (free_blocks[1])
440
	case 176400:
-
 
441
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
Line 446... Line 442...
446
			return R600_HDMI_BLOCK2;
442
		break;
447
	}
443
	case 192000:
448
	return 0;
444
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
449
}
445
		break;
450
 
446
	}
451
static void r600_hdmi_assign_block(struct drm_encoder *encoder)
447
 
452
{
448
	WREG32(HDMI0_60958_0 + offset, iec);
453
	struct drm_device *dev = encoder->dev;
449
 
-
 
450
	iec = 0;
454
	struct radeon_device *rdev = dev->dev_private;
451
	switch (audio.bits_per_sample) {
-
 
452
	case 16:
Line 455... Line 453...
455
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
453
		iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
456
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
454
			break;
Line 457... Line -...
457
 
-
 
458
	if (!dig) {
455
	case 20:
459
		dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
456
		iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
460
		return;
-
 
461
	}
-
 
462
 
457
			break;
463
	if (ASIC_IS_DCE4(rdev)) {
458
	case 24:
464
		/* TODO */
-
 
Line 465... Line 459...
465
	} else if (ASIC_IS_DCE3(rdev)) {
459
		iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
466
		radeon_encoder->hdmi_offset = dig->dig_encoder ?
460
			break;
467
			R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
-
 
468
		if (ASIC_IS_DCE32(rdev))
461
		}
469
			radeon_encoder->hdmi_config_offset = dig->dig_encoder ?
462
	if (audio.status_bits & AUDIO_STATUS_V)
470
				R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1;
463
		iec |= 0x5 << 16;
471
	} else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 ||
464
	WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
-
 
465
 
472
		   rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
466
	r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0,
473
		radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev);
467
				 0);
474
	}
468
 
475
}
469
	r600_hdmi_audio_workaround(encoder);
-
 
470
}
-
 
471
#endif
-
 
472
 
-
 
473
/*
476
 
474
 * enable the HDMI engine
-
 
475
 */
-
 
476
void r600_hdmi_enable(struct drm_encoder *encoder)
-
 
477
{
-
 
478
	struct drm_device *dev = encoder->dev;
477
/*
479
	struct radeon_device *rdev = dev->dev_private;
478
 * enable the HDMI engine
480
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
479
 */
481
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-
 
482
	uint32_t offset;
480
void r600_hdmi_enable(struct drm_encoder *encoder)
483
	u32 hdmi;
481
{
484
 
-
 
485
	if (ASIC_IS_DCE6(rdev))
482
	struct drm_device *dev = encoder->dev;
486
		return;
483
	struct radeon_device *rdev = dev->dev_private;
-
 
484
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-
 
485
	uint32_t offset;
-
 
486
 
-
 
487
	if (ASIC_IS_DCE4(rdev))
-
 
Line -... Line 487...
-
 
487
 
488
		return;
488
	/* Silent, r600_hdmi_enable will raise WARN for us */
489
 
-
 
490
	if (!radeon_encoder->hdmi_offset) {
489
	if (dig->afmt->enabled)
491
		r600_hdmi_assign_block(encoder);
-
 
492
		if (!radeon_encoder->hdmi_offset) {
-
 
493
			dev_warn(rdev->dev, "Could not find HDMI block for "
-
 
494
				"0x%x encoder\n", radeon_encoder->encoder_id);
-
 
495
		return;
-
 
496
		}
490
		return;
-
 
491
	offset = dig->afmt->offset;
-
 
492
 
497
	}
493
	/* Older chipsets require setting HDMI and routing manually */
498
 
494
	if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
499
	offset = radeon_encoder->hdmi_offset;
495
		hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
500
	if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
496
	switch (radeon_encoder->encoder_id) {
Line 501... Line 497...
501
		WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
497
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
502
	} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
498
			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
503
	switch (radeon_encoder->encoder_id) {
499
				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
504
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
500
			hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
505
			WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);
501
		break;
506
			WREG32(offset + R600_HDMI_ENABLE, 0x101);
502
	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
507
		break;
503
			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
508
	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
504
				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
-
 
505
			hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
509
			WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);
506
			break;
Line 510... Line 507...
510
			WREG32(offset + R600_HDMI_ENABLE, 0x105);
507
		case ENCODER_OBJECT_ID_INTERNAL_DDI:
511
		break;
508
			WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
Line 512... Line 509...
512
	default:
509
			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
513
			dev_err(rdev->dev, "Unknown HDMI output type\n");
510
			break;
514
		break;
511
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
515
	}
512
			hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
516
	}
513
		break;
-
 
514
	default:
-
 
515
			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
-
 
516
				radeon_encoder->encoder_id);
Line 517... Line 517...
517
#if 0
517
		break;
518
	if (rdev->irq.installed
518
	}
Line -... Line 519...
-
 
519
		WREG32(HDMI0_CONTROL + offset, hdmi);
519
	    && rdev->family != CHIP_RS600
520
	}
-
 
521
 
520
	    && rdev->family != CHIP_RS690
522
	if (rdev->irq.installed) {
521
	    && rdev->family != CHIP_RS740) {
523
		/* if irq is available use it */
522
 
524
//		radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
523
		/* if irq is available use it */
525
	}
524
		rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
526
 
525
		radeon_irq_set(rdev);
527
	dig->afmt->enabled = true;
526
 
528
 
527
		r600_audio_disable_polling(encoder);
529
	DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
528
	} else {
530
		  offset, radeon_encoder->encoder_id);
-
 
531
}
-
 
532
 
-
 
533
/*
529
		/* if not fallback to polling */
534
 * disable the HDMI engine
-
 
535
 */
-
 
536
void r600_hdmi_disable(struct drm_encoder *encoder)
530
		r600_audio_enable_polling(encoder);
537
{
531
	}
538
	struct drm_device *dev = encoder->dev;
532
#endif
539
	struct radeon_device *rdev = dev->dev_private;
-
 
540
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
533
	DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
541
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
534
		radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
542
	uint32_t offset;
-
 
543
 
535
}
544
	if (ASIC_IS_DCE6(rdev))
Line 536... Line 545...
536
 
545
		return;
537
/*
-
 
538
 * disable the HDMI engine
546