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839 | } |
839 | } |
840 | } |
840 | } |
841 | } |
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Line 842... | Line -... | ||
842 | - | ||
843 | - | ||
844 | void r600_kms_video_blit(struct radeon_device *rdev, |
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845 | u64 src_gpu_addr, int dstx, int dsty, int w, int h, int pitch) |
- | |
846 | { |
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Line 847... | Line -... | ||
847 | u64 vb_gpu_addr; |
- | |
848 | u32 *vb; |
- | |
849 | - | ||
850 | // DRM_DEBUG("emitting video copy\n"); |
- | |
851 | vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
- | |
852 | - | ||
853 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
- | |
854 | // WARN_ON(1); |
- | |
855 | } |
- | |
856 | - | ||
857 | vb[0] = i2f(dstx); |
- | |
858 | vb[1] = i2f(dsty); |
- | |
859 | vb[2] = 0; |
- | |
860 | vb[3] = 0; |
- | |
861 | - | ||
862 | vb[4] = i2f(dstx); |
- | |
863 | vb[5] = i2f(dsty+h); |
- | |
864 | vb[6] = 0; |
- | |
865 | vb[7] = i2f(h); |
- | |
866 | - | ||
867 | vb[8] = i2f(dstx + w); |
- | |
868 | vb[9] = i2f(dsty + h); |
- | |
869 | vb[10] = i2f(w); |
- | |
870 | vb[11] = i2f(h); |
- | |
871 | - | ||
872 | /* src 9 */ |
- | |
873 | set_tex_resource(rdev, FMT_8_8_8_8, |
- | |
874 | w, h, pitch/4, src_gpu_addr); |
- | |
875 | /* 5 */ |
- | |
876 | cp_set_surface_sync(rdev, |
- | |
877 | PACKET3_TC_ACTION_ENA, pitch * h, src_gpu_addr); |
- | |
878 | - | ||
879 | /* dst 23 */ |
- | |
880 | set_render_target(rdev, COLOR_8_8_8_8, |
- | |
881 | 1024, 768, rdev->mc.vram_start); |
- | |
882 | - | ||
883 | /* scissors 12 */ |
- | |
884 | set_scissors(rdev, 0, 0, 1024, 768); |
- | |
885 | - | ||
886 | /* Vertex buffer setup 14 */ |
- | |
887 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
- | |
888 | set_vtx_resource(rdev, vb_gpu_addr); |
- | |
889 | - | ||
890 | /* draw 10 */ |
- | |
891 | draw_auto(rdev); |
- | |
892 | - | ||
893 | /* 5 */ |
- | |
894 | cp_set_surface_sync(rdev, |
- | |
895 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
- | |
896 | 1024*4*768, rdev->mc.vram_start); |
- | |
897 | - | ||
898 | /* 78 ring dwords per loop */ |
- | |
899 | vb += 12; |
- | |
900 | rdev->r600_blit.vb_used += 12 * 4; |
- | |
901 | - | ||
902 | } |
- | |
903 | - | ||
904 | extern struct radeon_device *main_device; |
- | |
905 | - | ||
906 | int r600_video_blit(uint64_t src_offset, int x, int y, |
- | |
907 | int w, int h, int pitch) |
- | |
908 | { |
- | |
909 | struct radeon_device *rdev = main_device; |
- | |
910 | static struct radeon_fence *fence; |
- | |
911 | unsigned long irq_flags; |
- | |
912 | - | ||
913 | int r; |
- | |
914 | - | ||
915 | if(fence == NULL) |
- | |
916 | { |
- | |
917 | r = radeon_fence_create(rdev, &fence); |
- | |
918 | if (r) { |
- | |
919 | printf("%s epic fail", __FUNCTION__); |
- | |
920 | return r; |
- | |
921 | } |
- | |
922 | }; |
- | |
923 | - | ||
924 | fence->evnt = CreateEvent(NULL, 0); |
- | |
925 | - | ||
926 | mutex_lock(&rdev->r600_blit.mutex); |
- | |
927 | rdev->r600_blit.vb_ib = NULL; |
- | |
928 | r = r600_blit_prepare_copy(rdev, h*pitch); |
- | |
929 | if (r) { |
- | |
930 | // if (rdev->r600_blit.vb_ib) |
- | |
931 | // radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
- | |
932 | mutex_unlock(&rdev->r600_blit.mutex); |
- | |
933 | return r; |
- | |
934 | } |
- | |
935 | - | ||
936 | r600_kms_video_blit(rdev, src_offset,x,y,w,h,pitch); |
- | |
937 | r600_blit_done_copy(rdev, fence); |
- | |
938 | mutex_unlock(&rdev->r600_blit.mutex); |
- | |
939 | - | ||
940 | r = radeon_fence_wait(fence, false); |
- | |
941 | - | ||
942 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
- | |
943 | list_del(&fence->list); |
- | |
944 | fence->emited = false; |
- | |
945 | fence->signaled = false; |
- | |
946 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
- | |
947 | - | ||
948 | return r; |
- | |
949 | }; |
- | |
950 | - | ||
951 | int r600_create_video(int w, int h, u32_t *outp) |
- | |
952 | { |
- | |
953 | int r; |
- | |
954 | struct radeon_device *rdev = main_device; |
- | |
955 | struct radeon_bo *sobj = NULL; |
- | |
956 | uint64_t saddr; |
- | |
957 | void *uaddr; |
- | |
958 | - | ||
959 | size_t size; |
- | |
960 | size_t pitch; |
- | |
961 | - | ||
962 | pitch = radeon_align_pitch(rdev, w, 32, false) * 4; |
- | |
963 | - | ||
964 | size = pitch * h; |
- | |
965 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, |
- | |
966 | RADEON_GEM_DOMAIN_GTT, &sobj); |
- | |
967 | if (r) { |
- | |
968 | goto fail; |
- | |
969 | } |
- | |
970 | r = radeon_bo_reserve(sobj, false); |
- | |
971 | if (unlikely(r != 0)) |
- | |
972 | goto fail; |
- | |
973 | r = radeon_bo_pin(sobj, RADEON_GEM_DOMAIN_GTT, &saddr); |
- | |
974 | // radeon_bo_unreserve(sobj); |
- | |
975 | if (r) { |
- | |
976 | goto fail; |
- | |
977 | } |
- | |
978 | - | ||
979 | r = radeon_bo_user_map(sobj, &uaddr); |
- | |
980 | if (r) { |
- | |
981 | goto fail; |
- | |
982 | } |
- | |
983 | - | ||
984 | ((uint64_t*)outp)[0] = saddr; |
- | |
985 | outp[2] = uaddr; |
- | |
986 | outp[3] = pitch; |
- | |
987 | - | ||
988 | // dbgprintf("Create video surface %x, mapped at %x pitch %d\n", |
- | |
989 | // (uint32_t)saddr, uaddr, pitch); |
- | |
990 | return 0; |
- | |
991 | - |