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Rev 5179 | Rev 5271 | ||
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Line 120... | Line 120... | ||
120 | return rdev->clock.spll.reference_freq; |
120 | return rdev->clock.spll.reference_freq; |
121 | } |
121 | } |
Line 122... | Line 122... | ||
122 | 122 | ||
123 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
123 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
- | 124 | { |
|
- | 125 | unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; |
|
- | 126 | int r; |
|
- | 127 | ||
- | 128 | /* bypass vclk and dclk with bclk */ |
|
- | 129 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 130 | VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), |
|
- | 131 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
- | 132 | ||
- | 133 | /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ |
|
- | 134 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( |
|
- | 135 | UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); |
|
- | 136 | ||
- | 137 | if (rdev->family >= CHIP_RS780) |
|
- | 138 | WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, |
|
- | 139 | ~UPLL_BYPASS_CNTL); |
|
- | 140 | ||
- | 141 | if (!vclk || !dclk) { |
|
- | 142 | /* keep the Bypass mode, put PLL to sleep */ |
|
- | 143 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
|
- | 144 | return 0; |
|
- | 145 | } |
|
- | 146 | ||
- | 147 | if (rdev->clock.spll.reference_freq == 10000) |
|
- | 148 | ref_div = 34; |
|
- | 149 | else |
|
- | 150 | ref_div = 4; |
|
- | 151 | ||
- | 152 | r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
|
- | 153 | ref_div + 1, 0xFFF, 2, 30, ~0, |
|
- | 154 | &fb_div, &vclk_div, &dclk_div); |
|
- | 155 | if (r) |
|
- | 156 | return r; |
|
- | 157 | ||
- | 158 | if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) |
|
- | 159 | fb_div >>= 1; |
|
- | 160 | else |
|
- | 161 | fb_div |= 1; |
|
- | 162 | ||
- | 163 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
|
- | 164 | if (r) |
|
- | 165 | return r; |
|
- | 166 | ||
- | 167 | /* assert PLL_RESET */ |
|
- | 168 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); |
|
- | 169 | ||
- | 170 | /* For RS780 we have to choose ref clk */ |
|
- | 171 | if (rdev->family >= CHIP_RS780) |
|
- | 172 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, |
|
- | 173 | ~UPLL_REFCLK_SRC_SEL_MASK); |
|
- | 174 | ||
- | 175 | /* set the required fb, ref and post divder values */ |
|
- | 176 | WREG32_P(CG_UPLL_FUNC_CNTL, |
|
- | 177 | UPLL_FB_DIV(fb_div) | |
|
- | 178 | UPLL_REF_DIV(ref_div), |
|
- | 179 | ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); |
|
- | 180 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 181 | UPLL_SW_HILEN(vclk_div >> 1) | |
|
- | 182 | UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | |
|
- | 183 | UPLL_SW_HILEN2(dclk_div >> 1) | |
|
- | 184 | UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | |
|
- | 185 | UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, |
|
- | 186 | ~UPLL_SW_MASK); |
|
- | 187 | ||
- | 188 | /* give the PLL some time to settle */ |
|
- | 189 | mdelay(15); |
|
- | 190 | ||
- | 191 | /* deassert PLL_RESET */ |
|
- | 192 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
|
- | 193 | ||
- | 194 | mdelay(15); |
|
- | 195 | ||
- | 196 | /* deassert BYPASS EN */ |
|
- | 197 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
|
- | 198 | ||
- | 199 | if (rdev->family >= CHIP_RS780) |
|
- | 200 | WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); |
|
- | 201 | ||
- | 202 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
|
- | 203 | if (r) |
|
- | 204 | return r; |
|
- | 205 | ||
- | 206 | /* switch VCLK and DCLK selection */ |
|
- | 207 | WREG32_P(CG_UPLL_FUNC_CNTL_2, |
|
- | 208 | VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), |
|
- | 209 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
- | 210 | ||
- | 211 | mdelay(100); |
|
124 | { |
212 | |
125 | return 0; |
213 | return 0; |
Line 126... | Line 214... | ||
126 | } |
214 | } |
127 | 215 | ||
Line 990... | Line 1078... | ||
990 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
1078 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
991 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
1079 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
992 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
1080 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
993 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
1081 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
994 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
1082 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
- | 1083 | WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); |
|
- | 1084 | WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); |
|
995 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
1085 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
996 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
1086 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
997 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
1087 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
998 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
1088 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
999 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
1089 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
Line 1040... | Line 1130... | ||
1040 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
1130 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
1041 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
1131 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
1042 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
1132 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
1043 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
1133 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
1044 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
1134 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
- | 1135 | WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); |
|
- | 1136 | WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); |
|
1045 | radeon_gart_table_vram_unpin(rdev); |
1137 | radeon_gart_table_vram_unpin(rdev); |
1046 | } |
1138 | } |
Line 1047... | Line 1139... | ||
1047 | 1139 | ||
1048 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
1140 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
Line 1336... | Line 1428... | ||
1336 | int r; |
1428 | int r; |
Line 1337... | Line 1429... | ||
1337 | 1429 | ||
1338 | if (rdev->vram_scratch.robj == NULL) { |
1430 | if (rdev->vram_scratch.robj == NULL) { |
1339 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
1431 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
1340 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
1432 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
1341 | 0, NULL, &rdev->vram_scratch.robj); |
1433 | 0, NULL, NULL, &rdev->vram_scratch.robj); |
1342 | if (r) { |
1434 | if (r) { |
1343 | return r; |
1435 | return r; |
1344 | } |
1436 | } |
Line 2790... | Line 2882... | ||
2790 | * |
2882 | * |
2791 | * Copy GPU paging using the CP DMA engine (r6xx+). |
2883 | * Copy GPU paging using the CP DMA engine (r6xx+). |
2792 | * Used by the radeon ttm implementation to move pages if |
2884 | * Used by the radeon ttm implementation to move pages if |
2793 | * registered as the asic copy callback. |
2885 | * registered as the asic copy callback. |
2794 | */ |
2886 | */ |
2795 | int r600_copy_cpdma(struct radeon_device *rdev, |
2887 | struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, |
2796 | uint64_t src_offset, uint64_t dst_offset, |
2888 | uint64_t src_offset, uint64_t dst_offset, |
2797 | unsigned num_gpu_pages, |
2889 | unsigned num_gpu_pages, |
2798 | struct radeon_fence **fence) |
2890 | struct reservation_object *resv) |
2799 | { |
2891 | { |
2800 | struct radeon_semaphore *sem = NULL; |
2892 | struct radeon_fence *fence; |
- | 2893 | struct radeon_sync sync; |
|
2801 | int ring_index = rdev->asic->copy.blit_ring_index; |
2894 | int ring_index = rdev->asic->copy.blit_ring_index; |
2802 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
2895 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
2803 | u32 size_in_bytes, cur_size_in_bytes, tmp; |
2896 | u32 size_in_bytes, cur_size_in_bytes, tmp; |
2804 | int i, num_loops; |
2897 | int i, num_loops; |
2805 | int r = 0; |
2898 | int r = 0; |
Line 2806... | Line 2899... | ||
2806 | 2899 | ||
2807 | r = radeon_semaphore_create(rdev, &sem); |
- | |
2808 | if (r) { |
- | |
2809 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
- | |
2810 | return r; |
- | |
Line 2811... | Line 2900... | ||
2811 | } |
2900 | radeon_sync_create(&sync); |
2812 | 2901 | ||
2813 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
2902 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
2814 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); |
2903 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); |
2815 | r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); |
2904 | r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); |
2816 | if (r) { |
2905 | if (r) { |
2817 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
2906 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
2818 | radeon_semaphore_free(rdev, &sem, NULL); |
2907 | radeon_sync_free(rdev, &sync, NULL); |
Line 2819... | Line 2908... | ||
2819 | return r; |
2908 | return ERR_PTR(r); |
2820 | } |
2909 | } |
Line 2821... | Line 2910... | ||
2821 | 2910 | ||
2822 | radeon_semaphore_sync_to(sem, *fence); |
2911 | radeon_sync_resv(rdev, &sync, resv, false); |
2823 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); |
2912 | radeon_sync_rings(rdev, &sync, ring->idx); |
2824 | 2913 | ||
Line 2844... | Line 2933... | ||
2844 | } |
2933 | } |
2845 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2934 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2846 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2935 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2847 | radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); |
2936 | radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); |
Line 2848... | Line 2937... | ||
2848 | 2937 | ||
2849 | r = radeon_fence_emit(rdev, fence, ring->idx); |
2938 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
2850 | if (r) { |
2939 | if (r) { |
2851 | radeon_ring_unlock_undo(rdev, ring); |
2940 | radeon_ring_unlock_undo(rdev, ring); |
2852 | radeon_semaphore_free(rdev, &sem, NULL); |
2941 | radeon_sync_free(rdev, &sync, NULL); |
2853 | return r; |
2942 | return ERR_PTR(r); |
Line 2854... | Line 2943... | ||
2854 | } |
2943 | } |
2855 | 2944 | ||
Line 2856... | Line 2945... | ||
2856 | radeon_ring_unlock_commit(rdev, ring, false); |
2945 | radeon_ring_unlock_commit(rdev, ring, false); |
2857 | radeon_semaphore_free(rdev, &sem, *fence); |
2946 | radeon_sync_free(rdev, &sync, fence); |
Line 2858... | Line 2947... | ||
2858 | 2947 | ||
2859 | return r; |
2948 | return fence; |
2860 | } |
2949 | } |
Line 3169... | Line 3258... | ||
3169 | /* Allocate ring buffer */ |
3258 | /* Allocate ring buffer */ |
3170 | if (rdev->ih.ring_obj == NULL) { |
3259 | if (rdev->ih.ring_obj == NULL) { |
3171 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
3260 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
3172 | PAGE_SIZE, true, |
3261 | PAGE_SIZE, true, |
3173 | RADEON_GEM_DOMAIN_GTT, 0, |
3262 | RADEON_GEM_DOMAIN_GTT, 0, |
3174 | NULL, &rdev->ih.ring_obj); |
3263 | NULL, NULL, &rdev->ih.ring_obj); |
3175 | if (r) { |
3264 | if (r) { |
3176 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
3265 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
3177 | return r; |
3266 | return r; |
3178 | } |
3267 | } |
3179 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
3268 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |