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| Rev 2004 | Rev 2005 | ||
|---|---|---|---|
| Line 1869... | Line 1869... | ||
| 1869 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); |
1869 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); |
| 1870 | radeon_ring_write(rdev, RB_INT_STAT); |
1870 | radeon_ring_write(rdev, RB_INT_STAT); |
| 1871 | } |
1871 | } |
| 1872 | } |
1872 | } |
| Line -... | Line 1873... | ||
| - | 1873 | ||
| - | 1874 | int r600_copy_blit(struct radeon_device *rdev, |
|
| - | 1875 | uint64_t src_offset, uint64_t dst_offset, |
|
| - | 1876 | unsigned num_pages, struct radeon_fence *fence) |
|
| - | 1877 | { |
|
| - | 1878 | int r; |
|
| - | 1879 | ||
| - | 1880 | mutex_lock(&rdev->r600_blit.mutex); |
|
| - | 1881 | rdev->r600_blit.vb_ib = NULL; |
|
| - | 1882 | r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
|
| - | 1883 | if (r) { |
|
| - | 1884 | // if (rdev->r600_blit.vb_ib) |
|
| - | 1885 | // radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
|
| - | 1886 | mutex_unlock(&rdev->r600_blit.mutex); |
|
| - | 1887 | return r; |
|
| - | 1888 | } |
|
| - | 1889 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
|
| - | 1890 | r600_blit_done_copy(rdev, fence); |
|
| - | 1891 | mutex_unlock(&rdev->r600_blit.mutex); |
|
| - | 1892 | return 0; |
|
| Line 1873... | Line 1893... | ||
| 1873 | 1893 | } |
|
| 1874 | 1894 | ||
| 1875 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
1895 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 1876 | uint32_t tiling_flags, uint32_t pitch, |
1896 | uint32_t tiling_flags, uint32_t pitch, |
| Line 1907... | Line 1927... | ||
| 1907 | r = r600_pcie_gart_enable(rdev); |
1927 | r = r600_pcie_gart_enable(rdev); |
| 1908 | if (r) |
1928 | if (r) |
| 1909 | return r; |
1929 | return r; |
| 1910 | } |
1930 | } |
| 1911 | r600_gpu_init(rdev); |
1931 | r600_gpu_init(rdev); |
| - | 1932 | r = r600_blit_init(rdev); |
|
| - | 1933 | if (r) { |
|
| - | 1934 | // r600_blit_fini(rdev); |
|
| - | 1935 | rdev->asic->copy = NULL; |
|
| - | 1936 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
|
| - | 1937 | } |
|
| - | 1938 | ||
| - | 1939 | /* allocate wb buffer */ |
|
| - | 1940 | r = radeon_wb_init(rdev); |
|
| - | 1941 | if (r) |
|
| - | 1942 | return r; |
|
| - | 1943 | ||
| - | 1944 | /* Enable IRQ */ |
|
| - | 1945 | r = r600_irq_init(rdev); |
|
| - | 1946 | if (r) { |
|
| - | 1947 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
|
| - | 1948 | // radeon_irq_kms_fini(rdev); |
|
| - | 1949 | return r; |
|
| - | 1950 | } |
|
| - | 1951 | r600_irq_set(rdev); |
|
| Line 1912... | Line 1952... | ||
| 1912 | 1952 | ||
| 1913 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1953 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| 1914 | if (r) |
1954 | if (r) |
| 1915 | return r; |
1955 | return r; |
| Line 2026... | Line 2066... | ||
| 2026 | // radeon_ring_fini(rdev); |
2066 | // radeon_ring_fini(rdev); |
| 2027 | r600_pcie_gart_fini(rdev); |
2067 | r600_pcie_gart_fini(rdev); |
| 2028 | rdev->accel_working = false; |
2068 | rdev->accel_working = false; |
| 2029 | } |
2069 | } |
| 2030 | if (rdev->accel_working) { |
2070 | if (rdev->accel_working) { |
| 2031 | // r = radeon_ib_pool_init(rdev); |
2071 | r = radeon_ib_pool_init(rdev); |
| 2032 | // if (r) { |
2072 | if (r) { |
| 2033 | // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
2073 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 2034 | // rdev->accel_working = false; |
2074 | rdev->accel_working = false; |
| 2035 | // } |
2075 | } else { |
| 2036 | // r = r600_ib_test(rdev); |
2076 | r = r600_ib_test(rdev); |
| 2037 | // if (r) { |
2077 | if (r) { |
| 2038 | // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
2078 | dev_err(rdev->dev, "IB test failed (%d).\n", r); |
| 2039 | // rdev->accel_working = false; |
2079 | rdev->accel_working = false; |
| 2040 | // } |
- | |
| 2041 | } |
2080 | } |
| 2042 | if (r) |
2081 | } |
| 2043 | return r; /* TODO error handling */ |
- | |
| - | 2082 | } |
|
| - | 2083 | ||
| 2044 | return 0; |
2084 | return 0; |
| 2045 | } |
2085 | } |
| Line 2046... | Line 2086... | ||
| 2046 | 2086 | ||
| 2047 | /* |
2087 | /* |
| Line 2421... | Line 2461... | ||
| 2421 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
2461 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
| 2422 | u32 grbm_int_cntl = 0; |
2462 | u32 grbm_int_cntl = 0; |
| 2423 | u32 hdmi1, hdmi2; |
2463 | u32 hdmi1, hdmi2; |
| 2424 | u32 d1grph = 0, d2grph = 0; |
2464 | u32 d1grph = 0, d2grph = 0; |
| Line 2425... | Line -... | ||
| 2425 | - | ||
| 2426 | ENTER(); |
- | |
| 2427 | 2465 | ||
| 2428 | if (!rdev->irq.installed) { |
2466 | if (!rdev->irq.installed) { |
| 2429 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
2467 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| 2430 | return -EINVAL; |
2468 | return -EINVAL; |
| 2431 | } |
2469 | } |
| Line 2528... | Line 2566... | ||
| 2528 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
2566 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
| 2529 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
2567 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
| 2530 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
2568 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
| 2531 | } |
2569 | } |
| Line 2532... | Line -... | ||
| 2532 | - | ||
| 2533 | LEAVE(); |
- | |
| 2534 | 2570 | ||
| 2535 | return 0; |
2571 | return 0; |
| Line 2536... | Line 2572... | ||
| 2536 | } |
2572 | } |
| 2537 | 2573 | ||
| Line 2823... | Line 2859... | ||
| 2823 | break; |
2859 | break; |
| 2824 | case 176: /* CP_INT in ring buffer */ |
2860 | case 176: /* CP_INT in ring buffer */ |
| 2825 | case 177: /* CP_INT in IB1 */ |
2861 | case 177: /* CP_INT in IB1 */ |
| 2826 | case 178: /* CP_INT in IB2 */ |
2862 | case 178: /* CP_INT in IB2 */ |
| 2827 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
2863 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
| 2828 | // radeon_fence_process(rdev); |
2864 | radeon_fence_process(rdev); |
| 2829 | break; |
2865 | break; |
| 2830 | case 181: /* CP EOP event */ |
2866 | case 181: /* CP EOP event */ |
| 2831 | DRM_DEBUG("IH: CP EOP\n"); |
2867 | DRM_DEBUG("IH: CP EOP\n"); |
| 2832 | // radeon_fence_process(rdev); |
2868 | radeon_fence_process(rdev); |
| 2833 | break; |
2869 | break; |
| 2834 | case 233: /* GUI IDLE */ |
2870 | case 233: /* GUI IDLE */ |
| 2835 | DRM_DEBUG("IH: GUI idle\n"); |
2871 | DRM_DEBUG("IH: GUI idle\n"); |
| 2836 | rdev->pm.gui_idle = true; |
2872 | rdev->pm.gui_idle = true; |
| 2837 | // wake_up(&rdev->irq.idle_queue); |
2873 | // wake_up(&rdev->irq.idle_queue); |