WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r600.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include 
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon.h"
#include "radeon_mode.h"
#include "r600d.h"
#include "atom.h"
#include "avivod.h"
 
#define PFP_UCODE_SIZE 576
#define PM4_UCODE_SIZE 1792
#define RLC_UCODE_SIZE 768
#define R700_PFP_UCODE_SIZE 848
#define R700_PM4_UCODE_SIZE 1360
#define R700_RLC_UCODE_SIZE 1024
 
/* Firmware Names */
MODULE_FIRMWARE("radeon/R600_pfp.bin");
MODULE_FIRMWARE("radeon/R600_me.bin");
MODULE_FIRMWARE("radeon/RV610_pfp.bin");
MODULE_FIRMWARE("radeon/RV610_me.bin");
MODULE_FIRMWARE("radeon/RV630_pfp.bin");
MODULE_FIRMWARE("radeon/RV630_me.bin");
MODULE_FIRMWARE("radeon/RV620_pfp.bin");
MODULE_FIRMWARE("radeon/RV620_me.bin");
MODULE_FIRMWARE("radeon/RV635_pfp.bin");
MODULE_FIRMWARE("radeon/RV635_me.bin");
MODULE_FIRMWARE("radeon/RV670_pfp.bin");
MODULE_FIRMWARE("radeon/RV670_me.bin");
MODULE_FIRMWARE("radeon/RS780_pfp.bin");
MODULE_FIRMWARE("radeon/RS780_me.bin");
MODULE_FIRMWARE("radeon/RV770_pfp.bin");
MODULE_FIRMWARE("radeon/RV770_me.bin");
MODULE_FIRMWARE("radeon/RV730_pfp.bin");
MODULE_FIRMWARE("radeon/RV730_me.bin");
MODULE_FIRMWARE("radeon/RV710_pfp.bin");
MODULE_FIRMWARE("radeon/RV710_me.bin");
MODULE_FIRMWARE("radeon/R600_rlc.bin");
MODULE_FIRMWARE("radeon/R700_rlc.bin");
 
int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 
/* r600,rv610,rv630,rv620,rv635,rv670 */
int r600_mc_wait_for_idle(struct radeon_device *rdev);
void r600_gpu_init(struct radeon_device *rdev);
void r600_fini(struct radeon_device *rdev);
 
/* hpd for digital panel detect/disconnect */
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
{
	bool connected = false;
 
	if (ASIC_IS_DCE3(rdev)) {
		switch (hpd) {
		case RADEON_HPD_1:
			if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_2:
			if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_3:
			if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_4:
			if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
			/* DCE 3.2 */
		case RADEON_HPD_5:
			if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_6:
			if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
				connected = true;
			break;
		default:
			break;
		}
	} else {
		switch (hpd) {
		case RADEON_HPD_1:
			if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_2:
			if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
				connected = true;
			break;
		case RADEON_HPD_3:
			if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
				connected = true;
			break;
		default:
			break;
		}
	}
	return connected;
}
 
void r600_hpd_set_polarity(struct radeon_device *rdev,
			   enum radeon_hpd_id hpd)
{
	u32 tmp;
	bool connected = r600_hpd_sense(rdev, hpd);
 
	if (ASIC_IS_DCE3(rdev)) {
		switch (hpd) {
		case RADEON_HPD_1:
			tmp = RREG32(DC_HPD1_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD1_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_2:
			tmp = RREG32(DC_HPD2_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD2_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_3:
			tmp = RREG32(DC_HPD3_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD3_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_4:
			tmp = RREG32(DC_HPD4_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD4_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_5:
			tmp = RREG32(DC_HPD5_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD5_INT_CONTROL, tmp);
			break;
			/* DCE 3.2 */
		case RADEON_HPD_6:
			tmp = RREG32(DC_HPD6_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HPDx_INT_POLARITY;
			else
				tmp |= DC_HPDx_INT_POLARITY;
			WREG32(DC_HPD6_INT_CONTROL, tmp);
			break;
		default:
			break;
		}
	} else {
		switch (hpd) {
		case RADEON_HPD_1:
			tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
			else
				tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
			WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_2:
			tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
			else
				tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
			WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
			break;
		case RADEON_HPD_3:
			tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
			if (connected)
				tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
			else
				tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
			WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
			break;
		default:
			break;
		}
	}
}
 
void r600_hpd_init(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
 
	if (ASIC_IS_DCE3(rdev)) {
		u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
		if (ASIC_IS_DCE32(rdev))
			tmp |= DC_HPDx_EN;
 
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
			switch (radeon_connector->hpd.hpd) {
			case RADEON_HPD_1:
				WREG32(DC_HPD1_CONTROL, tmp);
//               rdev->irq.hpd[0] = true;
				break;
			case RADEON_HPD_2:
				WREG32(DC_HPD2_CONTROL, tmp);
//               rdev->irq.hpd[1] = true;
				break;
			case RADEON_HPD_3:
				WREG32(DC_HPD3_CONTROL, tmp);
//               rdev->irq.hpd[2] = true;
				break;
			case RADEON_HPD_4:
				WREG32(DC_HPD4_CONTROL, tmp);
//               rdev->irq.hpd[3] = true;
				break;
				/* DCE 3.2 */
			case RADEON_HPD_5:
				WREG32(DC_HPD5_CONTROL, tmp);
//               rdev->irq.hpd[4] = true;
				break;
			case RADEON_HPD_6:
				WREG32(DC_HPD6_CONTROL, tmp);
//               rdev->irq.hpd[5] = true;
				break;
			default:
				break;
			}
		}
	} else {
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
			switch (radeon_connector->hpd.hpd) {
			case RADEON_HPD_1:
				WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
//               rdev->irq.hpd[0] = true;
				break;
			case RADEON_HPD_2:
				WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
//               rdev->irq.hpd[1] = true;
				break;
			case RADEON_HPD_3:
				WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
//               rdev->irq.hpd[2] = true;
				break;
			default:
				break;
			}
		}
	}
//   if (rdev->irq.installed)
//   r600_irq_set(rdev);
}
 
void r600_hpd_fini(struct radeon_device *rdev)
{
	struct drm_device *dev = rdev->ddev;
	struct drm_connector *connector;
 
	if (ASIC_IS_DCE3(rdev)) {
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
			switch (radeon_connector->hpd.hpd) {
			case RADEON_HPD_1:
				WREG32(DC_HPD1_CONTROL, 0);
//               rdev->irq.hpd[0] = false;
				break;
			case RADEON_HPD_2:
				WREG32(DC_HPD2_CONTROL, 0);
//               rdev->irq.hpd[1] = false;
				break;
			case RADEON_HPD_3:
				WREG32(DC_HPD3_CONTROL, 0);
//               rdev->irq.hpd[2] = false;
				break;
			case RADEON_HPD_4:
				WREG32(DC_HPD4_CONTROL, 0);
//               rdev->irq.hpd[3] = false;
				break;
				/* DCE 3.2 */
			case RADEON_HPD_5:
				WREG32(DC_HPD5_CONTROL, 0);
//               rdev->irq.hpd[4] = false;
				break;
			case RADEON_HPD_6:
				WREG32(DC_HPD6_CONTROL, 0);
//               rdev->irq.hpd[5] = false;
				break;
			default:
				break;
			}
		}
	} else {
		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
			switch (radeon_connector->hpd.hpd) {
			case RADEON_HPD_1:
				WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
//               rdev->irq.hpd[0] = false;
				break;
			case RADEON_HPD_2:
				WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
//               rdev->irq.hpd[1] = false;
				break;
			case RADEON_HPD_3:
				WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
//               rdev->irq.hpd[2] = false;
				break;
			default:
				break;
			}
		}
	}
}
 
/*
 * R600 PCIE GART
 */
int r600_gart_clear_page(struct radeon_device *rdev, int i)
{
	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
	u64 pte;
 
	if (i < 0 || i > rdev->gart.num_gpu_pages)
		return -EINVAL;
	pte = 0;
	writeq(pte, ((void __iomem *)ptr) + (i * 8));
	return 0;
}
 
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
{
	unsigned i;
	u32 tmp;
 
	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
		tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
		if (tmp == 2) {
			printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
			return;
		}
		if (tmp) {
			return;
		}
		udelay(1);
	}
}
 
int r600_pcie_gart_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->gart.table.vram.robj) {
		WARN(1, "R600 PCIE GART already initialized.\n");
		return 0;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r)
		return r;
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	return radeon_gart_table_vram_alloc(rdev);
}
 
int r600_pcie_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;
 
	if (rdev->gart.table.vram.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
 
	/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL2, 0);
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
	/* Setup TLB control */
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
		ENABLE_WAIT_L2_QUERY;
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
			(u32)(rdev->dummy_page.addr >> 12));
	for (i = 1; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
	r600_pcie_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}
 
void r600_pcie_gart_disable(struct radeon_device *rdev)
{
	u32 tmp;
	int i, r;
 
	/* Disable all tables */
	for (i = 0; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
	/* Disable L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
	/* Setup L1 TLB control */
	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
		ENABLE_WAIT_L2_QUERY;
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
	if (rdev->gart.table.vram.robj) {
		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rdev->gart.table.vram.robj);
			radeon_bo_unpin(rdev->gart.table.vram.robj);
			radeon_bo_unreserve(rdev->gart.table.vram.robj);
		}
	}
}
 
void r600_pcie_gart_fini(struct radeon_device *rdev)
{
	r600_pcie_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
	radeon_gart_fini(rdev);
}
 
void r600_agp_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int i;
 
	/* Setup L2 cache */
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
				EFFECTIVE_L2_QUEUE_SIZE(7));
	WREG32(VM_L2_CNTL2, 0);
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
	/* Setup TLB control */
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
		ENABLE_WAIT_L2_QUERY;
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
	for (i = 0; i < 7; i++)
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
}
 
int r600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	u32 tmp;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
		if (!tmp)
	return 0;
		udelay(1);
	}
	return -1;
}
 
static void r600_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 tmp;
	int i, j;
 
	/* Initialize HDP */
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		WREG32((0x2c14 + j), 0x00000000);
		WREG32((0x2c18 + j), 0x00000000);
		WREG32((0x2c1c + j), 0x00000000);
		WREG32((0x2c20 + j), 0x00000000);
		WREG32((0x2c24 + j), 0x00000000);
	}
	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
	rv515_mc_stop(rdev, &save);
	if (r600_mc_wait_for_idle(rdev)) {
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}
	/* Lockout access through VGA aperture (doesn't exist before R600) */
	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
	/* Update configuration */
	if (rdev->flags & RADEON_IS_AGP) {
		if (rdev->mc.vram_start < rdev->mc.gtt_start) {
			/* VRAM before AGP */
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
				rdev->mc.vram_start >> 12);
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
				rdev->mc.gtt_end >> 12);
		} else {
			/* VRAM after AGP */
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
				rdev->mc.gtt_start >> 12);
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
				rdev->mc.vram_end >> 12);
		}
	} else {
		WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
		WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
	}
	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
	WREG32(MC_VM_FB_LOCATION, tmp);
	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
	WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
	} else {
		WREG32(MC_VM_AGP_BASE, 0);
		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
	}
	if (r600_mc_wait_for_idle(rdev)) {
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}
	rv515_mc_resume(rdev, &save);
	/* we need to own VRAM, so turn off the VGA renderer here
	 * to stop it overwriting our objects */
	rv515_vga_render_disable(rdev);
}
 
int r600_mc_init(struct radeon_device *rdev)
{
	fixed20_12 a;
	u32 tmp;
	int chansize, numchan;
 
	/* Get VRAM informations */
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32(RAMCFG);
	if (tmp & CHANSIZE_OVERRIDE) {
		chansize = 16;
	} else if (tmp & CHANSIZE_MASK) {
		chansize = 64;
	} else {
		chansize = 32;
	}
	tmp = RREG32(CHMAP);
	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
	case 0:
	default:
		numchan = 1;
		break;
	case 1:
		numchan = 2;
		break;
	case 2:
		numchan = 4;
		break;
	case 3:
		numchan = 8;
		break;
	}
	rdev->mc.vram_width = numchan * chansize;
	/* Could aper size report 0 ? */
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
	/* Setup GPU memory space */
	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 
	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		rdev->mc.mc_vram_size = rdev->mc.aper_size;
 
	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		rdev->mc.real_vram_size = rdev->mc.aper_size;
 
	if (rdev->flags & RADEON_IS_AGP) {
		/* gtt_size is setup by radeon_agp_init */
		rdev->mc.gtt_location = rdev->mc.agp_base;
		tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
		/* Try to put vram before or after AGP because we
		 * we want SYSTEM_APERTURE to cover both VRAM and
		 * AGP so that GPU can catch out of VRAM/AGP access
		 */
		if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
			/* Enough place before */
			rdev->mc.vram_location = rdev->mc.gtt_location -
							rdev->mc.mc_vram_size;
		} else if (tmp > rdev->mc.mc_vram_size) {
			/* Enough place after */
			rdev->mc.vram_location = rdev->mc.gtt_location +
							rdev->mc.gtt_size;
		} else {
			/* Try to setup VRAM then AGP might not
			 * not work on some card
			 */
			rdev->mc.vram_location = 0x00000000UL;
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		}
	} else {
		rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
			rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
								0xFFFF) << 24;
			tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
				/* Enough place after vram */
				rdev->mc.gtt_location = tmp;
			} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
				/* Enough place before vram */
				rdev->mc.gtt_location = 0;
			} else {
				/* Not enough place after or before shrink
				 * gart size
				 */
				if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
					rdev->mc.gtt_location = 0;
					rdev->mc.gtt_size = rdev->mc.vram_location;
				} else {
					rdev->mc.gtt_location = tmp;
					rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
				}
			}
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
	}
	rdev->mc.vram_start = rdev->mc.vram_location;
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
	rdev->mc.gtt_start = rdev->mc.gtt_location;
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
	/* FIXME: we should enforce default clock in case GPU is not in
	 * default setup
	 */
	a.full = rfixed_const(100);
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 
	if (rdev->flags & RADEON_IS_IGP)
		rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 
	return 0;
}
 
/* We doesn't check that the GPU really needs a reset we simply do the
 * reset, it's up to the caller to determine if the GPU needs one. We
 * might add an helper function to check that.
 */
int r600_gpu_soft_reset(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
	u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
				S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
				S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
				S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
				S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
				S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
				S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
				S_008010_GUI_ACTIVE(1);
	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
			S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
			S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
			S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
			S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
			S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
			S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
			S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
	u32 srbm_reset = 0;
	u32 tmp;
 
	dev_info(rdev->dev, "GPU softreset \n");
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
		RREG32(R_008010_GRBM_STATUS));
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
		RREG32(R_008014_GRBM_STATUS2));
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
		RREG32(R_000E50_SRBM_STATUS));
	rv515_mc_stop(rdev, &save);
	if (r600_mc_wait_for_idle(rdev)) {
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
	}
	/* Disable CP parsing/prefetching */
	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
	/* Check if any of the rendering block is busy and reset it */
	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
	    (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
		tmp = S_008020_SOFT_RESET_CR(1) |
			S_008020_SOFT_RESET_DB(1) |
			S_008020_SOFT_RESET_CB(1) |
			S_008020_SOFT_RESET_PA(1) |
			S_008020_SOFT_RESET_SC(1) |
			S_008020_SOFT_RESET_SMX(1) |
			S_008020_SOFT_RESET_SPI(1) |
			S_008020_SOFT_RESET_SX(1) |
			S_008020_SOFT_RESET_SH(1) |
			S_008020_SOFT_RESET_TC(1) |
			S_008020_SOFT_RESET_TA(1) |
			S_008020_SOFT_RESET_VC(1) |
			S_008020_SOFT_RESET_VGT(1);
		dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(R_008020_GRBM_SOFT_RESET, tmp);
		(void)RREG32(R_008020_GRBM_SOFT_RESET);
		udelay(50);
		WREG32(R_008020_GRBM_SOFT_RESET, 0);
		(void)RREG32(R_008020_GRBM_SOFT_RESET);
	}
	/* Reset CP (we always reset CP) */
	tmp = S_008020_SOFT_RESET_CP(1);
	dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
	WREG32(R_008020_GRBM_SOFT_RESET, tmp);
	(void)RREG32(R_008020_GRBM_SOFT_RESET);
	udelay(50);
	WREG32(R_008020_GRBM_SOFT_RESET, 0);
	(void)RREG32(R_008020_GRBM_SOFT_RESET);
	/* Reset others GPU block if necessary */
	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
	if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
	if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_IH(1);
	if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
	if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
	if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
	if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
	if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
	if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
	if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
	if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
	dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
	udelay(50);
	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
	udelay(50);
	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
	/* Wait a little for things to settle down */
	udelay(50);
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
		RREG32(R_008010_GRBM_STATUS));
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
		RREG32(R_008014_GRBM_STATUS2));
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
		RREG32(R_000E50_SRBM_STATUS));
	/* After reset we need to reinit the asic as GPU often endup in an
	 * incoherent state.
	 */
	atom_asic_init(rdev->mode_info.atom_context);
	rv515_mc_resume(rdev, &save);
	return 0;
}
 
int r600_gpu_reset(struct radeon_device *rdev)
{
	return r600_gpu_soft_reset(rdev);
}
 
static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
					     u32 num_backends,
					     u32 backend_disable_mask)
{
	u32 backend_map = 0;
	u32 enabled_backends_mask;
	u32 enabled_backends_count;
	u32 cur_pipe;
	u32 swizzle_pipe[R6XX_MAX_PIPES];
	u32 cur_backend;
	u32 i;
 
	if (num_tile_pipes > R6XX_MAX_PIPES)
		num_tile_pipes = R6XX_MAX_PIPES;
	if (num_tile_pipes < 1)
		num_tile_pipes = 1;
	if (num_backends > R6XX_MAX_BACKENDS)
		num_backends = R6XX_MAX_BACKENDS;
	if (num_backends < 1)
		num_backends = 1;
 
	enabled_backends_mask = 0;
	enabled_backends_count = 0;
	for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
		if (((backend_disable_mask >> i) & 1) == 0) {
			enabled_backends_mask |= (1 << i);
			++enabled_backends_count;
		}
		if (enabled_backends_count == num_backends)
			break;
	}
 
	if (enabled_backends_count == 0) {
		enabled_backends_mask = 1;
		enabled_backends_count = 1;
	}
 
	if (enabled_backends_count != num_backends)
		num_backends = enabled_backends_count;
 
	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
	switch (num_tile_pipes) {
	case 1:
		swizzle_pipe[0] = 0;
		break;
	case 2:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 1;
		break;
	case 3:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 1;
		swizzle_pipe[2] = 2;
		break;
	case 4:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 1;
		swizzle_pipe[2] = 2;
		swizzle_pipe[3] = 3;
		break;
	case 5:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 1;
		swizzle_pipe[2] = 2;
		swizzle_pipe[3] = 3;
		swizzle_pipe[4] = 4;
		break;
	case 6:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 5;
		swizzle_pipe[4] = 1;
		swizzle_pipe[5] = 3;
		break;
	case 7:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 6;
		swizzle_pipe[4] = 1;
		swizzle_pipe[5] = 3;
		swizzle_pipe[6] = 5;
		break;
	case 8:
		swizzle_pipe[0] = 0;
		swizzle_pipe[1] = 2;
		swizzle_pipe[2] = 4;
		swizzle_pipe[3] = 6;
		swizzle_pipe[4] = 1;
		swizzle_pipe[5] = 3;
		swizzle_pipe[6] = 5;
		swizzle_pipe[7] = 7;
		break;
	}
 
	cur_backend = 0;
	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
		while (((1 << cur_backend) & enabled_backends_mask) == 0)
			cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 
		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 
		cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
	}
 
	return backend_map;
}
 
int r600_count_pipe_bits(uint32_t val)
{
	int i, ret = 0;
 
	for (i = 0; i < 32; i++) {
		ret += val & 1;
		val >>= 1;
	}
	return ret;
}
 
void r600_gpu_init(struct radeon_device *rdev)
{
	u32 tiling_config;
	u32 ramcfg;
	u32 tmp;
	int i, j;
	u32 sq_config;
	u32 sq_gpr_resource_mgmt_1 = 0;
	u32 sq_gpr_resource_mgmt_2 = 0;
	u32 sq_thread_resource_mgmt = 0;
	u32 sq_stack_resource_mgmt_1 = 0;
	u32 sq_stack_resource_mgmt_2 = 0;
 
	/* FIXME: implement */
	switch (rdev->family) {
	case CHIP_R600:
		rdev->config.r600.max_pipes = 4;
		rdev->config.r600.max_tile_pipes = 8;
		rdev->config.r600.max_simds = 4;
		rdev->config.r600.max_backends = 4;
		rdev->config.r600.max_gprs = 256;
		rdev->config.r600.max_threads = 192;
		rdev->config.r600.max_stack_entries = 256;
		rdev->config.r600.max_hw_contexts = 8;
		rdev->config.r600.max_gs_threads = 16;
		rdev->config.r600.sx_max_export_size = 128;
		rdev->config.r600.sx_max_export_pos_size = 16;
		rdev->config.r600.sx_max_export_smx_size = 128;
		rdev->config.r600.sq_num_cf_insts = 2;
		break;
	case CHIP_RV630:
	case CHIP_RV635:
		rdev->config.r600.max_pipes = 2;
		rdev->config.r600.max_tile_pipes = 2;
		rdev->config.r600.max_simds = 3;
		rdev->config.r600.max_backends = 1;
		rdev->config.r600.max_gprs = 128;
		rdev->config.r600.max_threads = 192;
		rdev->config.r600.max_stack_entries = 128;
		rdev->config.r600.max_hw_contexts = 8;
		rdev->config.r600.max_gs_threads = 4;
		rdev->config.r600.sx_max_export_size = 128;
		rdev->config.r600.sx_max_export_pos_size = 16;
		rdev->config.r600.sx_max_export_smx_size = 128;
		rdev->config.r600.sq_num_cf_insts = 2;
		break;
	case CHIP_RV610:
	case CHIP_RV620:
	case CHIP_RS780:
	case CHIP_RS880:
		rdev->config.r600.max_pipes = 1;
		rdev->config.r600.max_tile_pipes = 1;
		rdev->config.r600.max_simds = 2;
		rdev->config.r600.max_backends = 1;
		rdev->config.r600.max_gprs = 128;
		rdev->config.r600.max_threads = 192;
		rdev->config.r600.max_stack_entries = 128;
		rdev->config.r600.max_hw_contexts = 4;
		rdev->config.r600.max_gs_threads = 4;
		rdev->config.r600.sx_max_export_size = 128;
		rdev->config.r600.sx_max_export_pos_size = 16;
		rdev->config.r600.sx_max_export_smx_size = 128;
		rdev->config.r600.sq_num_cf_insts = 1;
		break;
	case CHIP_RV670:
		rdev->config.r600.max_pipes = 4;
		rdev->config.r600.max_tile_pipes = 4;
		rdev->config.r600.max_simds = 4;
		rdev->config.r600.max_backends = 4;
		rdev->config.r600.max_gprs = 192;
		rdev->config.r600.max_threads = 192;
		rdev->config.r600.max_stack_entries = 256;
		rdev->config.r600.max_hw_contexts = 8;
		rdev->config.r600.max_gs_threads = 16;
		rdev->config.r600.sx_max_export_size = 128;
		rdev->config.r600.sx_max_export_pos_size = 16;
		rdev->config.r600.sx_max_export_smx_size = 128;
		rdev->config.r600.sq_num_cf_insts = 2;
		break;
	default:
		break;
	}
 
	/* Initialize HDP */
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		WREG32((0x2c14 + j), 0x00000000);
		WREG32((0x2c18 + j), 0x00000000);
		WREG32((0x2c1c + j), 0x00000000);
		WREG32((0x2c20 + j), 0x00000000);
		WREG32((0x2c24 + j), 0x00000000);
	}
 
	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 
	/* Setup tiling */
	tiling_config = 0;
	ramcfg = RREG32(RAMCFG);
	switch (rdev->config.r600.max_tile_pipes) {
	case 1:
		tiling_config |= PIPE_TILING(0);
		break;
	case 2:
		tiling_config |= PIPE_TILING(1);
		break;
	case 4:
		tiling_config |= PIPE_TILING(2);
		break;
	case 8:
		tiling_config |= PIPE_TILING(3);
		break;
	default:
		break;
	}
	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
	tiling_config |= GROUP_SIZE(0);
	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
	if (tmp > 3) {
		tiling_config |= ROW_TILING(3);
		tiling_config |= SAMPLE_SPLIT(3);
	} else {
		tiling_config |= ROW_TILING(tmp);
		tiling_config |= SAMPLE_SPLIT(tmp);
	}
	tiling_config |= BANK_SWAPS(1);
	tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
						rdev->config.r600.max_backends,
						(0xff << rdev->config.r600.max_backends) & 0xff);
	tiling_config |= BACKEND_MAP(tmp);
	WREG32(GB_TILING_CONFIG, tiling_config);
	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 
	tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
	WREG32(CC_RB_BACKEND_DISABLE, tmp);
 
	/* Setup pipes */
	tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
	tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
	WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
 
	tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 
	/* Setup some CP states */
	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
	WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
 
	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
			     SYNC_WALKER | SYNC_ALIGNER));
	/* Setup various GPU states */
	if (rdev->family == CHIP_RV670)
		WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
 
	tmp = RREG32(SX_DEBUG_1);
	tmp |= SMX_EVENT_RELEASE;
	if ((rdev->family > CHIP_R600))
		tmp |= ENABLE_NEW_SMX_ADDRESS;
	WREG32(SX_DEBUG_1, tmp);
 
	if (((rdev->family) == CHIP_R600) ||
	    ((rdev->family) == CHIP_RV630) ||
	    ((rdev->family) == CHIP_RV610) ||
	    ((rdev->family) == CHIP_RV620) ||
	    ((rdev->family) == CHIP_RS780) ||
	    ((rdev->family) == CHIP_RS880)) {
		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
	} else {
		WREG32(DB_DEBUG, 0);
	}
	WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
			       DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
 
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
	WREG32(VGT_NUM_INSTANCES, 0);
 
	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 
	tmp = RREG32(SQ_MS_FIFO_SIZES);
	if (((rdev->family) == CHIP_RV610) ||
	    ((rdev->family) == CHIP_RV620) ||
	    ((rdev->family) == CHIP_RS780) ||
	    ((rdev->family) == CHIP_RS880)) {
		tmp = (CACHE_FIFO_SIZE(0xa) |
		       FETCH_FIFO_HIWATER(0xa) |
		       DONE_FIFO_HIWATER(0xe0) |
		       ALU_UPDATE_FIFO_HIWATER(0x8));
	} else if (((rdev->family) == CHIP_R600) ||
		   ((rdev->family) == CHIP_RV630)) {
		tmp &= ~DONE_FIFO_HIWATER(0xff);
		tmp |= DONE_FIFO_HIWATER(0x4);
	}
	WREG32(SQ_MS_FIFO_SIZES, tmp);
 
	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
	 */
	sq_config = RREG32(SQ_CONFIG);
	sq_config &= ~(PS_PRIO(3) |
		       VS_PRIO(3) |
		       GS_PRIO(3) |
		       ES_PRIO(3));
	sq_config |= (DX9_CONSTS |
		      VC_ENABLE |
		      PS_PRIO(0) |
		      VS_PRIO(1) |
		      GS_PRIO(2) |
		      ES_PRIO(3));
 
	if ((rdev->family) == CHIP_R600) {
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
					  NUM_VS_GPRS(124) |
					  NUM_CLAUSE_TEMP_GPRS(4));
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
					  NUM_ES_GPRS(0));
		sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
					   NUM_VS_THREADS(48) |
					   NUM_GS_THREADS(4) |
					   NUM_ES_THREADS(4));
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
					    NUM_VS_STACK_ENTRIES(128));
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
					    NUM_ES_STACK_ENTRIES(0));
	} else if (((rdev->family) == CHIP_RV610) ||
		   ((rdev->family) == CHIP_RV620) ||
		   ((rdev->family) == CHIP_RS780) ||
		   ((rdev->family) == CHIP_RS880)) {
		/* no vertex cache */
		sq_config &= ~VC_ENABLE;
 
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
					  NUM_VS_GPRS(44) |
					  NUM_CLAUSE_TEMP_GPRS(2));
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
					  NUM_ES_GPRS(17));
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
					   NUM_VS_THREADS(78) |
					   NUM_GS_THREADS(4) |
					   NUM_ES_THREADS(31));
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
					    NUM_VS_STACK_ENTRIES(40));
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
					    NUM_ES_STACK_ENTRIES(16));
	} else if (((rdev->family) == CHIP_RV630) ||
		   ((rdev->family) == CHIP_RV635)) {
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
					  NUM_VS_GPRS(44) |
					  NUM_CLAUSE_TEMP_GPRS(2));
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
					  NUM_ES_GPRS(18));
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
					   NUM_VS_THREADS(78) |
					   NUM_GS_THREADS(4) |
					   NUM_ES_THREADS(31));
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
					    NUM_VS_STACK_ENTRIES(40));
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
					    NUM_ES_STACK_ENTRIES(16));
	} else if ((rdev->family) == CHIP_RV670) {
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
					  NUM_VS_GPRS(44) |
					  NUM_CLAUSE_TEMP_GPRS(2));
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
					  NUM_ES_GPRS(17));
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
					   NUM_VS_THREADS(78) |
					   NUM_GS_THREADS(4) |
					   NUM_ES_THREADS(31));
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
					    NUM_VS_STACK_ENTRIES(64));
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
					    NUM_ES_STACK_ENTRIES(64));
	}
 
	WREG32(SQ_CONFIG, sq_config);
	WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
	WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 
	if (((rdev->family) == CHIP_RV610) ||
	    ((rdev->family) == CHIP_RV620) ||
	    ((rdev->family) == CHIP_RS780) ||
	    ((rdev->family) == CHIP_RS880)) {
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
	} else {
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
	}
 
	/* More default values. 2D/3D driver should adjust as needed */
	WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
					 S1_X(0x4) | S1_Y(0xc)));
	WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
					 S1_X(0x2) | S1_Y(0x2) |
					 S2_X(0xa) | S2_Y(0x6) |
					 S3_X(0x6) | S3_Y(0xa)));
	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
					     S1_X(0x4) | S1_Y(0xc) |
					     S2_X(0x1) | S2_Y(0x6) |
					     S3_X(0xa) | S3_Y(0xe)));
	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
					     S5_X(0x0) | S5_Y(0x0) |
					     S6_X(0xb) | S6_Y(0x4) |
					     S7_X(0x7) | S7_Y(0x8)));
 
	WREG32(VGT_STRMOUT_EN, 0);
	tmp = rdev->config.r600.max_pipes * 16;
	switch (rdev->family) {
	case CHIP_RV610:
	case CHIP_RV620:
	case CHIP_RS780:
	case CHIP_RS880:
		tmp += 32;
		break;
	case CHIP_RV670:
		tmp += 128;
		break;
	default:
		break;
	}
	if (tmp > 256) {
		tmp = 256;
	}
	WREG32(VGT_ES_PER_GS, 128);
	WREG32(VGT_GS_PER_ES, tmp);
	WREG32(VGT_GS_PER_VS, 2);
	WREG32(VGT_GS_VERTEX_REUSE, 16);
 
	/* more default values. 2D/3D driver should adjust as needed */
	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
	WREG32(VGT_STRMOUT_EN, 0);
	WREG32(SX_MISC, 0);
	WREG32(PA_SC_MODE_CNTL, 0);
	WREG32(PA_SC_AA_CONFIG, 0);
	WREG32(PA_SC_LINE_STIPPLE, 0);
	WREG32(SPI_INPUT_Z, 0);
	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
	WREG32(CB_COLOR7_FRAG, 0);
 
	/* Clear render buffer base addresses */
	WREG32(CB_COLOR0_BASE, 0);
	WREG32(CB_COLOR1_BASE, 0);
	WREG32(CB_COLOR2_BASE, 0);
	WREG32(CB_COLOR3_BASE, 0);
	WREG32(CB_COLOR4_BASE, 0);
	WREG32(CB_COLOR5_BASE, 0);
	WREG32(CB_COLOR6_BASE, 0);
	WREG32(CB_COLOR7_BASE, 0);
	WREG32(CB_COLOR7_FRAG, 0);
 
	switch (rdev->family) {
	case CHIP_RV610:
	case CHIP_RV620:
	case CHIP_RS780:
	case CHIP_RS880:
		tmp = TC_L2_SIZE(8);
		break;
	case CHIP_RV630:
	case CHIP_RV635:
		tmp = TC_L2_SIZE(4);
		break;
	case CHIP_R600:
		tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
		break;
	default:
		tmp = TC_L2_SIZE(0);
		break;
	}
	WREG32(TC_CNTL, tmp);
 
	tmp = RREG32(HDP_HOST_PATH_CNTL);
	WREG32(HDP_HOST_PATH_CNTL, tmp);
 
	tmp = RREG32(ARB_POP);
	tmp |= ENABLE_TC128;
	WREG32(ARB_POP, tmp);
 
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
			       NUM_CLIP_SEQ(3)));
	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
}
 
 
/*
 * Indirect registers accessor
 */
u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
{
	u32 r;
 
	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
	(void)RREG32(PCIE_PORT_INDEX);
	r = RREG32(PCIE_PORT_DATA);
	return r;
}
 
void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
	(void)RREG32(PCIE_PORT_INDEX);
	WREG32(PCIE_PORT_DATA, (v));
	(void)RREG32(PCIE_PORT_DATA);
}
 
/*
 * CP & Ring
 */
void r600_cp_stop(struct radeon_device *rdev)
{
	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
}
 
int r600_init_microcode(struct radeon_device *rdev)
{
	struct platform_device *pdev;
	const char *chip_name;
	const char *rlc_chip_name;
	size_t pfp_req_size, me_req_size, rlc_req_size;
	char fw_name[30];
	int err;
 
	DRM_DEBUG("\n");
 
	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
	err = IS_ERR(pdev);
	if (err) {
		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		return -EINVAL;
	}
 
	switch (rdev->family) {
	case CHIP_R600:
		chip_name = "R600";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV610:
		chip_name = "RV610";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV630:
		chip_name = "RV630";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV620:
		chip_name = "RV620";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV635:
		chip_name = "RV635";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV670:
		chip_name = "RV670";
		rlc_chip_name = "R600";
		break;
	case CHIP_RS780:
	case CHIP_RS880:
		chip_name = "RS780";
		rlc_chip_name = "R600";
		break;
	case CHIP_RV770:
		chip_name = "RV770";
		rlc_chip_name = "R700";
		break;
	case CHIP_RV730:
	case CHIP_RV740:
		chip_name = "RV730";
		rlc_chip_name = "R700";
		break;
	case CHIP_RV710:
		chip_name = "RV710";
		rlc_chip_name = "R700";
		break;
	default: BUG();
	}
 
	if (rdev->family >= CHIP_RV770) {
		pfp_req_size = R700_PFP_UCODE_SIZE * 4;
		me_req_size = R700_PM4_UCODE_SIZE * 4;
		rlc_req_size = R700_RLC_UCODE_SIZE * 4;
	} else {
		pfp_req_size = PFP_UCODE_SIZE * 4;
		me_req_size = PM4_UCODE_SIZE * 12;
		rlc_req_size = RLC_UCODE_SIZE * 4;
	}
 
	DRM_INFO("Loading %s Microcode\n", chip_name);
 
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
	err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
	if (err)
		goto out;
	if (rdev->pfp_fw->size != pfp_req_size) {
		printk(KERN_ERR
		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
		       rdev->pfp_fw->size, fw_name);
		err = -EINVAL;
		goto out;
	}
 
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
	if (err)
		goto out;
	if (rdev->me_fw->size != me_req_size) {
		printk(KERN_ERR
		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
		       rdev->me_fw->size, fw_name);
		err = -EINVAL;
	}
 
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
	err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
	if (err)
		goto out;
	if (rdev->rlc_fw->size != rlc_req_size) {
		printk(KERN_ERR
		       "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
		       rdev->rlc_fw->size, fw_name);
		err = -EINVAL;
	}
 
out:
	platform_device_unregister(pdev);
 
	if (err) {
		if (err != -EINVAL)
			printk(KERN_ERR
			       "r600_cp: Failed to load firmware \"%s\"\n",
			       fw_name);
		release_firmware(rdev->pfp_fw);
		rdev->pfp_fw = NULL;
		release_firmware(rdev->me_fw);
		rdev->me_fw = NULL;
		release_firmware(rdev->rlc_fw);
		rdev->rlc_fw = NULL;
	}
	return err;
}
 
static int r600_cp_load_microcode(struct radeon_device *rdev)
{
	const __be32 *fw_data;
	int i;
 
	if (!rdev->me_fw || !rdev->pfp_fw)
		return -EINVAL;
 
	r600_cp_stop(rdev);
 
	WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
 
	/* Reset cp */
	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
	RREG32(GRBM_SOFT_RESET);
	mdelay(15);
	WREG32(GRBM_SOFT_RESET, 0);
 
	WREG32(CP_ME_RAM_WADDR, 0);
 
	fw_data = (const __be32 *)rdev->me_fw->data;
	WREG32(CP_ME_RAM_WADDR, 0);
	for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
		WREG32(CP_ME_RAM_DATA,
		       be32_to_cpup(fw_data++));
 
	fw_data = (const __be32 *)rdev->pfp_fw->data;
	WREG32(CP_PFP_UCODE_ADDR, 0);
	for (i = 0; i < PFP_UCODE_SIZE; i++)
		WREG32(CP_PFP_UCODE_DATA,
		       be32_to_cpup(fw_data++));
 
	WREG32(CP_PFP_UCODE_ADDR, 0);
	WREG32(CP_ME_RAM_WADDR, 0);
	WREG32(CP_ME_RAM_RADDR, 0);
	return 0;
}
 
int r600_cp_start(struct radeon_device *rdev)
{
	int r;
	uint32_t cp_me;
 
	r = radeon_ring_lock(rdev, 7);
	if (r) {
		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		return r;
	}
	radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
	radeon_ring_write(rdev, 0x1);
	if (rdev->family < CHIP_RV770) {
		radeon_ring_write(rdev, 0x3);
		radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
	} else {
		radeon_ring_write(rdev, 0x0);
		radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
	}
	radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
	radeon_ring_write(rdev, 0);
	radeon_ring_write(rdev, 0);
	radeon_ring_unlock_commit(rdev);
 
	cp_me = 0xff;
	WREG32(R_0086D8_CP_ME_CNTL, cp_me);
	return 0;
}
 
int r600_cp_resume(struct radeon_device *rdev)
{
	u32 tmp;
	u32 rb_bufsz;
	int r;
 
	/* Reset cp */
	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
	RREG32(GRBM_SOFT_RESET);
	mdelay(15);
	WREG32(GRBM_SOFT_RESET, 0);
 
	/* Set ring buffer size */
	rb_bufsz = drm_order(rdev->cp.ring_size / 8);
	tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
	tmp |= BUF_SWAP_32BIT;
#endif
	WREG32(CP_RB_CNTL, tmp);
	WREG32(CP_SEM_WAIT_TIMER, 0x4);
 
	/* Set the write pointer delay */
	WREG32(CP_RB_WPTR_DELAY, 0);
 
	/* Initialize the ring buffer's read and write pointers */
	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
	WREG32(CP_RB_RPTR_WR, 0);
	WREG32(CP_RB_WPTR, 0);
	WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
	mdelay(1);
	WREG32(CP_RB_CNTL, tmp);
 
	WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
	rdev->cp.rptr = RREG32(CP_RB_RPTR);
	rdev->cp.wptr = RREG32(CP_RB_WPTR);
 
	r600_cp_start(rdev);
	rdev->cp.ready = true;
	r = radeon_ring_test(rdev);
	if (r) {
		rdev->cp.ready = false;
		return r;
	}
	return 0;
}
 
void r600_cp_commit(struct radeon_device *rdev)
{
	WREG32(CP_RB_WPTR, rdev->cp.wptr);
	(void)RREG32(CP_RB_WPTR);
}
 
void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
{
	u32 rb_bufsz;
 
	/* Align ring size */
	rb_bufsz = drm_order(ring_size / 8);
	ring_size = (1 << (rb_bufsz + 1)) * 4;
	rdev->cp.ring_size = ring_size;
	rdev->cp.align_mask = 16 - 1;
}
 
 
/*
 * GPU scratch registers helpers function.
 */
void r600_scratch_init(struct radeon_device *rdev)
{
	int i;
 
	rdev->scratch.num_reg = 7;
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		rdev->scratch.free[i] = true;
		rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
	}
}
 
int r600_ring_test(struct radeon_device *rdev)
{
	uint32_t scratch;
	uint32_t tmp = 0;
	unsigned i;
	int r;
 
	r = radeon_scratch_get(rdev, &scratch);
	if (r) {
		DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		return r;
	}
	WREG32(scratch, 0xCAFEDEAD);
	r = radeon_ring_lock(rdev, 3);
	if (r) {
		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		radeon_scratch_free(rdev, scratch);
		return r;
	}
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
	radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
	radeon_ring_write(rdev, 0xDEADBEEF);
	radeon_ring_unlock_commit(rdev);
	for (i = 0; i < rdev->usec_timeout; i++) {
		tmp = RREG32(scratch);
		if (tmp == 0xDEADBEEF)
			break;
		DRM_UDELAY(1);
	}
	if (i < rdev->usec_timeout) {
		DRM_INFO("ring test succeeded in %d usecs\n", i);
	} else {
		DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
			  scratch, tmp);
		r = -EINVAL;
	}
	radeon_scratch_free(rdev, scratch);
	return r;
}
void r600_fence_ring_emit(struct radeon_device *rdev,
			  struct radeon_fence *fence)
{
	/* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
	/* Emit fence sequence & fire IRQ */
	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
	radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
	radeon_ring_write(rdev, fence->seq);
	radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
	radeon_ring_write(rdev, 1);
	/* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
	radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
	radeon_ring_write(rdev, RB_INT_STAT);
}
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size)
{
	/* FIXME: implement */
	return 0;
}
 
void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
{
	/* FIXME: implement */
}
 
 
bool r600_card_posted(struct radeon_device *rdev)
{
	uint32_t reg;
 
	/* first check CRTCs */
	reg = RREG32(D1CRTC_CONTROL) |
		RREG32(D2CRTC_CONTROL);
	if (reg & CRTC_EN)
		return true;
 
	/* then check MEM_SIZE, in case the crtcs are off */
	if (RREG32(CONFIG_MEMSIZE))
		return true;
 
	return false;
}
 
int r600_startup(struct radeon_device *rdev)
{
	int r;
 
	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
		r = r600_init_microcode(rdev);
		if (r) {
			DRM_ERROR("Failed to load firmware!\n");
			return r;
		}
	}
 
	r600_mc_program(rdev);
	if (rdev->flags & RADEON_IS_AGP) {
		r600_agp_enable(rdev);
	} else {
		r = r600_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	r600_gpu_init(rdev);
 
 
 
 
 
 
 
 
	r = radeon_ring_init(rdev, rdev->cp.ring_size);
	if (r)
		return r;
	r = r600_cp_load_microcode(rdev);
	if (r)
		return r;
	r = r600_cp_resume(rdev);
	if (r)
		return r;
	/* write back buffer are not vital so don't worry about failure */
//	r600_wb_enable(rdev);
	return 0;
}
 
void r600_vga_set_state(struct radeon_device *rdev, bool state)
{
	uint32_t temp;
 
	temp = RREG32(CONFIG_CNTL);
	if (state == false) {
		temp &= ~(1<<0);
		temp |= (1<<1);
	} else {
		temp &= ~(1<<1);
	}
	WREG32(CONFIG_CNTL, temp);
}
 
 
 
 
 
/* Plan is to move initialization in that function and use
 * helper function so that radeon_device_init pretty much
 * do nothing more than calling asic specific function. This
 * should also allow to remove a bunch of callback function
 * like vram_info.
 */
int r600_init(struct radeon_device *rdev)
{
	int r;
 
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	if (r600_debugfs_mc_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for mc !\n");
	}
	/* This don't do much */
	r = radeon_gem_init(rdev);
	if (r)
		return r;
	/* Read BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	/* Must be an ATOMBIOS */
	if (!rdev->is_atom_bios) {
		dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
		return -EINVAL;
	}
	r = radeon_atombios_init(rdev);
	if (r)
		return r;
	/* Post card if necessary */
	if (!r600_card_posted(rdev)) {
		if (!rdev->bios) {
			dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
			return -EINVAL;
		}
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize scratch registers */
	r600_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	r = radeon_clocks_init(rdev);
	if (r)
		return r;
	/* Initialize power management */
	radeon_pm_init(rdev);
	/* Fence driver */
//	r = radeon_fence_driver_init(rdev);
//	if (r)
//		return r;
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r)
			radeon_agp_disable(rdev);
	}
	r = r600_mc_init(rdev);
    dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
 
//	r = radeon_irq_kms_init(rdev);
//	if (r)
//		return r;
 
	rdev->cp.ring_obj = NULL;
	r600_ring_init(rdev, 1024 * 1024);
 
//	rdev->ih.ring_obj = NULL;
//	r600_ih_ring_init(rdev, 64 * 1024);
 
	r = r600_pcie_gart_init(rdev);
	if (r)
		return r;
 
 
 
 
 
 
 
	rdev->accel_working = true;
	r = r600_startup(rdev);
	if (r) {
//		r600_suspend(rdev);
//		r600_wb_fini(rdev);
//		radeon_ring_fini(rdev);
		r600_pcie_gart_fini(rdev);
		rdev->accel_working = false;
	}
	if (rdev->accel_working) {
//		r = radeon_ib_pool_init(rdev);
//		if (r) {
//			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
//			rdev->accel_working = false;
//		}
//		r = r600_ib_test(rdev);
//		if (r) {
//			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
//			rdev->accel_working = false;
//		}
	}
	return 0;
}
 
 
 
 
 
 
 
 
 
/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
 
static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	unsigned count, i, j;
 
	radeon_ring_free_size(rdev);
	count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
	seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
	seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
	seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
	seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
	seq_printf(m, "%u dwords in ring\n", count);
	i = rdev->cp.rptr;
	for (j = 0; j <= count; j++) {
		seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		i = (i + 1) & rdev->cp.ptr_mask;
	}
	return 0;
}
 
static int r600_debugfs_mc_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
 
	DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
	DREG32_SYS(m, rdev, VM_L2_STATUS);
	return 0;
}
 
static struct drm_info_list r600_mc_info_list[] = {
	{"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
	{"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
};
#endif
 
int r600_debugfs_mc_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
#else
	return 0;
#endif
}
 
/**
 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
 * rdev: radeon device structure
 * bo: buffer object struct which userspace is waiting for idle
 *
 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
 * through ring buffer, this leads to corruption in rendering, see
 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
 * directly perform HDP flush by writing register through MMIO.
 */
void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
{
	WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
}
>
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Rev 1404	Rev 1413
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include	29	#include
30	#include "drmP.h"	30	#include "drmP.h"
31	#include "radeon_drm.h"	31	#include "radeon_drm.h"
32	#include "radeon.h"	32	#include "radeon.h"
33	#include "radeon_mode.h"	33	#include "radeon_mode.h"
34	#include "r600d.h"	34	#include "r600d.h"
35	#include "atom.h"	35	#include "atom.h"
36	#include "avivod.h"	36	#include "avivod.h"
37		37
38	#define PFP_UCODE_SIZE 576	38	#define PFP_UCODE_SIZE 576
39	#define PM4_UCODE_SIZE 1792	39	#define PM4_UCODE_SIZE 1792
40	#define RLC_UCODE_SIZE 768	40	#define RLC_UCODE_SIZE 768
41	#define R700_PFP_UCODE_SIZE 848	41	#define R700_PFP_UCODE_SIZE 848
42	#define R700_PM4_UCODE_SIZE 1360	42	#define R700_PM4_UCODE_SIZE 1360
43	#define R700_RLC_UCODE_SIZE 1024	43	#define R700_RLC_UCODE_SIZE 1024
44		44
45	/* Firmware Names */	45	/* Firmware Names */
46	MODULE_FIRMWARE("radeon/R600_pfp.bin");	46	MODULE_FIRMWARE("radeon/R600_pfp.bin");
47	MODULE_FIRMWARE("radeon/R600_me.bin");	47	MODULE_FIRMWARE("radeon/R600_me.bin");
48	MODULE_FIRMWARE("radeon/RV610_pfp.bin");	48	MODULE_FIRMWARE("radeon/RV610_pfp.bin");
49	MODULE_FIRMWARE("radeon/RV610_me.bin");	49	MODULE_FIRMWARE("radeon/RV610_me.bin");
50	MODULE_FIRMWARE("radeon/RV630_pfp.bin");	50	MODULE_FIRMWARE("radeon/RV630_pfp.bin");
51	MODULE_FIRMWARE("radeon/RV630_me.bin");	51	MODULE_FIRMWARE("radeon/RV630_me.bin");
52	MODULE_FIRMWARE("radeon/RV620_pfp.bin");	52	MODULE_FIRMWARE("radeon/RV620_pfp.bin");
53	MODULE_FIRMWARE("radeon/RV620_me.bin");	53	MODULE_FIRMWARE("radeon/RV620_me.bin");
54	MODULE_FIRMWARE("radeon/RV635_pfp.bin");	54	MODULE_FIRMWARE("radeon/RV635_pfp.bin");
55	MODULE_FIRMWARE("radeon/RV635_me.bin");	55	MODULE_FIRMWARE("radeon/RV635_me.bin");
56	MODULE_FIRMWARE("radeon/RV670_pfp.bin");	56	MODULE_FIRMWARE("radeon/RV670_pfp.bin");
57	MODULE_FIRMWARE("radeon/RV670_me.bin");	57	MODULE_FIRMWARE("radeon/RV670_me.bin");
58	MODULE_FIRMWARE("radeon/RS780_pfp.bin");	58	MODULE_FIRMWARE("radeon/RS780_pfp.bin");
59	MODULE_FIRMWARE("radeon/RS780_me.bin");	59	MODULE_FIRMWARE("radeon/RS780_me.bin");
60	MODULE_FIRMWARE("radeon/RV770_pfp.bin");	60	MODULE_FIRMWARE("radeon/RV770_pfp.bin");
61	MODULE_FIRMWARE("radeon/RV770_me.bin");	61	MODULE_FIRMWARE("radeon/RV770_me.bin");
62	MODULE_FIRMWARE("radeon/RV730_pfp.bin");	62	MODULE_FIRMWARE("radeon/RV730_pfp.bin");
63	MODULE_FIRMWARE("radeon/RV730_me.bin");	63	MODULE_FIRMWARE("radeon/RV730_me.bin");
64	MODULE_FIRMWARE("radeon/RV710_pfp.bin");	64	MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65	MODULE_FIRMWARE("radeon/RV710_me.bin");	65	MODULE_FIRMWARE("radeon/RV710_me.bin");
66	MODULE_FIRMWARE("radeon/R600_rlc.bin");	66	MODULE_FIRMWARE("radeon/R600_rlc.bin");
67	MODULE_FIRMWARE("radeon/R700_rlc.bin");	67	MODULE_FIRMWARE("radeon/R700_rlc.bin");
68		68
69	int r600_debugfs_mc_info_init(struct radeon_device *rdev);	69	int r600_debugfs_mc_info_init(struct radeon_device *rdev);
70		70
71	/* r600,rv610,rv630,rv620,rv635,rv670 */	71	/* r600,rv610,rv630,rv620,rv635,rv670 */
72	int r600_mc_wait_for_idle(struct radeon_device *rdev);	72	int r600_mc_wait_for_idle(struct radeon_device *rdev);
73	void r600_gpu_init(struct radeon_device *rdev);	73	void r600_gpu_init(struct radeon_device *rdev);
74	void r600_fini(struct radeon_device *rdev);	74	void r600_fini(struct radeon_device *rdev);
75		75
76	/* hpd for digital panel detect/disconnect */	76	/* hpd for digital panel detect/disconnect */
77	bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)	77	bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
78	{	78	{
79	bool connected = false;	79	bool connected = false;
80		80
81	if (ASIC_IS_DCE3(rdev)) {	81	if (ASIC_IS_DCE3(rdev)) {
82	switch (hpd) {	82	switch (hpd) {
83	case RADEON_HPD_1:	83	case RADEON_HPD_1:
84	if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)	84	if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
85	connected = true;	85	connected = true;
86	break;	86	break;
87	case RADEON_HPD_2:	87	case RADEON_HPD_2:
88	if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)	88	if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
89	connected = true;	89	connected = true;
90	break;	90	break;
91	case RADEON_HPD_3:	91	case RADEON_HPD_3:
92	if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)	92	if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
93	connected = true;	93	connected = true;
94	break;	94	break;
95	case RADEON_HPD_4:	95	case RADEON_HPD_4:
96	if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)	96	if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
97	connected = true;	97	connected = true;
98	break;	98	break;
99	/* DCE 3.2 */	99	/* DCE 3.2 */
100	case RADEON_HPD_5:	100	case RADEON_HPD_5:
101	if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)	101	if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
102	connected = true;	102	connected = true;
103	break;	103	break;
104	case RADEON_HPD_6:	104	case RADEON_HPD_6:
105	if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)	105	if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
106	connected = true;	106	connected = true;
107	break;	107	break;
108	default:	108	default:
109	break;	109	break;
110	}	110	}
111	} else {	111	} else {
112	switch (hpd) {	112	switch (hpd) {
113	case RADEON_HPD_1:	113	case RADEON_HPD_1:
114	if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)	114	if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
115	connected = true;	115	connected = true;
116	break;	116	break;
117	case RADEON_HPD_2:	117	case RADEON_HPD_2:
118	if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)	118	if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
119	connected = true;	119	connected = true;
120	break;	120	break;
121	case RADEON_HPD_3:	121	case RADEON_HPD_3:
122	if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)	122	if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
123	connected = true;	123	connected = true;
124	break;	124	break;
125	default:	125	default:
126	break;	126	break;
127	}	127	}
128	}	128	}
129	return connected;	129	return connected;
130	}	130	}
131		131
132	void r600_hpd_set_polarity(struct radeon_device *rdev,	132	void r600_hpd_set_polarity(struct radeon_device *rdev,
133	enum radeon_hpd_id hpd)	133	enum radeon_hpd_id hpd)
134	{	134	{
135	u32 tmp;	135	u32 tmp;
136	bool connected = r600_hpd_sense(rdev, hpd);	136	bool connected = r600_hpd_sense(rdev, hpd);
137		137
138	if (ASIC_IS_DCE3(rdev)) {	138	if (ASIC_IS_DCE3(rdev)) {
139	switch (hpd) {	139	switch (hpd) {
140	case RADEON_HPD_1:	140	case RADEON_HPD_1:
141	tmp = RREG32(DC_HPD1_INT_CONTROL);	141	tmp = RREG32(DC_HPD1_INT_CONTROL);
142	if (connected)	142	if (connected)
143	tmp &= ~DC_HPDx_INT_POLARITY;	143	tmp &= ~DC_HPDx_INT_POLARITY;
144	else	144	else
145	tmp \|= DC_HPDx_INT_POLARITY;	145	tmp \|= DC_HPDx_INT_POLARITY;
146	WREG32(DC_HPD1_INT_CONTROL, tmp);	146	WREG32(DC_HPD1_INT_CONTROL, tmp);
147	break;	147	break;
148	case RADEON_HPD_2:	148	case RADEON_HPD_2:
149	tmp = RREG32(DC_HPD2_INT_CONTROL);	149	tmp = RREG32(DC_HPD2_INT_CONTROL);
150	if (connected)	150	if (connected)
151	tmp &= ~DC_HPDx_INT_POLARITY;	151	tmp &= ~DC_HPDx_INT_POLARITY;
152	else	152	else
153	tmp \|= DC_HPDx_INT_POLARITY;	153	tmp \|= DC_HPDx_INT_POLARITY;
154	WREG32(DC_HPD2_INT_CONTROL, tmp);	154	WREG32(DC_HPD2_INT_CONTROL, tmp);
155	break;	155	break;
156	case RADEON_HPD_3:	156	case RADEON_HPD_3:
157	tmp = RREG32(DC_HPD3_INT_CONTROL);	157	tmp = RREG32(DC_HPD3_INT_CONTROL);
158	if (connected)	158	if (connected)
159	tmp &= ~DC_HPDx_INT_POLARITY;	159	tmp &= ~DC_HPDx_INT_POLARITY;
160	else	160	else
161	tmp \|= DC_HPDx_INT_POLARITY;	161	tmp \|= DC_HPDx_INT_POLARITY;
162	WREG32(DC_HPD3_INT_CONTROL, tmp);	162	WREG32(DC_HPD3_INT_CONTROL, tmp);
163	break;	163	break;
164	case RADEON_HPD_4:	164	case RADEON_HPD_4:
165	tmp = RREG32(DC_HPD4_INT_CONTROL);	165	tmp = RREG32(DC_HPD4_INT_CONTROL);
166	if (connected)	166	if (connected)
167	tmp &= ~DC_HPDx_INT_POLARITY;	167	tmp &= ~DC_HPDx_INT_POLARITY;
168	else	168	else
169	tmp \|= DC_HPDx_INT_POLARITY;	169	tmp \|= DC_HPDx_INT_POLARITY;
170	WREG32(DC_HPD4_INT_CONTROL, tmp);	170	WREG32(DC_HPD4_INT_CONTROL, tmp);
171	break;	171	break;
172	case RADEON_HPD_5:	172	case RADEON_HPD_5:
173	tmp = RREG32(DC_HPD5_INT_CONTROL);	173	tmp = RREG32(DC_HPD5_INT_CONTROL);
174	if (connected)	174	if (connected)
175	tmp &= ~DC_HPDx_INT_POLARITY;	175	tmp &= ~DC_HPDx_INT_POLARITY;
176	else	176	else
177	tmp \|= DC_HPDx_INT_POLARITY;	177	tmp \|= DC_HPDx_INT_POLARITY;
178	WREG32(DC_HPD5_INT_CONTROL, tmp);	178	WREG32(DC_HPD5_INT_CONTROL, tmp);
179	break;	179	break;
180	/* DCE 3.2 */	180	/* DCE 3.2 */
181	case RADEON_HPD_6:	181	case RADEON_HPD_6:
182	tmp = RREG32(DC_HPD6_INT_CONTROL);	182	tmp = RREG32(DC_HPD6_INT_CONTROL);
183	if (connected)	183	if (connected)
184	tmp &= ~DC_HPDx_INT_POLARITY;	184	tmp &= ~DC_HPDx_INT_POLARITY;
185	else	185	else
186	tmp \|= DC_HPDx_INT_POLARITY;	186	tmp \|= DC_HPDx_INT_POLARITY;
187	WREG32(DC_HPD6_INT_CONTROL, tmp);	187	WREG32(DC_HPD6_INT_CONTROL, tmp);
188	break;	188	break;
189	default:	189	default:
190	break;	190	break;
191	}	191	}
192	} else {	192	} else {
193	switch (hpd) {	193	switch (hpd) {
194	case RADEON_HPD_1:	194	case RADEON_HPD_1:
195	tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);	195	tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
196	if (connected)	196	if (connected)
197	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;	197	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
198	else	198	else
199	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;	199	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
200	WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);	200	WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
201	break;	201	break;
202	case RADEON_HPD_2:	202	case RADEON_HPD_2:
203	tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);	203	tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
204	if (connected)	204	if (connected)
205	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;	205	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
206	else	206	else
207	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;	207	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
208	WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);	208	WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
209	break;	209	break;
210	case RADEON_HPD_3:	210	case RADEON_HPD_3:
211	tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);	211	tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
212	if (connected)	212	if (connected)
213	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;	213	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
214	else	214	else
215	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;	215	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
216	WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);	216	WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
217	break;	217	break;
218	default:	218	default:
219	break;	219	break;
220	}	220	}
221	}	221	}
222	}	222	}
223		223
224	void r600_hpd_init(struct radeon_device *rdev)	224	void r600_hpd_init(struct radeon_device *rdev)
225	{	225	{
226	struct drm_device *dev = rdev->ddev;	226	struct drm_device *dev = rdev->ddev;
227	struct drm_connector *connector;	227	struct drm_connector *connector;
228		228
229	if (ASIC_IS_DCE3(rdev)) {	229	if (ASIC_IS_DCE3(rdev)) {
230	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) \| DC_HPDx_RX_INT_TIMER(0xfa);	230	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) \| DC_HPDx_RX_INT_TIMER(0xfa);
231	if (ASIC_IS_DCE32(rdev))	231	if (ASIC_IS_DCE32(rdev))
232	tmp \|= DC_HPDx_EN;	232	tmp \|= DC_HPDx_EN;
233		233
234	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	234	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
235	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	235	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
236	switch (radeon_connector->hpd.hpd) {	236	switch (radeon_connector->hpd.hpd) {
237	case RADEON_HPD_1:	237	case RADEON_HPD_1:
238	WREG32(DC_HPD1_CONTROL, tmp);	238	WREG32(DC_HPD1_CONTROL, tmp);
239	// rdev->irq.hpd[0] = true;	239	// rdev->irq.hpd[0] = true;
240	break;	240	break;
241	case RADEON_HPD_2:	241	case RADEON_HPD_2:
242	WREG32(DC_HPD2_CONTROL, tmp);	242	WREG32(DC_HPD2_CONTROL, tmp);
243	// rdev->irq.hpd[1] = true;	243	// rdev->irq.hpd[1] = true;
244	break;	244	break;
245	case RADEON_HPD_3:	245	case RADEON_HPD_3:
246	WREG32(DC_HPD3_CONTROL, tmp);	246	WREG32(DC_HPD3_CONTROL, tmp);
247	// rdev->irq.hpd[2] = true;	247	// rdev->irq.hpd[2] = true;
248	break;	248	break;
249	case RADEON_HPD_4:	249	case RADEON_HPD_4:
250	WREG32(DC_HPD4_CONTROL, tmp);	250	WREG32(DC_HPD4_CONTROL, tmp);
251	// rdev->irq.hpd[3] = true;	251	// rdev->irq.hpd[3] = true;
252	break;	252	break;
253	/* DCE 3.2 */	253	/* DCE 3.2 */
254	case RADEON_HPD_5:	254	case RADEON_HPD_5:
255	WREG32(DC_HPD5_CONTROL, tmp);	255	WREG32(DC_HPD5_CONTROL, tmp);
256	// rdev->irq.hpd[4] = true;	256	// rdev->irq.hpd[4] = true;
257	break;	257	break;
258	case RADEON_HPD_6:	258	case RADEON_HPD_6:
259	WREG32(DC_HPD6_CONTROL, tmp);	259	WREG32(DC_HPD6_CONTROL, tmp);
260	// rdev->irq.hpd[5] = true;	260	// rdev->irq.hpd[5] = true;
261	break;	261	break;
262	default:	262	default:
263	break;	263	break;
264	}	264	}
265	}	265	}
266	} else {	266	} else {
267	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	267	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
268	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	268	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
269	switch (radeon_connector->hpd.hpd) {	269	switch (radeon_connector->hpd.hpd) {
270	case RADEON_HPD_1:	270	case RADEON_HPD_1:
271	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);	271	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
272	// rdev->irq.hpd[0] = true;	272	// rdev->irq.hpd[0] = true;
273	break;	273	break;
274	case RADEON_HPD_2:	274	case RADEON_HPD_2:
275	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);	275	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
276	// rdev->irq.hpd[1] = true;	276	// rdev->irq.hpd[1] = true;
277	break;	277	break;
278	case RADEON_HPD_3:	278	case RADEON_HPD_3:
279	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);	279	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
280	// rdev->irq.hpd[2] = true;	280	// rdev->irq.hpd[2] = true;
281	break;	281	break;
282	default:	282	default:
283	break;	283	break;
284	}	284	}
285	}	285	}
286	}	286	}
287	// if (rdev->irq.installed)	287	// if (rdev->irq.installed)
288	// r600_irq_set(rdev);	288	// r600_irq_set(rdev);
289	}	289	}
290		290
291	void r600_hpd_fini(struct radeon_device *rdev)	291	void r600_hpd_fini(struct radeon_device *rdev)
292	{	292	{
293	struct drm_device *dev = rdev->ddev;	293	struct drm_device *dev = rdev->ddev;
294	struct drm_connector *connector;	294	struct drm_connector *connector;
295		295
296	if (ASIC_IS_DCE3(rdev)) {	296	if (ASIC_IS_DCE3(rdev)) {
297	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	297	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
298	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	298	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
299	switch (radeon_connector->hpd.hpd) {	299	switch (radeon_connector->hpd.hpd) {
300	case RADEON_HPD_1:	300	case RADEON_HPD_1:
301	WREG32(DC_HPD1_CONTROL, 0);	301	WREG32(DC_HPD1_CONTROL, 0);
302	// rdev->irq.hpd[0] = false;	302	// rdev->irq.hpd[0] = false;
303	break;	303	break;
304	case RADEON_HPD_2:	304	case RADEON_HPD_2:
305	WREG32(DC_HPD2_CONTROL, 0);	305	WREG32(DC_HPD2_CONTROL, 0);
306	// rdev->irq.hpd[1] = false;	306	// rdev->irq.hpd[1] = false;
307	break;	307	break;
308	case RADEON_HPD_3:	308	case RADEON_HPD_3:
309	WREG32(DC_HPD3_CONTROL, 0);	309	WREG32(DC_HPD3_CONTROL, 0);
310	// rdev->irq.hpd[2] = false;	310	// rdev->irq.hpd[2] = false;
311	break;	311	break;
312	case RADEON_HPD_4:	312	case RADEON_HPD_4:
313	WREG32(DC_HPD4_CONTROL, 0);	313	WREG32(DC_HPD4_CONTROL, 0);
314	// rdev->irq.hpd[3] = false;	314	// rdev->irq.hpd[3] = false;
315	break;	315	break;
316	/* DCE 3.2 */	316	/* DCE 3.2 */
317	case RADEON_HPD_5:	317	case RADEON_HPD_5:
318	WREG32(DC_HPD5_CONTROL, 0);	318	WREG32(DC_HPD5_CONTROL, 0);
319	// rdev->irq.hpd[4] = false;	319	// rdev->irq.hpd[4] = false;
320	break;	320	break;
321	case RADEON_HPD_6:	321	case RADEON_HPD_6:
322	WREG32(DC_HPD6_CONTROL, 0);	322	WREG32(DC_HPD6_CONTROL, 0);
323	// rdev->irq.hpd[5] = false;	323	// rdev->irq.hpd[5] = false;
324	break;	324	break;
325	default:	325	default:
326	break;	326	break;
327	}	327	}
328	}	328	}
329	} else {	329	} else {
330	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {	330	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
331	struct radeon_connector *radeon_connector = to_radeon_connector(connector);	331	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
332	switch (radeon_connector->hpd.hpd) {	332	switch (radeon_connector->hpd.hpd) {
333	case RADEON_HPD_1:	333	case RADEON_HPD_1:
334	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);	334	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
335	// rdev->irq.hpd[0] = false;	335	// rdev->irq.hpd[0] = false;
336	break;	336	break;
337	case RADEON_HPD_2:	337	case RADEON_HPD_2:
338	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);	338	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
339	// rdev->irq.hpd[1] = false;	339	// rdev->irq.hpd[1] = false;
340	break;	340	break;
341	case RADEON_HPD_3:	341	case RADEON_HPD_3:
342	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);	342	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
343	// rdev->irq.hpd[2] = false;	343	// rdev->irq.hpd[2] = false;
344	break;	344	break;
345	default:	345	default:
346	break;	346	break;
347	}	347	}
348	}	348	}
349	}	349	}
350	}	350	}
351		351
352	/*	352	/*
353	* R600 PCIE GART	353	* R600 PCIE GART
354	*/	354	*/
355	int r600_gart_clear_page(struct radeon_device *rdev, int i)	355	int r600_gart_clear_page(struct radeon_device *rdev, int i)
356	{	356	{
357	void __iomem ptr = (void )rdev->gart.table.vram.ptr;	357	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
358	u64 pte;	358	u64 pte;
359		359
360	if (i < 0 \|\| i > rdev->gart.num_gpu_pages)	360	if (i < 0 \|\| i > rdev->gart.num_gpu_pages)
361	return -EINVAL;	361	return -EINVAL;
362	pte = 0;	362	pte = 0;
363	writeq(pte, ((void __iomem )ptr) + (i 8));	363	writeq(pte, ((void __iomem )ptr) + (i 8));
364	return 0;	364	return 0;
365	}	365	}
366		366
367	void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)	367	void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
368	{	368	{
369	unsigned i;	369	unsigned i;
370	u32 tmp;	370	u32 tmp;
371		371
372	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);	372	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
373	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);	373	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
374	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));	374	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
375	for (i = 0; i < rdev->usec_timeout; i++) {	375	for (i = 0; i < rdev->usec_timeout; i++) {
376	/* read MC_STATUS */	376	/* read MC_STATUS */
377	tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);	377	tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
378	tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;	378	tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
379	if (tmp == 2) {	379	if (tmp == 2) {
380	printk(KERN_WARNING "[drm] r600 flush TLB failed\n");	380	printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
381	return;	381	return;
382	}	382	}
383	if (tmp) {	383	if (tmp) {
384	return;	384	return;
385	}	385	}
386	udelay(1);	386	udelay(1);
387	}	387	}
388	}	388	}
389		389
390	int r600_pcie_gart_init(struct radeon_device *rdev)	390	int r600_pcie_gart_init(struct radeon_device *rdev)
391	{	391	{
392	int r;	392	int r;
393		393
394	if (rdev->gart.table.vram.robj) {	394	if (rdev->gart.table.vram.robj) {
395	WARN(1, "R600 PCIE GART already initialized.\n");	395	WARN(1, "R600 PCIE GART already initialized.\n");
396	return 0;	396	return 0;
397	}	397	}
398	/* Initialize common gart structure */	398	/* Initialize common gart structure */
399	r = radeon_gart_init(rdev);	399	r = radeon_gart_init(rdev);
400	if (r)	400	if (r)
401	return r;	401	return r;
402	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;	402	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
403	return radeon_gart_table_vram_alloc(rdev);	403	return radeon_gart_table_vram_alloc(rdev);
404	}	404	}
405		405
406	int r600_pcie_gart_enable(struct radeon_device *rdev)	406	int r600_pcie_gart_enable(struct radeon_device *rdev)
407	{	407	{
408	u32 tmp;	408	u32 tmp;
409	int r, i;	409	int r, i;
410		410
411	if (rdev->gart.table.vram.robj == NULL) {	411	if (rdev->gart.table.vram.robj == NULL) {
412	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");	412	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
413	return -EINVAL;	413	return -EINVAL;
414	}	414	}
415	r = radeon_gart_table_vram_pin(rdev);	415	r = radeon_gart_table_vram_pin(rdev);
416	if (r)	416	if (r)
417	return r;	417	return r;
418		418
419	/* Setup L2 cache */	419	/* Setup L2 cache */
420	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|	420	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
421	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|	421	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
422	EFFECTIVE_L2_QUEUE_SIZE(7));	422	EFFECTIVE_L2_QUEUE_SIZE(7));
423	WREG32(VM_L2_CNTL2, 0);	423	WREG32(VM_L2_CNTL2, 0);
424	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));	424	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));
425	/* Setup TLB control */	425	/* Setup TLB control */
426	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|	426	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
427	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|	427	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
428	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|	428	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|
429	ENABLE_WAIT_L2_QUERY;	429	ENABLE_WAIT_L2_QUERY;
430	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);	430	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
431	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);	431	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
432	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp \| ENABLE_L1_STRICT_ORDERING);	432	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp \| ENABLE_L1_STRICT_ORDERING);
433	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);	433	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
434	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);	434	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
435	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);	435	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
436	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);	436	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
437	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);	437	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
438	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);	438	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
439	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);	439	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
440	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);	440	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
441	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);	441	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
442	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);	442	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
443	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);	443	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
444	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);	444	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
445	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);	445	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
446	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);	446	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
447	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|	447	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|
448	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);	448	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
449	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,	449	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
450	(u32)(rdev->dummy_page.addr >> 12));	450	(u32)(rdev->dummy_page.addr >> 12));
451	for (i = 1; i < 7; i++)	451	for (i = 1; i < 7; i++)
452	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);	452	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
453		453
454	r600_pcie_gart_tlb_flush(rdev);	454	r600_pcie_gart_tlb_flush(rdev);
455	rdev->gart.ready = true;	455	rdev->gart.ready = true;
456	return 0;	456	return 0;
457	}	457	}
458		458
459	void r600_pcie_gart_disable(struct radeon_device *rdev)	459	void r600_pcie_gart_disable(struct radeon_device *rdev)
460	{	460	{
461	u32 tmp;	461	u32 tmp;
462	int i, r;	462	int i, r;
463		463
464	/* Disable all tables */	464	/* Disable all tables */
465	for (i = 0; i < 7; i++)	465	for (i = 0; i < 7; i++)
466	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);	466	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
467		467
468	/* Disable L2 cache */	468	/* Disable L2 cache */
469	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|	469	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|
470	EFFECTIVE_L2_QUEUE_SIZE(7));	470	EFFECTIVE_L2_QUEUE_SIZE(7));
471	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));	471	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));
472	/* Setup L1 TLB control */	472	/* Setup L1 TLB control */
473	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|	473	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|
474	ENABLE_WAIT_L2_QUERY;	474	ENABLE_WAIT_L2_QUERY;
475	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);	475	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
476	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);	476	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
477	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);	477	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
478	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);	478	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
479	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);	479	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
480	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);	480	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
481	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);	481	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
482	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);	482	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
483	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);	483	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
484	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);	484	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
485	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);	485	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
486	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);	486	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
487	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);	487	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
488	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);	488	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
489	if (rdev->gart.table.vram.robj) {	489	if (rdev->gart.table.vram.robj) {
490	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);	490	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
491	if (likely(r == 0)) {	491	if (likely(r == 0)) {
492	radeon_bo_kunmap(rdev->gart.table.vram.robj);	492	radeon_bo_kunmap(rdev->gart.table.vram.robj);
493	radeon_bo_unpin(rdev->gart.table.vram.robj);	493	radeon_bo_unpin(rdev->gart.table.vram.robj);
494	radeon_bo_unreserve(rdev->gart.table.vram.robj);	494	radeon_bo_unreserve(rdev->gart.table.vram.robj);
495	}	495	}
496	}	496	}
497	}	497	}
498		498
499	void r600_pcie_gart_fini(struct radeon_device *rdev)	499	void r600_pcie_gart_fini(struct radeon_device *rdev)
500	{	500	{

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r600.c – Rev 1404 → 1413