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| Rev 1404 | Rev 1413 | ||
|---|---|---|---|
| Line 1389... | Line 1389... | ||
| 1389 | */ |
1389 | */ |
| 1390 | void r600_cp_stop(struct radeon_device *rdev) |
1390 | void r600_cp_stop(struct radeon_device *rdev) |
| 1391 | { |
1391 | { |
| 1392 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
1392 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
| 1393 | } |
1393 | } |
| - | 1394 | ||
| - | 1395 | int r600_init_microcode(struct radeon_device *rdev) |
|
| - | 1396 | { |
|
| - | 1397 | struct platform_device *pdev; |
|
| - | 1398 | const char *chip_name; |
|
| - | 1399 | const char *rlc_chip_name; |
|
| - | 1400 | size_t pfp_req_size, me_req_size, rlc_req_size; |
|
| - | 1401 | char fw_name[30]; |
|
| - | 1402 | int err; |
|
| - | 1403 | ||
| - | 1404 | DRM_DEBUG("\n"); |
|
| - | 1405 | ||
| - | 1406 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
|
| - | 1407 | err = IS_ERR(pdev); |
|
| - | 1408 | if (err) { |
|
| - | 1409 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
|
| - | 1410 | return -EINVAL; |
|
| - | 1411 | } |
|
| - | 1412 | ||
| - | 1413 | switch (rdev->family) { |
|
| - | 1414 | case CHIP_R600: |
|
| - | 1415 | chip_name = "R600"; |
|
| - | 1416 | rlc_chip_name = "R600"; |
|
| - | 1417 | break; |
|
| - | 1418 | case CHIP_RV610: |
|
| - | 1419 | chip_name = "RV610"; |
|
| - | 1420 | rlc_chip_name = "R600"; |
|
| - | 1421 | break; |
|
| - | 1422 | case CHIP_RV630: |
|
| - | 1423 | chip_name = "RV630"; |
|
| - | 1424 | rlc_chip_name = "R600"; |
|
| - | 1425 | break; |
|
| - | 1426 | case CHIP_RV620: |
|
| - | 1427 | chip_name = "RV620"; |
|
| - | 1428 | rlc_chip_name = "R600"; |
|
| - | 1429 | break; |
|
| - | 1430 | case CHIP_RV635: |
|
| - | 1431 | chip_name = "RV635"; |
|
| - | 1432 | rlc_chip_name = "R600"; |
|
| - | 1433 | break; |
|
| - | 1434 | case CHIP_RV670: |
|
| - | 1435 | chip_name = "RV670"; |
|
| - | 1436 | rlc_chip_name = "R600"; |
|
| - | 1437 | break; |
|
| - | 1438 | case CHIP_RS780: |
|
| - | 1439 | case CHIP_RS880: |
|
| - | 1440 | chip_name = "RS780"; |
|
| - | 1441 | rlc_chip_name = "R600"; |
|
| - | 1442 | break; |
|
| - | 1443 | case CHIP_RV770: |
|
| - | 1444 | chip_name = "RV770"; |
|
| - | 1445 | rlc_chip_name = "R700"; |
|
| - | 1446 | break; |
|
| - | 1447 | case CHIP_RV730: |
|
| - | 1448 | case CHIP_RV740: |
|
| - | 1449 | chip_name = "RV730"; |
|
| - | 1450 | rlc_chip_name = "R700"; |
|
| - | 1451 | break; |
|
| - | 1452 | case CHIP_RV710: |
|
| - | 1453 | chip_name = "RV710"; |
|
| - | 1454 | rlc_chip_name = "R700"; |
|
| - | 1455 | break; |
|
| - | 1456 | default: BUG(); |
|
| - | 1457 | } |
|
| - | 1458 | ||
| - | 1459 | if (rdev->family >= CHIP_RV770) { |
|
| - | 1460 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
|
| - | 1461 | me_req_size = R700_PM4_UCODE_SIZE * 4; |
|
| - | 1462 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
|
| - | 1463 | } else { |
|
| - | 1464 | pfp_req_size = PFP_UCODE_SIZE * 4; |
|
| - | 1465 | me_req_size = PM4_UCODE_SIZE * 12; |
|
| - | 1466 | rlc_req_size = RLC_UCODE_SIZE * 4; |
|
| - | 1467 | } |
|
| - | 1468 | ||
| - | 1469 | DRM_INFO("Loading %s Microcode\n", chip_name); |
|
| - | 1470 | ||
| - | 1471 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
|
| - | 1472 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
|
| - | 1473 | if (err) |
|
| - | 1474 | goto out; |
|
| - | 1475 | if (rdev->pfp_fw->size != pfp_req_size) { |
|
| - | 1476 | printk(KERN_ERR |
|
| - | 1477 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
|
| - | 1478 | rdev->pfp_fw->size, fw_name); |
|
| - | 1479 | err = -EINVAL; |
|
| - | 1480 | goto out; |
|
| - | 1481 | } |
|
| - | 1482 | ||
| - | 1483 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
|
| - | 1484 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
|
| - | 1485 | if (err) |
|
| - | 1486 | goto out; |
|
| - | 1487 | if (rdev->me_fw->size != me_req_size) { |
|
| - | 1488 | printk(KERN_ERR |
|
| - | 1489 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
|
| - | 1490 | rdev->me_fw->size, fw_name); |
|
| - | 1491 | err = -EINVAL; |
|
| - | 1492 | } |
|
| - | 1493 | ||
| - | 1494 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
|
| - | 1495 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
|
| - | 1496 | if (err) |
|
| - | 1497 | goto out; |
|
| - | 1498 | if (rdev->rlc_fw->size != rlc_req_size) { |
|
| - | 1499 | printk(KERN_ERR |
|
| - | 1500 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", |
|
| - | 1501 | rdev->rlc_fw->size, fw_name); |
|
| - | 1502 | err = -EINVAL; |
|
| - | 1503 | } |
|
| - | 1504 | ||
| - | 1505 | out: |
|
| - | 1506 | platform_device_unregister(pdev); |
|
| - | 1507 | ||
| - | 1508 | if (err) { |
|
| - | 1509 | if (err != -EINVAL) |
|
| - | 1510 | printk(KERN_ERR |
|
| - | 1511 | "r600_cp: Failed to load firmware \"%s\"\n", |
|
| - | 1512 | fw_name); |
|
| - | 1513 | release_firmware(rdev->pfp_fw); |
|
| - | 1514 | rdev->pfp_fw = NULL; |
|
| - | 1515 | release_firmware(rdev->me_fw); |
|
| - | 1516 | rdev->me_fw = NULL; |
|
| - | 1517 | release_firmware(rdev->rlc_fw); |
|
| - | 1518 | rdev->rlc_fw = NULL; |
|
| - | 1519 | } |
|
| - | 1520 | return err; |
|
| - | 1521 | } |
|
| - | 1522 | ||
| - | 1523 | static int r600_cp_load_microcode(struct radeon_device *rdev) |
|
| - | 1524 | { |
|
| - | 1525 | const __be32 *fw_data; |
|
| - | 1526 | int i; |
|
| - | 1527 | ||
| - | 1528 | if (!rdev->me_fw || !rdev->pfp_fw) |
|
| - | 1529 | return -EINVAL; |
|
| - | 1530 | ||
| - | 1531 | r600_cp_stop(rdev); |
|
| - | 1532 | ||
| - | 1533 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
|
| - | 1534 | ||
| - | 1535 | /* Reset cp */ |
|
| - | 1536 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
|
| - | 1537 | RREG32(GRBM_SOFT_RESET); |
|
| - | 1538 | mdelay(15); |
|
| - | 1539 | WREG32(GRBM_SOFT_RESET, 0); |
|
| - | 1540 | ||
| - | 1541 | WREG32(CP_ME_RAM_WADDR, 0); |
|
| - | 1542 | ||
| - | 1543 | fw_data = (const __be32 *)rdev->me_fw->data; |
|
| - | 1544 | WREG32(CP_ME_RAM_WADDR, 0); |
|
| - | 1545 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) |
|
| - | 1546 | WREG32(CP_ME_RAM_DATA, |
|
| - | 1547 | be32_to_cpup(fw_data++)); |
|
| - | 1548 | ||
| - | 1549 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
|
| - | 1550 | WREG32(CP_PFP_UCODE_ADDR, 0); |
|
| - | 1551 | for (i = 0; i < PFP_UCODE_SIZE; i++) |
|
| - | 1552 | WREG32(CP_PFP_UCODE_DATA, |
|
| - | 1553 | be32_to_cpup(fw_data++)); |
|
| - | 1554 | ||
| - | 1555 | WREG32(CP_PFP_UCODE_ADDR, 0); |
|
| - | 1556 | WREG32(CP_ME_RAM_WADDR, 0); |
|
| - | 1557 | WREG32(CP_ME_RAM_RADDR, 0); |
|
| - | 1558 | return 0; |
|
| - | 1559 | } |
|
| - | 1560 | ||
| 1394 | int r600_cp_start(struct radeon_device *rdev) |
1561 | int r600_cp_start(struct radeon_device *rdev) |
| 1395 | { |
1562 | { |
| 1396 | int r; |
1563 | int r; |
| 1397 | uint32_t cp_me; |
1564 | uint32_t cp_me; |
| Line 1417... | Line 1584... | ||
| 1417 | 1584 | ||
| 1418 | cp_me = 0xff; |
1585 | cp_me = 0xff; |
| 1419 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
1586 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
| 1420 | return 0; |
1587 | return 0; |
| - | 1588 | } |
|
| - | 1589 | ||
| - | 1590 | int r600_cp_resume(struct radeon_device *rdev) |
|
| - | 1591 | { |
|
| - | 1592 | u32 tmp; |
|
| - | 1593 | u32 rb_bufsz; |
|
| - | 1594 | int r; |
|
| - | 1595 | ||
| - | 1596 | /* Reset cp */ |
|
| - | 1597 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
|
| - | 1598 | RREG32(GRBM_SOFT_RESET); |
|
| - | 1599 | mdelay(15); |
|
| - | 1600 | WREG32(GRBM_SOFT_RESET, 0); |
|
| - | 1601 | ||
| - | 1602 | /* Set ring buffer size */ |
|
| - | 1603 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
|
| - | 1604 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
|
| - | 1605 | #ifdef __BIG_ENDIAN |
|
| - | 1606 | tmp |= BUF_SWAP_32BIT; |
|
| - | 1607 | #endif |
|
| - | 1608 | WREG32(CP_RB_CNTL, tmp); |
|
| - | 1609 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
|
| - | 1610 | ||
| - | 1611 | /* Set the write pointer delay */ |
|
| - | 1612 | WREG32(CP_RB_WPTR_DELAY, 0); |
|
| - | 1613 | ||
| - | 1614 | /* Initialize the ring buffer's read and write pointers */ |
|
| - | 1615 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
|
| - | 1616 | WREG32(CP_RB_RPTR_WR, 0); |
|
| - | 1617 | WREG32(CP_RB_WPTR, 0); |
|
| - | 1618 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); |
|
| - | 1619 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); |
|
| - | 1620 | mdelay(1); |
|
| - | 1621 | WREG32(CP_RB_CNTL, tmp); |
|
| - | 1622 | ||
| - | 1623 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); |
|
| - | 1624 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
|
| - | 1625 | ||
| - | 1626 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
|
| - | 1627 | rdev->cp.wptr = RREG32(CP_RB_WPTR); |
|
| - | 1628 | ||
| - | 1629 | r600_cp_start(rdev); |
|
| - | 1630 | rdev->cp.ready = true; |
|
| - | 1631 | r = radeon_ring_test(rdev); |
|
| - | 1632 | if (r) { |
|
| - | 1633 | rdev->cp.ready = false; |
|
| - | 1634 | return r; |
|
| - | 1635 | } |
|
| - | 1636 | return 0; |
|
| - | 1637 | } |
|
| 1421 | } |
1638 | |
| 1422 | void r600_cp_commit(struct radeon_device *rdev) |
1639 | void r600_cp_commit(struct radeon_device *rdev) |
| 1423 | { |
1640 | { |
| 1424 | WREG32(CP_RB_WPTR, rdev->cp.wptr); |
1641 | WREG32(CP_RB_WPTR, rdev->cp.wptr); |
| 1425 | (void)RREG32(CP_RB_WPTR); |
1642 | (void)RREG32(CP_RB_WPTR); |
| Line 1448... | Line 1665... | ||
| 1448 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
1665 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 1449 | rdev->scratch.free[i] = true; |
1666 | rdev->scratch.free[i] = true; |
| 1450 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); |
1667 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); |
| 1451 | } |
1668 | } |
| 1452 | } |
1669 | } |
| - | 1670 | ||
| - | 1671 | int r600_ring_test(struct radeon_device *rdev) |
|
| - | 1672 | { |
|
| - | 1673 | uint32_t scratch; |
|
| - | 1674 | uint32_t tmp = 0; |
|
| - | 1675 | unsigned i; |
|
| - | 1676 | int r; |
|
| - | 1677 | ||
| - | 1678 | r = radeon_scratch_get(rdev, &scratch); |
|
| - | 1679 | if (r) { |
|
| - | 1680 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
|
| - | 1681 | return r; |
|
| - | 1682 | } |
|
| - | 1683 | WREG32(scratch, 0xCAFEDEAD); |
|
| - | 1684 | r = radeon_ring_lock(rdev, 3); |
|
| - | 1685 | if (r) { |
|
| - | 1686 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
|
| - | 1687 | radeon_scratch_free(rdev, scratch); |
|
| - | 1688 | return r; |
|
| - | 1689 | } |
|
| - | 1690 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
| - | 1691 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
|
| - | 1692 | radeon_ring_write(rdev, 0xDEADBEEF); |
|
| - | 1693 | radeon_ring_unlock_commit(rdev); |
|
| - | 1694 | for (i = 0; i < rdev->usec_timeout; i++) { |
|
| - | 1695 | tmp = RREG32(scratch); |
|
| - | 1696 | if (tmp == 0xDEADBEEF) |
|
| - | 1697 | break; |
|
| - | 1698 | DRM_UDELAY(1); |
|
| - | 1699 | } |
|
| - | 1700 | if (i < rdev->usec_timeout) { |
|
| - | 1701 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
|
| - | 1702 | } else { |
|
| - | 1703 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
|
| - | 1704 | scratch, tmp); |
|
| - | 1705 | r = -EINVAL; |
|
| - | 1706 | } |
|
| - | 1707 | radeon_scratch_free(rdev, scratch); |
|
| - | 1708 | return r; |
|
| - | 1709 | } |
|
| - | 1710 | void r600_fence_ring_emit(struct radeon_device *rdev, |
|
| - | 1711 | struct radeon_fence *fence) |
|
| - | 1712 | { |
|
| - | 1713 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
|
| - | 1714 | /* Emit fence sequence & fire IRQ */ |
|
| - | 1715 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
|
| - | 1716 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
|
| - | 1717 | radeon_ring_write(rdev, fence->seq); |
|
| - | 1718 | radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); |
|
| - | 1719 | radeon_ring_write(rdev, 1); |
|
| - | 1720 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
|
| - | 1721 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); |
|
| - | 1722 | radeon_ring_write(rdev, RB_INT_STAT); |
|
| - | 1723 | } |
|
| 1453 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
1724 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 1454 | uint32_t tiling_flags, uint32_t pitch, |
1725 | uint32_t tiling_flags, uint32_t pitch, |
| 1455 | uint32_t offset, uint32_t obj_size) |
1726 | uint32_t offset, uint32_t obj_size) |
| 1456 | { |
1727 | { |
| 1457 | /* FIXME: implement */ |
1728 | /* FIXME: implement */ |
| Line 1483... | Line 1754... | ||
| 1483 | 1754 | ||
| 1484 | int r600_startup(struct radeon_device *rdev) |
1755 | int r600_startup(struct radeon_device *rdev) |
| 1485 | { |
1756 | { |
| Line -... | Line 1757... | ||
| - | 1757 | int r; |
|
| - | 1758 | ||
| - | 1759 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
|
| - | 1760 | r = r600_init_microcode(rdev); |
|
| - | 1761 | if (r) { |
|
| - | 1762 | DRM_ERROR("Failed to load firmware!\n"); |
|
| - | 1763 | return r; |
|
| - | 1764 | } |
|
| 1486 | int r; |
1765 | } |
| 1487 | 1766 | ||
| 1488 | r600_mc_program(rdev); |
1767 | r600_mc_program(rdev); |
| 1489 | if (rdev->flags & RADEON_IS_AGP) { |
1768 | if (rdev->flags & RADEON_IS_AGP) { |
| 1490 | r600_agp_enable(rdev); |
1769 | r600_agp_enable(rdev); |
| 1491 | } else { |
1770 | } else { |
| 1492 | r = r600_pcie_gart_enable(rdev); |
1771 | r = r600_pcie_gart_enable(rdev); |
| 1493 | if (r) |
1772 | if (r) |
| 1494 | return r; |
1773 | return r; |
| Line 1495... | Line -... | ||
| 1495 | } |
- | |
| 1496 | r600_gpu_init(rdev); |
- | |
| 1497 | - | ||
| 1498 | // r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
- | |
| 1499 | // &rdev->r600_blit.shader_gpu_addr); |
- | |
| 1500 | // if (r) { |
- | |
| 1501 | // DRM_ERROR("failed to pin blit object %d\n", r); |
- | |
| 1502 | // return r; |
1774 | } |
| 1503 | // } |
1775 | r600_gpu_init(rdev); |
| 1504 | 1776 | ||
| 1505 | // r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1777 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| 1506 | // if (r) |
1778 | if (r) |
| 1507 | // return r; |
1779 | return r; |
| 1508 | // r = r600_cp_load_microcode(rdev); |
1780 | r = r600_cp_load_microcode(rdev); |
| 1509 | // if (r) |
1781 | if (r) |
| 1510 | // return r; |
1782 | return r; |
| 1511 | // r = r600_cp_resume(rdev); |
1783 | r = r600_cp_resume(rdev); |
| 1512 | // if (r) |
1784 | if (r) |
| 1513 | // return r; |
1785 | return r; |
| 1514 | /* write back buffer are not vital so don't worry about failure */ |
1786 | /* write back buffer are not vital so don't worry about failure */ |
| Line 1607... | Line 1879... | ||
| 1607 | 1879 | ||
| 1608 | // r = radeon_irq_kms_init(rdev); |
1880 | // r = radeon_irq_kms_init(rdev); |
| 1609 | // if (r) |
1881 | // if (r) |
| Line 1610... | Line 1882... | ||
| 1610 | // return r; |
1882 | // return r; |
| 1611 | 1883 | ||
| Line 1612... | Line 1884... | ||
| 1612 | // rdev->cp.ring_obj = NULL; |
1884 | rdev->cp.ring_obj = NULL; |
| 1613 | // r600_ring_init(rdev, 1024 * 1024); |
1885 | r600_ring_init(rdev, 1024 * 1024); |
| Line 1614... | Line 1886... | ||
| 1614 | 1886 | ||
| 1615 | // rdev->ih.ring_obj = NULL; |
1887 | // rdev->ih.ring_obj = NULL; |
| 1616 | // r600_ih_ring_init(rdev, 64 * 1024); |
1888 | // r600_ih_ring_init(rdev, 64 * 1024); |
| Line 1617... | Line -... | ||
| 1617 | - | ||
| 1618 | r = r600_pcie_gart_init(rdev); |
- | |
| 1619 | if (r) |
- | |
| 1620 | return r; |
- | |
| 1621 | - | ||
| 1622 | // r = r600_blit_init(rdev); |
- | |
| 1623 | // if (r) { |
1889 | |
| 1624 | // DRM_ERROR("radeon: failled blitter (%d).\n", r); |
1890 | r = r600_pcie_gart_init(rdev); |
| 1625 | // return r; |
1891 | if (r) |
| 1626 | // } |
1892 | return r; |
| 1627 | 1893 | ||