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Rev 1321 | Rev 1403 | ||
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Line 234... | Line 234... | ||
234 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
234 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
235 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
235 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
236 | switch (radeon_connector->hpd.hpd) { |
236 | switch (radeon_connector->hpd.hpd) { |
237 | case RADEON_HPD_1: |
237 | case RADEON_HPD_1: |
238 | WREG32(DC_HPD1_CONTROL, tmp); |
238 | WREG32(DC_HPD1_CONTROL, tmp); |
239 | rdev->irq.hpd[0] = true; |
239 | // rdev->irq.hpd[0] = true; |
240 | break; |
240 | break; |
241 | case RADEON_HPD_2: |
241 | case RADEON_HPD_2: |
242 | WREG32(DC_HPD2_CONTROL, tmp); |
242 | WREG32(DC_HPD2_CONTROL, tmp); |
243 | rdev->irq.hpd[1] = true; |
243 | // rdev->irq.hpd[1] = true; |
244 | break; |
244 | break; |
245 | case RADEON_HPD_3: |
245 | case RADEON_HPD_3: |
246 | WREG32(DC_HPD3_CONTROL, tmp); |
246 | WREG32(DC_HPD3_CONTROL, tmp); |
247 | rdev->irq.hpd[2] = true; |
247 | // rdev->irq.hpd[2] = true; |
248 | break; |
248 | break; |
249 | case RADEON_HPD_4: |
249 | case RADEON_HPD_4: |
250 | WREG32(DC_HPD4_CONTROL, tmp); |
250 | WREG32(DC_HPD4_CONTROL, tmp); |
251 | rdev->irq.hpd[3] = true; |
251 | // rdev->irq.hpd[3] = true; |
252 | break; |
252 | break; |
253 | /* DCE 3.2 */ |
253 | /* DCE 3.2 */ |
254 | case RADEON_HPD_5: |
254 | case RADEON_HPD_5: |
255 | WREG32(DC_HPD5_CONTROL, tmp); |
255 | WREG32(DC_HPD5_CONTROL, tmp); |
256 | rdev->irq.hpd[4] = true; |
256 | // rdev->irq.hpd[4] = true; |
257 | break; |
257 | break; |
258 | case RADEON_HPD_6: |
258 | case RADEON_HPD_6: |
259 | WREG32(DC_HPD6_CONTROL, tmp); |
259 | WREG32(DC_HPD6_CONTROL, tmp); |
260 | rdev->irq.hpd[5] = true; |
260 | // rdev->irq.hpd[5] = true; |
261 | break; |
261 | break; |
262 | default: |
262 | default: |
263 | break; |
263 | break; |
264 | } |
264 | } |
265 | } |
265 | } |
Line 267... | Line 267... | ||
267 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
267 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
268 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
268 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
269 | switch (radeon_connector->hpd.hpd) { |
269 | switch (radeon_connector->hpd.hpd) { |
270 | case RADEON_HPD_1: |
270 | case RADEON_HPD_1: |
271 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
271 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
272 | rdev->irq.hpd[0] = true; |
272 | // rdev->irq.hpd[0] = true; |
273 | break; |
273 | break; |
274 | case RADEON_HPD_2: |
274 | case RADEON_HPD_2: |
275 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
275 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
276 | rdev->irq.hpd[1] = true; |
276 | // rdev->irq.hpd[1] = true; |
277 | break; |
277 | break; |
278 | case RADEON_HPD_3: |
278 | case RADEON_HPD_3: |
279 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
279 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
280 | rdev->irq.hpd[2] = true; |
280 | // rdev->irq.hpd[2] = true; |
281 | break; |
281 | break; |
282 | default: |
282 | default: |
283 | break; |
283 | break; |
284 | } |
284 | } |
285 | } |
285 | } |
286 | } |
286 | } |
- | 287 | // if (rdev->irq.installed) |
|
287 | r600_irq_set(rdev); |
288 | // r600_irq_set(rdev); |
288 | } |
289 | } |
Line 289... | Line 290... | ||
289 | 290 | ||
290 | void r600_hpd_fini(struct radeon_device *rdev) |
291 | void r600_hpd_fini(struct radeon_device *rdev) |
291 | { |
292 | { |
Line 296... | Line 297... | ||
296 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
297 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
297 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
298 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
298 | switch (radeon_connector->hpd.hpd) { |
299 | switch (radeon_connector->hpd.hpd) { |
299 | case RADEON_HPD_1: |
300 | case RADEON_HPD_1: |
300 | WREG32(DC_HPD1_CONTROL, 0); |
301 | WREG32(DC_HPD1_CONTROL, 0); |
301 | rdev->irq.hpd[0] = false; |
302 | // rdev->irq.hpd[0] = false; |
302 | break; |
303 | break; |
303 | case RADEON_HPD_2: |
304 | case RADEON_HPD_2: |
304 | WREG32(DC_HPD2_CONTROL, 0); |
305 | WREG32(DC_HPD2_CONTROL, 0); |
305 | rdev->irq.hpd[1] = false; |
306 | // rdev->irq.hpd[1] = false; |
306 | break; |
307 | break; |
307 | case RADEON_HPD_3: |
308 | case RADEON_HPD_3: |
308 | WREG32(DC_HPD3_CONTROL, 0); |
309 | WREG32(DC_HPD3_CONTROL, 0); |
309 | rdev->irq.hpd[2] = false; |
310 | // rdev->irq.hpd[2] = false; |
310 | break; |
311 | break; |
311 | case RADEON_HPD_4: |
312 | case RADEON_HPD_4: |
312 | WREG32(DC_HPD4_CONTROL, 0); |
313 | WREG32(DC_HPD4_CONTROL, 0); |
313 | rdev->irq.hpd[3] = false; |
314 | // rdev->irq.hpd[3] = false; |
314 | break; |
315 | break; |
315 | /* DCE 3.2 */ |
316 | /* DCE 3.2 */ |
316 | case RADEON_HPD_5: |
317 | case RADEON_HPD_5: |
317 | WREG32(DC_HPD5_CONTROL, 0); |
318 | WREG32(DC_HPD5_CONTROL, 0); |
318 | rdev->irq.hpd[4] = false; |
319 | // rdev->irq.hpd[4] = false; |
319 | break; |
320 | break; |
320 | case RADEON_HPD_6: |
321 | case RADEON_HPD_6: |
321 | WREG32(DC_HPD6_CONTROL, 0); |
322 | WREG32(DC_HPD6_CONTROL, 0); |
322 | rdev->irq.hpd[5] = false; |
323 | // rdev->irq.hpd[5] = false; |
323 | break; |
324 | break; |
324 | default: |
325 | default: |
325 | break; |
326 | break; |
326 | } |
327 | } |
327 | } |
328 | } |
Line 329... | Line 330... | ||
329 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
330 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
330 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
331 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
331 | switch (radeon_connector->hpd.hpd) { |
332 | switch (radeon_connector->hpd.hpd) { |
332 | case RADEON_HPD_1: |
333 | case RADEON_HPD_1: |
333 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
334 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
334 | rdev->irq.hpd[0] = false; |
335 | // rdev->irq.hpd[0] = false; |
335 | break; |
336 | break; |
336 | case RADEON_HPD_2: |
337 | case RADEON_HPD_2: |
337 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
338 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
338 | rdev->irq.hpd[1] = false; |
339 | // rdev->irq.hpd[1] = false; |
339 | break; |
340 | break; |
340 | case RADEON_HPD_3: |
341 | case RADEON_HPD_3: |
341 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
342 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
342 | rdev->irq.hpd[2] = false; |
343 | // rdev->irq.hpd[2] = false; |
343 | break; |
344 | break; |
344 | default: |
345 | default: |
345 | break; |
346 | break; |
346 | } |
347 | } |
347 | } |
348 | } |
Line 484... | Line 485... | ||
484 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
485 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
485 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
486 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
486 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
487 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
487 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
488 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
488 | if (rdev->gart.table.vram.robj) { |
489 | if (rdev->gart.table.vram.robj) { |
- | 490 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
|
- | 491 | if (likely(r == 0)) { |
|
489 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
492 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
490 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
493 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
- | 494 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
|
- | 495 | } |
|
491 | } |
496 | } |
492 | } |
497 | } |
Line 493... | Line 498... | ||
493 | 498 | ||
494 | void r600_pcie_gart_fini(struct radeon_device *rdev) |
499 | void r600_pcie_gart_fini(struct radeon_device *rdev) |
Line 616... | Line 621... | ||
616 | int r600_mc_init(struct radeon_device *rdev) |
621 | int r600_mc_init(struct radeon_device *rdev) |
617 | { |
622 | { |
618 | fixed20_12 a; |
623 | fixed20_12 a; |
619 | u32 tmp; |
624 | u32 tmp; |
620 | int chansize, numchan; |
625 | int chansize, numchan; |
621 | int r; |
- | |
Line 622... | Line 626... | ||
622 | 626 | ||
623 | /* Get VRAM informations */ |
627 | /* Get VRAM informations */ |
624 | rdev->mc.vram_is_ddr = true; |
628 | rdev->mc.vram_is_ddr = true; |
625 | tmp = RREG32(RAMCFG); |
629 | tmp = RREG32(RAMCFG); |
Line 659... | Line 663... | ||
659 | 663 | ||
660 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
664 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
Line 661... | Line 665... | ||
661 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
665 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
662 | - | ||
663 | if (rdev->flags & RADEON_IS_AGP) { |
- | |
664 | r = radeon_agp_init(rdev); |
- | |
665 | if (r) |
666 | |
666 | return r; |
667 | if (rdev->flags & RADEON_IS_AGP) { |
667 | /* gtt_size is setup by radeon_agp_init */ |
668 | /* gtt_size is setup by radeon_agp_init */ |
668 | rdev->mc.gtt_location = rdev->mc.agp_base; |
669 | rdev->mc.gtt_location = rdev->mc.agp_base; |
669 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
670 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
Line 719... | Line 720... | ||
719 | * default setup |
720 | * default setup |
720 | */ |
721 | */ |
721 | a.full = rfixed_const(100); |
722 | a.full = rfixed_const(100); |
722 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
723 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
723 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
724 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
- | 725 | ||
- | 726 | if (rdev->flags & RADEON_IS_IGP) |
|
- | 727 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
|
- | 728 | ||
724 | return 0; |
729 | return 0; |
725 | } |
730 | } |
Line 726... | Line 731... | ||
726 | 731 | ||
727 | /* We doesn't check that the GPU really needs a reset we simply do the |
732 | /* We doesn't check that the GPU really needs a reset we simply do the |
Line 1377... | Line 1382... | ||
1377 | (void)RREG32(PCIE_PORT_INDEX); |
1382 | (void)RREG32(PCIE_PORT_INDEX); |
1378 | WREG32(PCIE_PORT_DATA, (v)); |
1383 | WREG32(PCIE_PORT_DATA, (v)); |
1379 | (void)RREG32(PCIE_PORT_DATA); |
1384 | (void)RREG32(PCIE_PORT_DATA); |
1380 | } |
1385 | } |
Line 1381... | Line -... | ||
1381 | - | ||
1382 | void r600_hdp_flush(struct radeon_device *rdev) |
- | |
1383 | { |
- | |
1384 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
- | |
1385 | } |
- | |
1386 | 1386 | ||
1387 | /* |
1387 | /* |
1388 | * CP & Ring |
1388 | * CP & Ring |
1389 | */ |
1389 | */ |
1390 | void r600_cp_stop(struct radeon_device *rdev) |
1390 | void r600_cp_stop(struct radeon_device *rdev) |
Line 1589... | Line 1589... | ||
1589 | radeon_pm_init(rdev); |
1589 | radeon_pm_init(rdev); |
1590 | /* Fence driver */ |
1590 | /* Fence driver */ |
1591 | // r = radeon_fence_driver_init(rdev); |
1591 | // r = radeon_fence_driver_init(rdev); |
1592 | // if (r) |
1592 | // if (r) |
1593 | // return r; |
1593 | // return r; |
- | 1594 | if (rdev->flags & RADEON_IS_AGP) { |
|
- | 1595 | r = radeon_agp_init(rdev); |
|
- | 1596 | if (r) |
|
- | 1597 | radeon_agp_disable(rdev); |
|
- | 1598 | } |
|
1594 | r = r600_mc_init(rdev); |
1599 | r = r600_mc_init(rdev); |
1595 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1600 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1596 | if (r) |
1601 | if (r) |
1597 | return r; |
1602 | return r; |
1598 | /* Memory manager */ |
1603 | /* Memory manager */ |