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| Rev 1313 | Rev 1321 | ||
|---|---|---|---|
| Line 35... | Line 35... | ||
| 35 | #include "atom.h" |
35 | #include "atom.h" |
| 36 | #include "avivod.h" |
36 | #include "avivod.h" |
| Line 37... | Line 37... | ||
| 37 | 37 | ||
| 38 | #define PFP_UCODE_SIZE 576 |
38 | #define PFP_UCODE_SIZE 576 |
| - | 39 | #define PM4_UCODE_SIZE 1792 |
|
| 39 | #define PM4_UCODE_SIZE 1792 |
40 | #define RLC_UCODE_SIZE 768 |
| 40 | #define R700_PFP_UCODE_SIZE 848 |
41 | #define R700_PFP_UCODE_SIZE 848 |
| - | 42 | #define R700_PM4_UCODE_SIZE 1360 |
|
| Line 41... | Line 43... | ||
| 41 | #define R700_PM4_UCODE_SIZE 1360 |
43 | #define R700_RLC_UCODE_SIZE 1024 |
| 42 | 44 | ||
| 43 | /* Firmware Names */ |
45 | /* Firmware Names */ |
| 44 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
46 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
| Line 59... | Line 61... | ||
| 59 | MODULE_FIRMWARE("radeon/RV770_me.bin"); |
61 | MODULE_FIRMWARE("radeon/RV770_me.bin"); |
| 60 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
62 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
| 61 | MODULE_FIRMWARE("radeon/RV730_me.bin"); |
63 | MODULE_FIRMWARE("radeon/RV730_me.bin"); |
| 62 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
64 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
| 63 | MODULE_FIRMWARE("radeon/RV710_me.bin"); |
65 | MODULE_FIRMWARE("radeon/RV710_me.bin"); |
| - | 66 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
|
| - | 67 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); |
|
| Line 64... | Line 68... | ||
| 64 | 68 | ||
| Line 65... | Line 69... | ||
| 65 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
69 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
| 66 | 70 | ||
| 67 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
71 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
| 68 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
72 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| Line -... | Line 73... | ||
| - | 73 | void r600_gpu_init(struct radeon_device *rdev); |
|
| - | 74 | void r600_fini(struct radeon_device *rdev); |
|
| - | 75 | ||
| - | 76 | /* hpd for digital panel detect/disconnect */ |
|
| - | 77 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
|
| - | 78 | { |
|
| - | 79 | bool connected = false; |
|
| - | 80 | ||
| - | 81 | if (ASIC_IS_DCE3(rdev)) { |
|
| - | 82 | switch (hpd) { |
|
| - | 83 | case RADEON_HPD_1: |
|
| - | 84 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 85 | connected = true; |
|
| - | 86 | break; |
|
| - | 87 | case RADEON_HPD_2: |
|
| - | 88 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 89 | connected = true; |
|
| - | 90 | break; |
|
| - | 91 | case RADEON_HPD_3: |
|
| - | 92 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 93 | connected = true; |
|
| - | 94 | break; |
|
| - | 95 | case RADEON_HPD_4: |
|
| - | 96 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 97 | connected = true; |
|
| - | 98 | break; |
|
| - | 99 | /* DCE 3.2 */ |
|
| - | 100 | case RADEON_HPD_5: |
|
| - | 101 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 102 | connected = true; |
|
| - | 103 | break; |
|
| - | 104 | case RADEON_HPD_6: |
|
| - | 105 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) |
|
| - | 106 | connected = true; |
|
| - | 107 | break; |
|
| - | 108 | default: |
|
| - | 109 | break; |
|
| - | 110 | } |
|
| - | 111 | } else { |
|
| - | 112 | switch (hpd) { |
|
| - | 113 | case RADEON_HPD_1: |
|
| - | 114 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
|
| - | 115 | connected = true; |
|
| - | 116 | break; |
|
| - | 117 | case RADEON_HPD_2: |
|
| - | 118 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
|
| - | 119 | connected = true; |
|
| - | 120 | break; |
|
| - | 121 | case RADEON_HPD_3: |
|
| - | 122 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
|
| - | 123 | connected = true; |
|
| - | 124 | break; |
|
| - | 125 | default: |
|
| - | 126 | break; |
|
| - | 127 | } |
|
| - | 128 | } |
|
| - | 129 | return connected; |
|
| - | 130 | } |
|
| - | 131 | ||
| - | 132 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
|
| - | 133 | enum radeon_hpd_id hpd) |
|
| - | 134 | { |
|
| - | 135 | u32 tmp; |
|
| - | 136 | bool connected = r600_hpd_sense(rdev, hpd); |
|
| - | 137 | ||
| - | 138 | if (ASIC_IS_DCE3(rdev)) { |
|
| - | 139 | switch (hpd) { |
|
| - | 140 | case RADEON_HPD_1: |
|
| - | 141 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
|
| - | 142 | if (connected) |
|
| - | 143 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 144 | else |
|
| - | 145 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 146 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
|
| - | 147 | break; |
|
| - | 148 | case RADEON_HPD_2: |
|
| - | 149 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
|
| - | 150 | if (connected) |
|
| - | 151 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 152 | else |
|
| - | 153 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 154 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
|
| - | 155 | break; |
|
| - | 156 | case RADEON_HPD_3: |
|
| - | 157 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
|
| - | 158 | if (connected) |
|
| - | 159 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 160 | else |
|
| - | 161 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 162 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
|
| - | 163 | break; |
|
| - | 164 | case RADEON_HPD_4: |
|
| - | 165 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
|
| - | 166 | if (connected) |
|
| - | 167 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 168 | else |
|
| - | 169 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 170 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
|
| - | 171 | break; |
|
| - | 172 | case RADEON_HPD_5: |
|
| - | 173 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
|
| - | 174 | if (connected) |
|
| - | 175 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 176 | else |
|
| - | 177 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 178 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
|
| - | 179 | break; |
|
| - | 180 | /* DCE 3.2 */ |
|
| - | 181 | case RADEON_HPD_6: |
|
| - | 182 | tmp = RREG32(DC_HPD6_INT_CONTROL); |
|
| - | 183 | if (connected) |
|
| - | 184 | tmp &= ~DC_HPDx_INT_POLARITY; |
|
| - | 185 | else |
|
| - | 186 | tmp |= DC_HPDx_INT_POLARITY; |
|
| - | 187 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
|
| - | 188 | break; |
|
| - | 189 | default: |
|
| - | 190 | break; |
|
| - | 191 | } |
|
| - | 192 | } else { |
|
| - | 193 | switch (hpd) { |
|
| - | 194 | case RADEON_HPD_1: |
|
| - | 195 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); |
|
| - | 196 | if (connected) |
|
| - | 197 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 198 | else |
|
| - | 199 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 200 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
|
| - | 201 | break; |
|
| - | 202 | case RADEON_HPD_2: |
|
| - | 203 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); |
|
| - | 204 | if (connected) |
|
| - | 205 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 206 | else |
|
| - | 207 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 208 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
|
| - | 209 | break; |
|
| - | 210 | case RADEON_HPD_3: |
|
| - | 211 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); |
|
| - | 212 | if (connected) |
|
| - | 213 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 214 | else |
|
| - | 215 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
|
| - | 216 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
|
| - | 217 | break; |
|
| - | 218 | default: |
|
| - | 219 | break; |
|
| - | 220 | } |
|
| - | 221 | } |
|
| - | 222 | } |
|
| - | 223 | ||
| - | 224 | void r600_hpd_init(struct radeon_device *rdev) |
|
| - | 225 | { |
|
| - | 226 | struct drm_device *dev = rdev->ddev; |
|
| - | 227 | struct drm_connector *connector; |
|
| - | 228 | ||
| - | 229 | if (ASIC_IS_DCE3(rdev)) { |
|
| - | 230 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); |
|
| - | 231 | if (ASIC_IS_DCE32(rdev)) |
|
| - | 232 | tmp |= DC_HPDx_EN; |
|
| - | 233 | ||
| - | 234 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 235 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 236 | switch (radeon_connector->hpd.hpd) { |
|
| - | 237 | case RADEON_HPD_1: |
|
| - | 238 | WREG32(DC_HPD1_CONTROL, tmp); |
|
| - | 239 | rdev->irq.hpd[0] = true; |
|
| - | 240 | break; |
|
| - | 241 | case RADEON_HPD_2: |
|
| - | 242 | WREG32(DC_HPD2_CONTROL, tmp); |
|
| - | 243 | rdev->irq.hpd[1] = true; |
|
| - | 244 | break; |
|
| - | 245 | case RADEON_HPD_3: |
|
| - | 246 | WREG32(DC_HPD3_CONTROL, tmp); |
|
| - | 247 | rdev->irq.hpd[2] = true; |
|
| - | 248 | break; |
|
| - | 249 | case RADEON_HPD_4: |
|
| - | 250 | WREG32(DC_HPD4_CONTROL, tmp); |
|
| - | 251 | rdev->irq.hpd[3] = true; |
|
| - | 252 | break; |
|
| - | 253 | /* DCE 3.2 */ |
|
| - | 254 | case RADEON_HPD_5: |
|
| - | 255 | WREG32(DC_HPD5_CONTROL, tmp); |
|
| - | 256 | rdev->irq.hpd[4] = true; |
|
| - | 257 | break; |
|
| - | 258 | case RADEON_HPD_6: |
|
| - | 259 | WREG32(DC_HPD6_CONTROL, tmp); |
|
| - | 260 | rdev->irq.hpd[5] = true; |
|
| - | 261 | break; |
|
| - | 262 | default: |
|
| - | 263 | break; |
|
| - | 264 | } |
|
| - | 265 | } |
|
| - | 266 | } else { |
|
| - | 267 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 268 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 269 | switch (radeon_connector->hpd.hpd) { |
|
| - | 270 | case RADEON_HPD_1: |
|
| - | 271 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
|
| - | 272 | rdev->irq.hpd[0] = true; |
|
| - | 273 | break; |
|
| - | 274 | case RADEON_HPD_2: |
|
| - | 275 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
|
| - | 276 | rdev->irq.hpd[1] = true; |
|
| - | 277 | break; |
|
| - | 278 | case RADEON_HPD_3: |
|
| - | 279 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
|
| - | 280 | rdev->irq.hpd[2] = true; |
|
| - | 281 | break; |
|
| - | 282 | default: |
|
| - | 283 | break; |
|
| - | 284 | } |
|
| - | 285 | } |
|
| - | 286 | } |
|
| - | 287 | r600_irq_set(rdev); |
|
| - | 288 | } |
|
| - | 289 | ||
| - | 290 | void r600_hpd_fini(struct radeon_device *rdev) |
|
| - | 291 | { |
|
| - | 292 | struct drm_device *dev = rdev->ddev; |
|
| - | 293 | struct drm_connector *connector; |
|
| - | 294 | ||
| - | 295 | if (ASIC_IS_DCE3(rdev)) { |
|
| - | 296 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 297 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 298 | switch (radeon_connector->hpd.hpd) { |
|
| - | 299 | case RADEON_HPD_1: |
|
| - | 300 | WREG32(DC_HPD1_CONTROL, 0); |
|
| - | 301 | rdev->irq.hpd[0] = false; |
|
| - | 302 | break; |
|
| - | 303 | case RADEON_HPD_2: |
|
| - | 304 | WREG32(DC_HPD2_CONTROL, 0); |
|
| - | 305 | rdev->irq.hpd[1] = false; |
|
| - | 306 | break; |
|
| - | 307 | case RADEON_HPD_3: |
|
| - | 308 | WREG32(DC_HPD3_CONTROL, 0); |
|
| - | 309 | rdev->irq.hpd[2] = false; |
|
| - | 310 | break; |
|
| - | 311 | case RADEON_HPD_4: |
|
| - | 312 | WREG32(DC_HPD4_CONTROL, 0); |
|
| - | 313 | rdev->irq.hpd[3] = false; |
|
| - | 314 | break; |
|
| - | 315 | /* DCE 3.2 */ |
|
| - | 316 | case RADEON_HPD_5: |
|
| - | 317 | WREG32(DC_HPD5_CONTROL, 0); |
|
| - | 318 | rdev->irq.hpd[4] = false; |
|
| - | 319 | break; |
|
| - | 320 | case RADEON_HPD_6: |
|
| - | 321 | WREG32(DC_HPD6_CONTROL, 0); |
|
| - | 322 | rdev->irq.hpd[5] = false; |
|
| - | 323 | break; |
|
| - | 324 | default: |
|
| - | 325 | break; |
|
| - | 326 | } |
|
| - | 327 | } |
|
| - | 328 | } else { |
|
| - | 329 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
|
| - | 330 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
|
| - | 331 | switch (radeon_connector->hpd.hpd) { |
|
| - | 332 | case RADEON_HPD_1: |
|
| - | 333 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
|
| - | 334 | rdev->irq.hpd[0] = false; |
|
| - | 335 | break; |
|
| - | 336 | case RADEON_HPD_2: |
|
| - | 337 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
|
| - | 338 | rdev->irq.hpd[1] = false; |
|
| - | 339 | break; |
|
| - | 340 | case RADEON_HPD_3: |
|
| - | 341 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
|
| - | 342 | rdev->irq.hpd[2] = false; |
|
| - | 343 | break; |
|
| - | 344 | default: |
|
| - | 345 | break; |
|
| - | 346 | } |
|
| - | 347 | } |
|
| 69 | void r600_gpu_init(struct radeon_device *rdev); |
348 | } |
| 70 | void r600_fini(struct radeon_device *rdev); |
349 | } |
| 71 | 350 | ||
| 72 | /* |
351 | /* |
| 73 | * R600 PCIE GART |
352 | * R600 PCIE GART |
| Line 177... | Line 456... | ||
| 177 | } |
456 | } |
| Line 178... | Line 457... | ||
| 178 | 457 | ||
| 179 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
458 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
| 180 | { |
459 | { |
| 181 | u32 tmp; |
460 | u32 tmp; |
| Line 182... | Line 461... | ||
| 182 | int i; |
461 | int i, r; |
| 183 | 462 | ||
| 184 | /* Disable all tables */ |
463 | /* Disable all tables */ |
| Line 1098... | Line 1377... | ||
| 1098 | (void)RREG32(PCIE_PORT_INDEX); |
1377 | (void)RREG32(PCIE_PORT_INDEX); |
| 1099 | WREG32(PCIE_PORT_DATA, (v)); |
1378 | WREG32(PCIE_PORT_DATA, (v)); |
| 1100 | (void)RREG32(PCIE_PORT_DATA); |
1379 | (void)RREG32(PCIE_PORT_DATA); |
| 1101 | } |
1380 | } |
| Line -... | Line 1381... | ||
| - | 1381 | ||
| - | 1382 | void r600_hdp_flush(struct radeon_device *rdev) |
|
| - | 1383 | { |
|
| - | 1384 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
|
| Line 1102... | Line 1385... | ||
| 1102 | 1385 | } |
|
| 1103 | 1386 | ||
| 1104 | /* |
1387 | /* |
| 1105 | * CP & Ring |
1388 | * CP & Ring |
| Line 1283... | Line 1566... | ||
| 1283 | } |
1566 | } |
| 1284 | r = radeon_atombios_init(rdev); |
1567 | r = radeon_atombios_init(rdev); |
| 1285 | if (r) |
1568 | if (r) |
| 1286 | return r; |
1569 | return r; |
| 1287 | /* Post card if necessary */ |
1570 | /* Post card if necessary */ |
| 1288 | if (!r600_card_posted(rdev) && rdev->bios) { |
1571 | if (!r600_card_posted(rdev)) { |
| - | 1572 | if (!rdev->bios) { |
|
| - | 1573 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
|
| - | 1574 | return -EINVAL; |
|
| - | 1575 | } |
|
| 1289 | DRM_INFO("GPU not posted. posting now...\n"); |
1576 | DRM_INFO("GPU not posted. posting now...\n"); |
| 1290 | atom_asic_init(rdev->mode_info.atom_context); |
1577 | atom_asic_init(rdev->mode_info.atom_context); |
| 1291 | } |
1578 | } |
| 1292 | /* Initialize scratch registers */ |
1579 | /* Initialize scratch registers */ |
| 1293 | r600_scratch_init(rdev); |
1580 | r600_scratch_init(rdev); |
| Line 1307... | Line 1594... | ||
| 1307 | r = r600_mc_init(rdev); |
1594 | r = r600_mc_init(rdev); |
| 1308 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1595 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
| 1309 | if (r) |
1596 | if (r) |
| 1310 | return r; |
1597 | return r; |
| 1311 | /* Memory manager */ |
1598 | /* Memory manager */ |
| 1312 | r = radeon_object_init(rdev); |
1599 | r = radeon_bo_init(rdev); |
| 1313 | if (r) |
1600 | if (r) |
| 1314 | return r; |
1601 | return r; |
| - | 1602 | ||
| - | 1603 | // r = radeon_irq_kms_init(rdev); |
|
| - | 1604 | // if (r) |
|
| - | 1605 | // return r; |
|
| - | 1606 | ||
| 1315 | // rdev->cp.ring_obj = NULL; |
1607 | // rdev->cp.ring_obj = NULL; |
| 1316 | // r600_ring_init(rdev, 1024 * 1024); |
1608 | // r600_ring_init(rdev, 1024 * 1024); |
| Line 1317... | Line 1609... | ||
| 1317 | 1609 | ||
| 1318 | // if (!rdev->me_fw || !rdev->pfp_fw) { |
1610 | // rdev->ih.ring_obj = NULL; |
| 1319 | // r = r600_cp_init_microcode(rdev); |
- | |
| 1320 | // if (r) { |
- | |
| 1321 | // DRM_ERROR("Failed to load firmware!\n"); |
- | |
| 1322 | // return r; |
- | |
| 1323 | // } |
- | |
| Line 1324... | Line 1611... | ||
| 1324 | // } |
1611 | // r600_ih_ring_init(rdev, 64 * 1024); |
| 1325 | 1612 | ||
| 1326 | r = r600_pcie_gart_init(rdev); |
1613 | r = r600_pcie_gart_init(rdev); |
| Line 1327... | Line -... | ||
| 1327 | if (r) |
- | |
| 1328 | return r; |
1614 | if (r) |
| 1329 | 1615 | return r; |
|
| 1330 | rdev->accel_working = true; |
1616 | |
| 1331 | // r = r600_blit_init(rdev); |
1617 | // r = r600_blit_init(rdev); |
| 1332 | // if (r) { |
1618 | // if (r) { |
| Line -... | Line 1619... | ||
| - | 1619 | // DRM_ERROR("radeon: failled blitter (%d).\n", r); |
|
| 1333 | // DRM_ERROR("radeon: failled blitter (%d).\n", r); |
1620 | // return r; |
| 1334 | // return r; |
1621 | // } |
| 1335 | // } |
1622 | |
| 1336 | 1623 | rdev->accel_working = true; |
|
| 1337 | r = r600_startup(rdev); |
1624 | r = r600_startup(rdev); |
| Line 1373... | Line 1660... | ||
| 1373 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) |
1660 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) |
| 1374 | { |
1661 | { |
| 1375 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
1662 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1376 | struct drm_device *dev = node->minor->dev; |
1663 | struct drm_device *dev = node->minor->dev; |
| 1377 | struct radeon_device *rdev = dev->dev_private; |
1664 | struct radeon_device *rdev = dev->dev_private; |
| 1378 | uint32_t rdp, wdp; |
- | |
| 1379 | unsigned count, i, j; |
1665 | unsigned count, i, j; |
| Line 1380... | Line 1666... | ||
| 1380 | 1666 | ||
| 1381 | radeon_ring_free_size(rdev); |
- | |
| 1382 | rdp = RREG32(CP_RB_RPTR); |
- | |
| 1383 | wdp = RREG32(CP_RB_WPTR); |
1667 | radeon_ring_free_size(rdev); |
| 1384 | count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; |
1668 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
| 1385 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
1669 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
| 1386 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
1670 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
| - | 1671 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); |
|
| - | 1672 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); |
|
| 1387 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
1673 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); |
| 1388 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
1674 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
| - | 1675 | seq_printf(m, "%u dwords in ring\n", count); |
|
| 1389 | seq_printf(m, "%u dwords in ring\n", count); |
1676 | i = rdev->cp.rptr; |
| 1390 | for (j = 0; j <= count; j++) { |
- | |
| 1391 | i = (rdp + j) & rdev->cp.ptr_mask; |
1677 | for (j = 0; j <= count; j++) { |
| - | 1678 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
|
| 1392 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
1679 | i = (i + 1) & rdev->cp.ptr_mask; |
| 1393 | } |
1680 | } |
| 1394 | return 0; |
1681 | return 0; |
| Line 1395... | Line 1682... | ||
| 1395 | } |
1682 | } |