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Rev 1246 Rev 1268
Line 336... Line 336...
336 
 
 336 
 
337 
int r600_mc_init(struct radeon_device *rdev)
 337 
int r600_mc_init(struct radeon_device *rdev)
338 
{
 338 
{
339 
	fixed20_12 a;
 339 
	fixed20_12 a;
340 
	u32 tmp;
 340 
	u32 tmp;
341 
	int chansize;
 341 
	int chansize, numchan;
Line 342... Line 342...
342 
	int r;
 342 
	int r;
343 
 
 - 
 
344 
	/* Get VRAM informations */
 343 
 
345 
	rdev->mc.vram_width = 128;
 344 
	/* Get VRAM informations */
346 
	rdev->mc.vram_is_ddr = true;
 345 
	rdev->mc.vram_is_ddr = true;
347 
	tmp = RREG32(RAMCFG);
 346 
	tmp = RREG32(RAMCFG);
348 
	if (tmp & CHANSIZE_OVERRIDE) {
 347 
	if (tmp & CHANSIZE_OVERRIDE) {
349 
		chansize = 16;
 348 
		chansize = 16;
350 
	} else if (tmp & CHANSIZE_MASK) {
 349 
	} else if (tmp & CHANSIZE_MASK) {
351 
		chansize = 64;
 350 
		chansize = 64;
352 
	} else {
 351 
	} else {
353 
		chansize = 32;
 352 
		chansize = 32;
354 
	}
 353 
	}
- 
 
 354 
	tmp = RREG32(CHMAP);
355 
	if (rdev->family == CHIP_R600) {
 355 
	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
356 
		rdev->mc.vram_width = 8 * chansize;
 356 
	case 0:
- 
 
 357 
	default:
357 
	} else if (rdev->family == CHIP_RV670) {
 358 
		numchan = 1;
358 
		rdev->mc.vram_width = 4 * chansize;
 359 
		break;
- 
 
 360 
	case 1:
- 
 
 361 
		numchan = 2;
359 
	} else if ((rdev->family == CHIP_RV610) ||
 362 
		break;
360 
			(rdev->family == CHIP_RV620)) {
 363 
	case 2:
361 
		rdev->mc.vram_width = chansize;
 364 
		numchan = 4;
362 
	} else if ((rdev->family == CHIP_RV630) ||
 365 
		break;
- 
 
 366 
	case 3:
363 
			(rdev->family == CHIP_RV635)) {
 367 
		numchan = 8;
- 
 
 368 
		break;
364 
		rdev->mc.vram_width = 2 * chansize;
 369 
	}
365 
	}
 370 
	rdev->mc.vram_width = numchan * chansize;
366 
	/* Could aper size report 0 ? */
 371 
	/* Could aper size report 0 ? */
367 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 372 
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
368 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 373 
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
Line 401... Line 406...
401 
			 */
 406 
			 */
402 
			rdev->mc.vram_location = 0x00000000UL;
 407 
			rdev->mc.vram_location = 0x00000000UL;
403 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 408 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
404 
		}
 409 
		}
405 
	} else {
 410 
	} else {
406 
		if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 411 
		rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
407 
			rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 412 
			rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
408 
								0xFFFF) << 24;
 413 
								0xFFFF) << 24;
409 
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 - 
 
410 
			tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 414 
			tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
411 
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 415 
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
412 
				/* Enough place after vram */
 416 
				/* Enough place after vram */
413 
				rdev->mc.gtt_location = tmp;
 417 
				rdev->mc.gtt_location = tmp;
414 
			} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 418 
			} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
Line 425... Line 429...
425 
					rdev->mc.gtt_location = tmp;
 429 
					rdev->mc.gtt_location = tmp;
426 
					rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 430 
					rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
427 
				}
 431 
				}
428 
			}
 432 
			}
429 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 433 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
430 
		} else {
 - 
 
431 
			rdev->mc.vram_location = 0x00000000UL;
 - 
 
432 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 - 
 
433 
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 - 
 
434 
		}
 - 
 
435 
	}
 434 
	}
436 
	rdev->mc.vram_start = rdev->mc.vram_location;
 435 
	rdev->mc.vram_start = rdev->mc.vram_location;
437 
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 436 
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
438 
	rdev->mc.gtt_start = rdev->mc.gtt_location;
 437 
	rdev->mc.gtt_start = rdev->mc.gtt_location;
439 
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 438 
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
Line 856... Line 855...
856 
 
 855 
 
857 
	if (((rdev->family) == CHIP_R600) ||
 856 
	if (((rdev->family) == CHIP_R600) ||
858 
	    ((rdev->family) == CHIP_RV630) ||
 857 
	    ((rdev->family) == CHIP_RV630) ||
859 
	    ((rdev->family) == CHIP_RV610) ||
 858 
	    ((rdev->family) == CHIP_RV610) ||
- 
 
 859 
	    ((rdev->family) == CHIP_RV620) ||
860 
	    ((rdev->family) == CHIP_RV620) ||
 860 
	    ((rdev->family) == CHIP_RS780) ||
861 
	    ((rdev->family) == CHIP_RS780)) {
 861 
	    ((rdev->family) == CHIP_RS880)) {
862 
		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 862 
		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
863 
	} else {
 863 
	} else {
864 
		WREG32(DB_DEBUG, 0);
 864 
		WREG32(DB_DEBUG, 0);
865 
	}
 865 
	}
Line 873... Line 873...
873 
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 873 
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
Line 874... Line 874...
874 
 
 874 
 
875 
	tmp = RREG32(SQ_MS_FIFO_SIZES);
 875 
	tmp = RREG32(SQ_MS_FIFO_SIZES);
876 
	if (((rdev->family) == CHIP_RV610) ||
 876 
	if (((rdev->family) == CHIP_RV610) ||
- 
 
 877 
	    ((rdev->family) == CHIP_RV620) ||
877 
	    ((rdev->family) == CHIP_RV620) ||
 878 
	    ((rdev->family) == CHIP_RS780) ||
878 
	    ((rdev->family) == CHIP_RS780)) {
 879 
	    ((rdev->family) == CHIP_RS880)) {
879 
		tmp = (CACHE_FIFO_SIZE(0xa) |
 880 
		tmp = (CACHE_FIFO_SIZE(0xa) |
880 
		       FETCH_FIFO_HIWATER(0xa) |
 881 
		       FETCH_FIFO_HIWATER(0xa) |
881 
		       DONE_FIFO_HIWATER(0xe0) |
 882 
		       DONE_FIFO_HIWATER(0xe0) |
882 
		       ALU_UPDATE_FIFO_HIWATER(0x8));
 883 
		       ALU_UPDATE_FIFO_HIWATER(0x8));
Line 916... Line 917...
916 
					    NUM_VS_STACK_ENTRIES(128));
 917 
					    NUM_VS_STACK_ENTRIES(128));
917 
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
 918 
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
918 
					    NUM_ES_STACK_ENTRIES(0));
 919 
					    NUM_ES_STACK_ENTRIES(0));
919 
	} else if (((rdev->family) == CHIP_RV610) ||
 920 
	} else if (((rdev->family) == CHIP_RV610) ||
920 
		   ((rdev->family) == CHIP_RV620) ||
 921 
		   ((rdev->family) == CHIP_RV620) ||
- 
 
 922 
		   ((rdev->family) == CHIP_RS780) ||
921 
		   ((rdev->family) == CHIP_RS780)) {
 923 
		   ((rdev->family) == CHIP_RS880)) {
922 
		/* no vertex cache */
 924 
		/* no vertex cache */
923 
		sq_config &= ~VC_ENABLE;
 925 
		sq_config &= ~VC_ENABLE;
Line 924... Line 926...
924 
 
 926 
 
925 
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 927 
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
Line 973... Line 975...
973 
	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 975 
	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
974 
	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 976 
	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
Line 975... Line 977...
975 
 
 977 
 
976 
	if (((rdev->family) == CHIP_RV610) ||
 978 
	if (((rdev->family) == CHIP_RV610) ||
- 
 
 979 
	    ((rdev->family) == CHIP_RV620) ||
977 
	    ((rdev->family) == CHIP_RV620) ||
 980 
	    ((rdev->family) == CHIP_RS780) ||
978 
	    ((rdev->family) == CHIP_RS780)) {
 981 
	    ((rdev->family) == CHIP_RS880)) {
979 
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
 982 
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
980 
	} else {
 983 
	} else {
981 
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
 984 
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
Line 999... Line 1002...
999 
 
 1002 
 
1000 
	WREG32(VGT_STRMOUT_EN, 0);
 1003 
	WREG32(VGT_STRMOUT_EN, 0);
1001 
	tmp = rdev->config.r600.max_pipes * 16;
 1004 
	tmp = rdev->config.r600.max_pipes * 16;
1002 
	switch (rdev->family) {
 1005 
	switch (rdev->family) {
1003 
	case CHIP_RV610:
 - 
 
1004 
	case CHIP_RS780:
 1006 
	case CHIP_RV610:
- 
 
 1007 
	case CHIP_RV620:
- 
 
 1008 
	case CHIP_RS780:
1005 
	case CHIP_RV620:
 1009 
	case CHIP_RS880:
1006 
		tmp += 32;
 1010 
		tmp += 32;
1007 
		break;
 1011 
		break;
1008 
	case CHIP_RV670:
 1012 
	case CHIP_RV670:
1009 
		tmp += 128;
 1013 
		tmp += 128;
Line 1041... Line 1045...
1041 
	WREG32(CB_COLOR7_BASE, 0);
 1045 
	WREG32(CB_COLOR7_BASE, 0);
1042 
	WREG32(CB_COLOR7_FRAG, 0);
 1046 
	WREG32(CB_COLOR7_FRAG, 0);
Line 1043... Line 1047...
1043 
 
 1047 
 
1044 
	switch (rdev->family) {
 1048 
	switch (rdev->family) {
1045 
	case CHIP_RV610:
 - 
 
1046 
	case CHIP_RS780:
 1049 
	case CHIP_RV610:
- 
 
 1050 
	case CHIP_RV620:
- 
 
 1051 
	case CHIP_RS780:
1047 
	case CHIP_RV620:
 1052 
	case CHIP_RS880:
1048 
		tmp = TC_L2_SIZE(8);
 1053 
		tmp = TC_L2_SIZE(8);
1049 
		break;
 1054 
		break;
1050 
	case CHIP_RV630:
 1055 
	case CHIP_RV630:
1051 
	case CHIP_RV635:
 1056 
	case CHIP_RV635:
Line 1286... Line 1291...
1286 
	}
 1291 
	}
1287 
	/* Initialize scratch registers */
 1292 
	/* Initialize scratch registers */
1288 
	r600_scratch_init(rdev);
 1293 
	r600_scratch_init(rdev);
1289 
	/* Initialize surface registers */
 1294 
	/* Initialize surface registers */
1290 
	radeon_surface_init(rdev);
 1295 
	radeon_surface_init(rdev);
- 
 
 1296 
	/* Initialize clocks */
1291 
	radeon_get_clock_info(rdev->ddev);
 1297 
	radeon_get_clock_info(rdev->ddev);
1292 
	r = radeon_clocks_init(rdev);
 1298 
	r = radeon_clocks_init(rdev);
1293 
	if (r)
 1299 
	if (r)
1294 
		return r;
 1300 
		return r;
- 
 
 1301 
	/* Initialize power management */
- 
 
 1302 
	radeon_pm_init(rdev);
1295 
	/* Fence driver */
 1303 
	/* Fence driver */
1296 
//	r = radeon_fence_driver_init(rdev);
 1304 
//	r = radeon_fence_driver_init(rdev);
1297 
//	if (r)
 1305 
//	if (r)
1298 
//		return r;
 1306 
//		return r;
1299 
	r = r600_mc_init(rdev);
 1307 
	r = r600_mc_init(rdev);