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Rev 1221 Rev 1233
Line 23... Line 23...
23 
 *
 23 
 *
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
#include
28 
#include
29 
#include
29 
#include
30 
#include "drmP.h"
 30 
#include "drmP.h"
31 
#include "radeon_drm.h"
 31 
#include "radeon_drm.h"
32 
#include "radeon.h"
 32 
#include "radeon.h"
33 
#include "radeon_mode.h"
 33 
#include "radeon_mode.h"
Line 205... Line 205...
205 
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 205 
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
206 
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 206 
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
207 
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 207 
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
208 
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 208 
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
209 
	if (rdev->gart.table.vram.robj) {
 209 
	if (rdev->gart.table.vram.robj) {
210 
		radeon_object_kunmap(rdev->gart.table.vram.robj);
 210 
//       radeon_object_kunmap(rdev->gart.table.vram.robj);
211 
		radeon_object_unpin(rdev->gart.table.vram.robj);
 211 
//       radeon_object_unpin(rdev->gart.table.vram.robj);
212 
	}
 212 
	}
213 
}
 213 
}
Line 214... Line 214...
214 
 
 214 
 
215 
void r600_pcie_gart_fini(struct radeon_device *rdev)
 215 
void r600_pcie_gart_fini(struct radeon_device *rdev)
Line 1135... Line 1135...
1135 
{
 1135 
{
1136 
	WREG32(CP_RB_WPTR, rdev->cp.wptr);
 1136 
	WREG32(CP_RB_WPTR, rdev->cp.wptr);
1137 
	(void)RREG32(CP_RB_WPTR);
 1137 
	(void)RREG32(CP_RB_WPTR);
1138 
}
 1138 
}
Line -... Line 1139...
- 
 
 1139 
 
- 
 
 1140 
void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
- 
 
 1141 
{
- 
 
 1142 
	u32 rb_bufsz;
- 
 
 1143 
 
- 
 
 1144 
	/* Align ring size */
- 
 
 1145 
	rb_bufsz = drm_order(ring_size / 8);
- 
 
 1146 
	ring_size = (1 << (rb_bufsz + 1)) * 4;
- 
 
 1147 
	rdev->cp.ring_size = ring_size;
- 
 
 1148 
	rdev->cp.align_mask = 16 - 1;
- 
 
 1149 
}
- 
 
 1150 
 
- 
 
 1151 
 
- 
 
 1152 
/*
- 
 
 1153 
 * GPU scratch registers helpers function.
- 
 
 1154 
 */
- 
 
 1155 
void r600_scratch_init(struct radeon_device *rdev)
- 
 
 1156 
{
Line -... Line 1157...
- 
 
 1157 
	int i;
- 
 
 1158 
 
- 
 
 1159 
	rdev->scratch.num_reg = 7;
- 
 
 1160 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
- 
 
 1161 
		rdev->scratch.free[i] = true;
- 
 
 1162 
		rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1139 
 
 1163 
	}
1140 
 
 1164 
}
1141 
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 1165 
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1142 
			 uint32_t tiling_flags, uint32_t pitch,
 1166 
			 uint32_t tiling_flags, uint32_t pitch,
1143 
			 uint32_t offset, uint32_t obj_size)
 1167 
			 uint32_t offset, uint32_t obj_size)
Line 1181... Line 1205...
1181 
		if (r)
 1205 
		if (r)
1182 
			return r;
 1206 
			return r;
1183 
	}
 1207 
	}
1184 
	r600_gpu_init(rdev);
 1208 
	r600_gpu_init(rdev);
Line 1185... Line 1209...
1185 
 
 1209 
 
1186 
	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 1210 
//	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1187 
			      &rdev->r600_blit.shader_gpu_addr);
 1211 
//			      &rdev->r600_blit.shader_gpu_addr);
1188 
	if (r) {
 1212 
//	if (r) {
1189 
		DRM_ERROR("failed to pin blit object %d\n", r);
 1213 
//		DRM_ERROR("failed to pin blit object %d\n", r);
1190 
		return r;
 1214 
//		return r;
Line 1191... Line 1215...
1191 
	}
 1215 
//	}
1192 
 
 1216 
 
1193 
	r = radeon_ring_init(rdev, rdev->cp.ring_size);
 1217 
//	r = radeon_ring_init(rdev, rdev->cp.ring_size);
1194 
	if (r)
 1218 
//	if (r)
1195 
		return r;
 1219 
//		return r;
1196 
	r = r600_cp_load_microcode(rdev);
 1220 
//	r = r600_cp_load_microcode(rdev);
1197 
	if (r)
 1221 
//	if (r)
1198 
		return r;
 1222 
//		return r;
1199 
	r = r600_cp_resume(rdev);
 1223 
//	r = r600_cp_resume(rdev);
1200 
	if (r)
 1224 
//	if (r)
1201 
		return r;
 1225 
//		return r;
1202 
	/* write back buffer are not vital so don't worry about failure */
 1226 
	/* write back buffer are not vital so don't worry about failure */
1203 
	r600_wb_enable(rdev);
 1227 
//	r600_wb_enable(rdev);
Line 1204... Line 1228...
1204 
	return 0;
 1228 
	return 0;
1205 
}
 1229 
}
Line 1277... Line 1301...
1277 
		return r;
 1301 
		return r;
1278 
	/* Memory manager */
 1302 
	/* Memory manager */
1279 
	r = radeon_object_init(rdev);
 1303 
	r = radeon_object_init(rdev);
1280 
	if (r)
 1304 
	if (r)
1281 
		return r;
 1305 
		return r;
1282 
	rdev->cp.ring_obj = NULL;
 1306 
//	rdev->cp.ring_obj = NULL;
1283 
	r600_ring_init(rdev, 1024 * 1024);
 1307 
//	r600_ring_init(rdev, 1024 * 1024);
Line 1284... Line 1308...
1284 
 
 1308 
 
1285 
	if (!rdev->me_fw || !rdev->pfp_fw) {
 1309 
//	if (!rdev->me_fw || !rdev->pfp_fw) {
1286 
		r = r600_cp_init_microcode(rdev);
 1310 
//		r = r600_cp_init_microcode(rdev);
1287 
		if (r) {
 1311 
//		if (r) {
1288 
			DRM_ERROR("Failed to load firmware!\n");
 1312 
//			DRM_ERROR("Failed to load firmware!\n");
1289 
			return r;
 1313 
//			return r;
1290 
		}
 1314 
//		}
Line 1291... Line 1315...
1291 
	}
 1315 
//	}
1292 
 
 1316 
 
1293 
	r = r600_pcie_gart_init(rdev);
 1317 
	r = r600_pcie_gart_init(rdev);
Line 1294... Line 1318...
1294 
	if (r)
 1318 
	if (r)
1295 
		return r;
 1319 
		return r;
1296 
 
 1320 
 
1297 
	rdev->accel_working = true;
 1321 
	rdev->accel_working = true;
1298 
	r = r600_blit_init(rdev);
 1322 
//	r = r600_blit_init(rdev);
1299 
	if (r) {
 1323 
//	if (r) {
Line 1300... Line 1324...
1300 
		DRM_ERROR("radeon: failled blitter (%d).\n", r);
 1324 
//		DRM_ERROR("radeon: failled blitter (%d).\n", r);
1301 
		return r;
 1325 
//		return r;
1302 
	}
 1326 
//	}
1303 
 
 1327