WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r520.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "r520d.h"
 
/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
 
int r520_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;
 
	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(R520_MC_STATUS);
		if (tmp & R520_MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}
 
static void r520_gpu_init(struct radeon_device *rdev)
{
	unsigned pipe_select_current, gb_pipe_select, tmp;
 
	rv515_vga_render_disable(rdev);
	/*
	 * DST_PIPE_CONFIG		0x170C
	 * GB_TILE_CONFIG		0x4018
	 * GB_FIFO_SIZE			0x4024
	 * GB_PIPE_SELECT		0x402C
	 * GB_PIPE_SELECT2              0x4124
	 *	Z_PIPE_SHIFT			0
	 *	Z_PIPE_MASK			0x000000003
	 * GB_FIFO_SIZE2                0x4128
	 *	SC_SFIFO_SIZE_SHIFT		0
	 *	SC_SFIFO_SIZE_MASK		0x000000003
	 *	SC_MFIFO_SIZE_SHIFT		2
	 *	SC_MFIFO_SIZE_MASK		0x00000000C
	 *	FG_SFIFO_SIZE_SHIFT		4
	 *	FG_SFIFO_SIZE_MASK		0x000000030
	 *	ZB_MFIFO_SIZE_SHIFT		6
	 *	ZB_MFIFO_SIZE_MASK		0x0000000C0
	 * GA_ENHANCE			0x4274
	 * SU_REG_DEST			0x42C8
	 */
	/* workaround for RV530 */
	if (rdev->family == CHIP_RV530) {
		WREG32(0x4128, 0xFF);
	}
	r420_pipes_init(rdev);
	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	pipe_select_current = (tmp >> 2) & 3;
	tmp = (1 << pipe_select_current) |
	      (((gb_pipe_select >> 8) & 0xF) << 4);
	WREG32_PLL(0x000D, tmp);
	if (r520_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}
 
static void r520_vram_get_type(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	rdev->mc.vram_width = 128;
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32_MC(R520_MC_CNTL0);
	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
	case 0:
		rdev->mc.vram_width = 32;
		break;
	case 1:
		rdev->mc.vram_width = 64;
		break;
	case 2:
		rdev->mc.vram_width = 128;
		break;
	case 3:
		rdev->mc.vram_width = 256;
		break;
	default:
		rdev->mc.vram_width = 128;
		break;
	}
	if (tmp & R520_MC_CHANNEL_SIZE)
		rdev->mc.vram_width *= 2;
}
 
static void r520_mc_init(struct radeon_device *rdev)
{
 
	r520_vram_get_type(rdev);
	r100_vram_init_sizes(rdev);
	radeon_vram_location(rdev, &rdev->mc, 0);
	rdev->mc.gtt_base_align = 0;
	if (!(rdev->flags & RADEON_IS_AGP))
		radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}
 
static void r520_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;
 
	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);
 
	/* Wait for mc idle */
	if (r520_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	/* Write VRAM size in case we are limiting it */
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
	/* Program MC, should be a 32bits limited address space */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32_MC(R_000005_MC_AGP_LOCATION,
			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		WREG32_MC(R_000007_AGP_BASE_2,
			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
	} else {
		WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
		WREG32_MC(R_000006_AGP_BASE, 0);
		WREG32_MC(R_000007_AGP_BASE_2, 0);
	}
 
	rv515_mc_resume(rdev, &save);
}
 
static int r520_startup(struct radeon_device *rdev)
{
	int r;
 
	r520_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	r520_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		return r;
	}
 
	/* Enable IRQ */
	if (!rdev->irq.installed) {
		r = radeon_irq_kms_init(rdev);
		if (r)
			return r;
	}
 
	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
    r = r100_cp_init(rdev, 1024 * 1024);
    if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
        return r;
    }
 
	r = radeon_ib_pool_init(rdev);
	if (r) {
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
		return r;
	}
 
	return 0;
}
 
 
 
int r520_init(struct radeon_device *rdev)
{
	int r;
 
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize AGP */
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			radeon_agp_disable(rdev);
		}
	}
	/* initialize memory controller */
	r520_mc_init(rdev);
	rv515_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
 
 
 
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rv370_pcie_gart_init(rdev);
	if (r)
		return r;
	rv515_set_safe_registers(rdev);
 
	rdev->accel_working = true;
	r = r520_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		rv370_pcie_gart_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

Rev 3120	Rev 3764
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include "radeon.h"	29	#include "radeon.h"
30	#include "radeon_asic.h"	30	#include "radeon_asic.h"
31	#include "atom.h"	31	#include "atom.h"
32	#include "r520d.h"	32	#include "r520d.h"
33		33
34	/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */	34	/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
35		35
36	int r520_mc_wait_for_idle(struct radeon_device *rdev)	36	int r520_mc_wait_for_idle(struct radeon_device *rdev)
37	{	37	{
38	unsigned i;	38	unsigned i;
39	uint32_t tmp;	39	uint32_t tmp;
40		40
41	for (i = 0; i < rdev->usec_timeout; i++) {	41	for (i = 0; i < rdev->usec_timeout; i++) {
42	/* read MC_STATUS */	42	/* read MC_STATUS */
43	tmp = RREG32_MC(R520_MC_STATUS);	43	tmp = RREG32_MC(R520_MC_STATUS);
44	if (tmp & R520_MC_STATUS_IDLE) {	44	if (tmp & R520_MC_STATUS_IDLE) {
45	return 0;	45	return 0;
46	}	46	}
47	DRM_UDELAY(1);	47	DRM_UDELAY(1);
48	}	48	}
49	return -1;	49	return -1;
50	}	50	}
51		51
52	static void r520_gpu_init(struct radeon_device *rdev)	52	static void r520_gpu_init(struct radeon_device *rdev)
53	{	53	{
54	unsigned pipe_select_current, gb_pipe_select, tmp;	54	unsigned pipe_select_current, gb_pipe_select, tmp;
55		55
56	rv515_vga_render_disable(rdev);	56	rv515_vga_render_disable(rdev);
57	/*	57	/*
58	* DST_PIPE_CONFIG 0x170C	58	* DST_PIPE_CONFIG 0x170C
59	* GB_TILE_CONFIG 0x4018	59	* GB_TILE_CONFIG 0x4018
60	* GB_FIFO_SIZE 0x4024	60	* GB_FIFO_SIZE 0x4024
61	* GB_PIPE_SELECT 0x402C	61	* GB_PIPE_SELECT 0x402C
62	* GB_PIPE_SELECT2 0x4124	62	* GB_PIPE_SELECT2 0x4124
63	* Z_PIPE_SHIFT 0	63	* Z_PIPE_SHIFT 0
64	* Z_PIPE_MASK 0x000000003	64	* Z_PIPE_MASK 0x000000003
65	* GB_FIFO_SIZE2 0x4128	65	* GB_FIFO_SIZE2 0x4128
66	* SC_SFIFO_SIZE_SHIFT 0	66	* SC_SFIFO_SIZE_SHIFT 0
67	* SC_SFIFO_SIZE_MASK 0x000000003	67	* SC_SFIFO_SIZE_MASK 0x000000003
68	* SC_MFIFO_SIZE_SHIFT 2	68	* SC_MFIFO_SIZE_SHIFT 2
69	* SC_MFIFO_SIZE_MASK 0x00000000C	69	* SC_MFIFO_SIZE_MASK 0x00000000C
70	* FG_SFIFO_SIZE_SHIFT 4	70	* FG_SFIFO_SIZE_SHIFT 4
71	* FG_SFIFO_SIZE_MASK 0x000000030	71	* FG_SFIFO_SIZE_MASK 0x000000030
72	* ZB_MFIFO_SIZE_SHIFT 6	72	* ZB_MFIFO_SIZE_SHIFT 6
73	* ZB_MFIFO_SIZE_MASK 0x0000000C0	73	* ZB_MFIFO_SIZE_MASK 0x0000000C0
74	* GA_ENHANCE 0x4274	74	* GA_ENHANCE 0x4274
75	* SU_REG_DEST 0x42C8	75	* SU_REG_DEST 0x42C8
76	*/	76	*/
77	/* workaround for RV530 */	77	/* workaround for RV530 */
78	if (rdev->family == CHIP_RV530) {	78	if (rdev->family == CHIP_RV530) {
79	WREG32(0x4128, 0xFF);	79	WREG32(0x4128, 0xFF);
80	}	80	}
81	r420_pipes_init(rdev);	81	r420_pipes_init(rdev);
82	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);	82	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
83	tmp = RREG32(R300_DST_PIPE_CONFIG);	83	tmp = RREG32(R300_DST_PIPE_CONFIG);
84	pipe_select_current = (tmp >> 2) & 3;	84	pipe_select_current = (tmp >> 2) & 3;
85	tmp = (1 << pipe_select_current) \|	85	tmp = (1 << pipe_select_current) \|
86	(((gb_pipe_select >> 8) & 0xF) << 4);	86	(((gb_pipe_select >> 8) & 0xF) << 4);
87	WREG32_PLL(0x000D, tmp);	87	WREG32_PLL(0x000D, tmp);
88	if (r520_mc_wait_for_idle(rdev)) {	88	if (r520_mc_wait_for_idle(rdev)) {
89	printk(KERN_WARNING "Failed to wait MC idle while "	89	printk(KERN_WARNING "Failed to wait MC idle while "
90	"programming pipes. Bad things might happen.\n");	90	"programming pipes. Bad things might happen.\n");
91	}	91	}
92	}	92	}
93		93
94	static void r520_vram_get_type(struct radeon_device *rdev)	94	static void r520_vram_get_type(struct radeon_device *rdev)
95	{	95	{
96	uint32_t tmp;	96	uint32_t tmp;
97		97
98	rdev->mc.vram_width = 128;	98	rdev->mc.vram_width = 128;
99	rdev->mc.vram_is_ddr = true;	99	rdev->mc.vram_is_ddr = true;
100	tmp = RREG32_MC(R520_MC_CNTL0);	100	tmp = RREG32_MC(R520_MC_CNTL0);
101	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {	101	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
102	case 0:	102	case 0:
103	rdev->mc.vram_width = 32;	103	rdev->mc.vram_width = 32;
104	break;	104	break;
105	case 1:	105	case 1:
106	rdev->mc.vram_width = 64;	106	rdev->mc.vram_width = 64;
107	break;	107	break;
108	case 2:	108	case 2:
109	rdev->mc.vram_width = 128;	109	rdev->mc.vram_width = 128;
110	break;	110	break;
111	case 3:	111	case 3:
112	rdev->mc.vram_width = 256;	112	rdev->mc.vram_width = 256;
113	break;	113	break;
114	default:	114	default:
115	rdev->mc.vram_width = 128;	115	rdev->mc.vram_width = 128;
116	break;	116	break;
117	}	117	}
118	if (tmp & R520_MC_CHANNEL_SIZE)	118	if (tmp & R520_MC_CHANNEL_SIZE)
119	rdev->mc.vram_width *= 2;	119	rdev->mc.vram_width *= 2;
120	}	120	}
121		121
122	static void r520_mc_init(struct radeon_device *rdev)	122	static void r520_mc_init(struct radeon_device *rdev)
123	{	123	{
124		124
125	r520_vram_get_type(rdev);	125	r520_vram_get_type(rdev);
126	r100_vram_init_sizes(rdev);	126	r100_vram_init_sizes(rdev);
127	radeon_vram_location(rdev, &rdev->mc, 0);	127	radeon_vram_location(rdev, &rdev->mc, 0);
128	rdev->mc.gtt_base_align = 0;	128	rdev->mc.gtt_base_align = 0;
129	if (!(rdev->flags & RADEON_IS_AGP))	129	if (!(rdev->flags & RADEON_IS_AGP))
130	radeon_gtt_location(rdev, &rdev->mc);	130	radeon_gtt_location(rdev, &rdev->mc);
131	radeon_update_bandwidth_info(rdev);	131	radeon_update_bandwidth_info(rdev);
132	}	132	}
133		133
134	static void r520_mc_program(struct radeon_device *rdev)	134	static void r520_mc_program(struct radeon_device *rdev)
135	{	135	{
136	struct rv515_mc_save save;	136	struct rv515_mc_save save;
137		137
138	/* Stops all mc clients */	138	/* Stops all mc clients */
139	rv515_mc_stop(rdev, &save);	139	rv515_mc_stop(rdev, &save);
140		140
141	/* Wait for mc idle */	141	/* Wait for mc idle */
142	if (r520_mc_wait_for_idle(rdev))	142	if (r520_mc_wait_for_idle(rdev))
143	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");	143	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
144	/* Write VRAM size in case we are limiting it */	144	/* Write VRAM size in case we are limiting it */
145	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);	145	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
146	/* Program MC, should be a 32bits limited address space */	146	/* Program MC, should be a 32bits limited address space */
147	WREG32_MC(R_000004_MC_FB_LOCATION,	147	WREG32_MC(R_000004_MC_FB_LOCATION,
148	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|	148	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|
149	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));	149	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
150	WREG32(R_000134_HDP_FB_LOCATION,	150	WREG32(R_000134_HDP_FB_LOCATION,
151	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));	151	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
152	if (rdev->flags & RADEON_IS_AGP) {	152	if (rdev->flags & RADEON_IS_AGP) {
153	WREG32_MC(R_000005_MC_AGP_LOCATION,	153	WREG32_MC(R_000005_MC_AGP_LOCATION,
154	S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) \|	154	S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
155	S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));	155	S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
156	WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));	156	WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
157	WREG32_MC(R_000007_AGP_BASE_2,	157	WREG32_MC(R_000007_AGP_BASE_2,
158	S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));	158	S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
159	} else {	159	} else {
160	WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);	160	WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
161	WREG32_MC(R_000006_AGP_BASE, 0);	161	WREG32_MC(R_000006_AGP_BASE, 0);
162	WREG32_MC(R_000007_AGP_BASE_2, 0);	162	WREG32_MC(R_000007_AGP_BASE_2, 0);
163	}	163	}
164		164
165	rv515_mc_resume(rdev, &save);	165	rv515_mc_resume(rdev, &save);
166	}	166	}
167		167
168	static int r520_startup(struct radeon_device *rdev)	168	static int r520_startup(struct radeon_device *rdev)
169	{	169	{
170	int r;	170	int r;
171		171
172	r520_mc_program(rdev);	172	r520_mc_program(rdev);
173	/* Resume clock */	173	/* Resume clock */
174	rv515_clock_startup(rdev);	174	rv515_clock_startup(rdev);
175	/* Initialize GPU configuration (# pipes, ...) */	175	/* Initialize GPU configuration (# pipes, ...) */
176	r520_gpu_init(rdev);	176	r520_gpu_init(rdev);
177	/* Initialize GART (initialize after TTM so we can allocate	177	/* Initialize GART (initialize after TTM so we can allocate
178	* memory through TTM but finalize after TTM) */	178	* memory through TTM but finalize after TTM) */
179	if (rdev->flags & RADEON_IS_PCIE) {	179	if (rdev->flags & RADEON_IS_PCIE) {
180	r = rv370_pcie_gart_enable(rdev);	180	r = rv370_pcie_gart_enable(rdev);
181	if (r)	181	if (r)
182	return r;	182	return r;
183	}	183	}
184		184
185	/* allocate wb buffer */	185	/* allocate wb buffer */
186	r = radeon_wb_init(rdev);	186	r = radeon_wb_init(rdev);
187	if (r)	187	if (r)
188	return r;	188	return r;
189		189
190	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);	190	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
191	if (r) {	191	if (r) {
192	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);	192	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
193	return r;	193	return r;
194	}	194	}
195		195
196	/* Enable IRQ */	196	/* Enable IRQ */
-		197	if (!rdev->irq.installed) {
-		198	r = radeon_irq_kms_init(rdev);
-		199	if (r)
-		200	return r;
-		201	}
-		202
197	rs600_irq_set(rdev);	203	rs600_irq_set(rdev);
198	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);	204	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
199	/* 1M ring buffer */	205	/* 1M ring buffer */
200	r = r100_cp_init(rdev, 1024 * 1024);	206	r = r100_cp_init(rdev, 1024 * 1024);
201	if (r) {	207	if (r) {
202	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);	208	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
203	return r;	209	return r;
204	}	210	}
205		211
206	r = radeon_ib_pool_init(rdev);	212	r = radeon_ib_pool_init(rdev);
207	if (r) {	213	if (r) {
208	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);	214	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
209	return r;	215	return r;
210	}	216	}
211		217
212	return 0;	218	return 0;
213	}	219	}
214		220
215		221
216		222
217	int r520_init(struct radeon_device *rdev)	223	int r520_init(struct radeon_device *rdev)
218	{	224	{
219	int r;	225	int r;
220		226
221	/* Initialize scratch registers */	227	/* Initialize scratch registers */
222	radeon_scratch_init(rdev);	228	radeon_scratch_init(rdev);
223	/* Initialize surface registers */	229	/* Initialize surface registers */
224	radeon_surface_init(rdev);	230	radeon_surface_init(rdev);
225	/* restore some register to sane defaults */	231	/* restore some register to sane defaults */
226	r100_restore_sanity(rdev);	232	r100_restore_sanity(rdev);
227	/* TODO: disable VGA need to use VGA request */	233	/* TODO: disable VGA need to use VGA request */
228	/* BIOS*/	234	/* BIOS*/
229	if (!radeon_get_bios(rdev)) {	235	if (!radeon_get_bios(rdev)) {
230	if (ASIC_IS_AVIVO(rdev))	236	if (ASIC_IS_AVIVO(rdev))
231	return -EINVAL;	237	return -EINVAL;
232	}	238	}
233	if (rdev->is_atom_bios) {	239	if (rdev->is_atom_bios) {
234	r = radeon_atombios_init(rdev);	240	r = radeon_atombios_init(rdev);
235	if (r)	241	if (r)
236	return r;	242	return r;
237	} else {	243	} else {
238	dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");	244	dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
239	return -EINVAL;	245	return -EINVAL;
240	}	246	}
241	/* Reset gpu before posting otherwise ATOM will enter infinite loop */	247	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
242	if (radeon_asic_reset(rdev)) {	248	if (radeon_asic_reset(rdev)) {
243	dev_warn(rdev->dev,	249	dev_warn(rdev->dev,
244	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",	250	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
245	RREG32(R_000E40_RBBM_STATUS),	251	RREG32(R_000E40_RBBM_STATUS),
246	RREG32(R_0007C0_CP_STAT));	252	RREG32(R_0007C0_CP_STAT));
247	}	253	}
248	/* check if cards are posted or not */	254	/* check if cards are posted or not */
249	if (radeon_boot_test_post_card(rdev) == false)	255	if (radeon_boot_test_post_card(rdev) == false)
250	return -EINVAL;	256	return -EINVAL;
251		257
252	if (!radeon_card_posted(rdev) && rdev->bios) {	258	if (!radeon_card_posted(rdev) && rdev->bios) {
253	DRM_INFO("GPU not posted. posting now...\n");	259	DRM_INFO("GPU not posted. posting now...\n");
254	atom_asic_init(rdev->mode_info.atom_context);	260	atom_asic_init(rdev->mode_info.atom_context);
255	}	261	}
256	/* Initialize clocks */	262	/* Initialize clocks */
257	radeon_get_clock_info(rdev->ddev);	263	radeon_get_clock_info(rdev->ddev);
258	/* initialize AGP */	264	/* initialize AGP */
259	if (rdev->flags & RADEON_IS_AGP) {	265	if (rdev->flags & RADEON_IS_AGP) {
260	r = radeon_agp_init(rdev);	266	r = radeon_agp_init(rdev);
261	if (r) {	267	if (r) {
262	radeon_agp_disable(rdev);	268	radeon_agp_disable(rdev);
263	}	269	}
264	}	270	}
265	/* initialize memory controller */	271	/* initialize memory controller */
266	r520_mc_init(rdev);	272	r520_mc_init(rdev);
267	rv515_debugfs(rdev);	273	rv515_debugfs(rdev);
268	/* Fence driver */	274	/* Fence driver */
269	r = radeon_fence_driver_init(rdev);	275	r = radeon_fence_driver_init(rdev);
270	if (r)	276	if (r)
271	return r;	-
272	r = radeon_irq_kms_init(rdev);	-
273	if (r)	-
274	return r;	277	return r;
275	/* Memory manager */	278	/* Memory manager */
276	r = radeon_bo_init(rdev);	279	r = radeon_bo_init(rdev);
277	if (r)	280	if (r)
278	return r;	281	return r;
279	r = rv370_pcie_gart_init(rdev);	282	r = rv370_pcie_gart_init(rdev);
280	if (r)	283	if (r)
281	return r;	284	return r;
282	rv515_set_safe_registers(rdev);	285	rv515_set_safe_registers(rdev);
283		286
284	rdev->accel_working = true;	287	rdev->accel_working = true;
285	r = r520_startup(rdev);	288	r = r520_startup(rdev);
286	if (r) {	289	if (r) {
287	/* Somethings want wront with the accel init stop accel */	290	/* Somethings want wront with the accel init stop accel */
288	dev_err(rdev->dev, "Disabling GPU acceleration\n");	291	dev_err(rdev->dev, "Disabling GPU acceleration\n");
289	rv370_pcie_gart_fini(rdev);	292	rv370_pcie_gart_fini(rdev);
290	rdev->accel_working = false;	293	rdev->accel_working = false;
291	}	294	}
292	return 0;	295	return 0;
293	}	296	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r520.c – Rev 3120 → 3764