Rev 1430 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1430 | Rev 1963 | ||
|---|---|---|---|
| Line 25... | Line 25... | ||
| 25 | * Alex Deucher |
25 | * Alex Deucher |
| 26 | * Jerome Glisse |
26 | * Jerome Glisse |
| 27 | */ |
27 | */ |
| 28 | #include "drmP.h" |
28 | #include "drmP.h" |
| 29 | #include "radeon.h" |
29 | #include "radeon.h" |
| - | 30 | #include "radeon_asic.h" |
|
| 30 | #include "atom.h" |
31 | #include "atom.h" |
| 31 | #include "r520d.h" |
32 | #include "r520d.h" |
| Line 32... | Line 33... | ||
| 32 | 33 | ||
| Line 50... | Line 51... | ||
| 50 | 51 | ||
| 51 | static void r520_gpu_init(struct radeon_device *rdev) |
52 | static void r520_gpu_init(struct radeon_device *rdev) |
| 52 | { |
53 | { |
| Line 53... | Line -... | ||
| 53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
- | |
| 54 | 54 | unsigned pipe_select_current, gb_pipe_select, tmp; |
|
| 55 | r100_hdp_reset(rdev); |
55 | |
| 56 | rv515_vga_render_disable(rdev); |
56 | rv515_vga_render_disable(rdev); |
| 57 | /* |
57 | /* |
| 58 | * DST_PIPE_CONFIG 0x170C |
58 | * DST_PIPE_CONFIG 0x170C |
| Line 77... | Line 77... | ||
| 77 | /* workaround for RV530 */ |
77 | /* workaround for RV530 */ |
| 78 | if (rdev->family == CHIP_RV530) { |
78 | if (rdev->family == CHIP_RV530) { |
| 79 | WREG32(0x4128, 0xFF); |
79 | WREG32(0x4128, 0xFF); |
| 80 | } |
80 | } |
| 81 | r420_pipes_init(rdev); |
81 | r420_pipes_init(rdev); |
| 82 | gb_pipe_select = RREG32(0x402C); |
82 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
| 83 | tmp = RREG32(0x170C); |
83 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
| 84 | pipe_select_current = (tmp >> 2) & 3; |
84 | pipe_select_current = (tmp >> 2) & 3; |
| 85 | tmp = (1 << pipe_select_current) | |
85 | tmp = (1 << pipe_select_current) | |
| 86 | (((gb_pipe_select >> 8) & 0xF) << 4); |
86 | (((gb_pipe_select >> 8) & 0xF) << 4); |
| 87 | WREG32_PLL(0x000D, tmp); |
87 | WREG32_PLL(0x000D, tmp); |
| 88 | if (r520_mc_wait_for_idle(rdev)) { |
88 | if (r520_mc_wait_for_idle(rdev)) { |
| Line 119... | Line 119... | ||
| 119 | rdev->mc.vram_width *= 2; |
119 | rdev->mc.vram_width *= 2; |
| 120 | } |
120 | } |
| Line 121... | Line 121... | ||
| 121 | 121 | ||
| 122 | void r520_mc_init(struct radeon_device *rdev) |
122 | void r520_mc_init(struct radeon_device *rdev) |
| 123 | { |
- | |
| Line 124... | Line 123... | ||
| 124 | fixed20_12 a; |
123 | { |
| 125 | 124 | ||
| 126 | r520_vram_get_type(rdev); |
125 | r520_vram_get_type(rdev); |
| - | 126 | r100_vram_init_sizes(rdev); |
|
| 127 | r100_vram_init_sizes(rdev); |
127 | radeon_vram_location(rdev, &rdev->mc, 0); |
| 128 | radeon_vram_location(rdev, &rdev->mc, 0); |
128 | rdev->mc.gtt_base_align = 0; |
| 129 | if (!(rdev->flags & RADEON_IS_AGP)) |
- | |
| 130 | radeon_gtt_location(rdev, &rdev->mc); |
- | |
| 131 | /* FIXME: we should enforce default clock in case GPU is not in |
- | |
| 132 | * default setup |
129 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 133 | */ |
- | |
| 134 | a.full = rfixed_const(100); |
- | |
| 135 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
130 | radeon_gtt_location(rdev, &rdev->mc); |
| Line 136... | Line 131... | ||
| 136 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
131 | radeon_update_bandwidth_info(rdev); |
| 137 | } |
132 | } |
| 138 | 133 | ||
| Line 185... | Line 180... | ||
| 185 | r = rv370_pcie_gart_enable(rdev); |
180 | r = rv370_pcie_gart_enable(rdev); |
| 186 | if (r) |
181 | if (r) |
| 187 | return r; |
182 | return r; |
| 188 | } |
183 | } |
| 189 | /* Enable IRQ */ |
184 | /* Enable IRQ */ |
| 190 | // rs600_irq_set(rdev); |
- | |
| 191 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
185 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| 192 | /* 1M ring buffer */ |
186 | /* 1M ring buffer */ |
| 193 | r = r100_cp_init(rdev, 1024 * 1024); |
187 | r = r100_cp_init(rdev, 1024 * 1024); |
| 194 | if (r) { |
188 | if (r) { |
| 195 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
189 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| 196 | return r; |
190 | return r; |
| 197 | } |
191 | } |
| 198 | // r = r100_wb_init(rdev); |
- | |
| 199 | // if (r) |
- | |
| 200 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
- | |
| 201 | // r = r100_ib_init(rdev); |
- | |
| 202 | // if (r) { |
- | |
| 203 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
- | |
| 204 | // return r; |
- | |
| 205 | // } |
- | |
| 206 | return 0; |
192 | return 0; |
| 207 | } |
193 | } |
| Line 208... | Line 194... | ||
| 208 | 194 | ||
| 209 | 195 | ||
| 210 | 196 | ||
| Line 211... | Line -... | ||
| 211 | int r520_init(struct radeon_device *rdev) |
- | |
| 212 | { |
- | |
| 213 | int r; |
197 | int r520_init(struct radeon_device *rdev) |
| 214 | 198 | { |
|
| 215 | ENTER(); |
199 | int r; |
| 216 | 200 | ||
| - | 201 | /* Initialize scratch registers */ |
|
| - | 202 | radeon_scratch_init(rdev); |
|
| 217 | /* Initialize scratch registers */ |
203 | /* Initialize surface registers */ |
| 218 | radeon_scratch_init(rdev); |
204 | radeon_surface_init(rdev); |
| 219 | /* Initialize surface registers */ |
205 | /* restore some register to sane defaults */ |
| 220 | radeon_surface_init(rdev); |
206 | r100_restore_sanity(rdev); |
| 221 | /* TODO: disable VGA need to use VGA request */ |
207 | /* TODO: disable VGA need to use VGA request */ |
| Line 231... | Line 217... | ||
| 231 | } else { |
217 | } else { |
| 232 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
218 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
| 233 | return -EINVAL; |
219 | return -EINVAL; |
| 234 | } |
220 | } |
| 235 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
221 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 236 | if (radeon_gpu_reset(rdev)) { |
222 | if (radeon_asic_reset(rdev)) { |
| 237 | dev_warn(rdev->dev, |
223 | dev_warn(rdev->dev, |
| 238 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
224 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 239 | RREG32(R_000E40_RBBM_STATUS), |
225 | RREG32(R_000E40_RBBM_STATUS), |
| 240 | RREG32(R_0007C0_CP_STAT)); |
226 | RREG32(R_0007C0_CP_STAT)); |
| 241 | } |
227 | } |
| Line 247... | Line 233... | ||
| 247 | DRM_INFO("GPU not posted. posting now...\n"); |
233 | DRM_INFO("GPU not posted. posting now...\n"); |
| 248 | atom_asic_init(rdev->mode_info.atom_context); |
234 | atom_asic_init(rdev->mode_info.atom_context); |
| 249 | } |
235 | } |
| 250 | /* Initialize clocks */ |
236 | /* Initialize clocks */ |
| 251 | radeon_get_clock_info(rdev->ddev); |
237 | radeon_get_clock_info(rdev->ddev); |
| 252 | /* Initialize power management */ |
- | |
| 253 | radeon_pm_init(rdev); |
- | |
| 254 | /* initialize AGP */ |
238 | /* initialize AGP */ |
| 255 | if (rdev->flags & RADEON_IS_AGP) { |
239 | if (rdev->flags & RADEON_IS_AGP) { |
| 256 | r = radeon_agp_init(rdev); |
240 | r = radeon_agp_init(rdev); |
| 257 | if (r) { |
241 | if (r) { |
| 258 | radeon_agp_disable(rdev); |
242 | radeon_agp_disable(rdev); |
| Line 260... | Line 244... | ||
| 260 | } |
244 | } |
| 261 | /* initialize memory controller */ |
245 | /* initialize memory controller */ |
| 262 | r520_mc_init(rdev); |
246 | r520_mc_init(rdev); |
| 263 | rv515_debugfs(rdev); |
247 | rv515_debugfs(rdev); |
| 264 | /* Fence driver */ |
248 | /* Fence driver */ |
| 265 | // r = radeon_fence_driver_init(rdev); |
- | |
| 266 | // if (r) |
- | |
| 267 | // return r; |
- | |
| 268 | // r = radeon_irq_kms_init(rdev); |
- | |
| 269 | // if (r) |
- | |
| 270 | // return r; |
- | |
| 271 | /* Memory manager */ |
249 | /* Memory manager */ |
| 272 | r = radeon_bo_init(rdev); |
250 | r = radeon_bo_init(rdev); |
| 273 | if (r) |
251 | if (r) |
| 274 | return r; |
252 | return r; |
| 275 | r = rv370_pcie_gart_init(rdev); |
253 | r = rv370_pcie_gart_init(rdev); |
| Line 279... | Line 257... | ||
| 279 | rdev->accel_working = true; |
257 | rdev->accel_working = true; |
| 280 | r = r520_startup(rdev); |
258 | r = r520_startup(rdev); |
| 281 | if (r) { |
259 | if (r) { |
| 282 | /* Somethings want wront with the accel init stop accel */ |
260 | /* Somethings want wront with the accel init stop accel */ |
| 283 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
261 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| 284 | // r100_cp_fini(rdev); |
- | |
| 285 | // r100_wb_fini(rdev); |
- | |
| 286 | // r100_ib_fini(rdev); |
- | |
| 287 | rv370_pcie_gart_fini(rdev); |
262 | rv370_pcie_gart_fini(rdev); |
| 288 | // radeon_agp_fini(rdev); |
- | |
| 289 | rdev->accel_working = false; |
263 | rdev->accel_working = false; |
| 290 | } |
264 | } |
| 291 | - | ||
| 292 | LEAVE(); |
- | |
| 293 | - | ||
| 294 | return 0; |
265 | return 0; |
| 295 | } |
266 | } |