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Rev 1428 | Rev 1430 | ||
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Line 49... | Line 49... | ||
49 | } |
49 | } |
Line 50... | Line 50... | ||
50 | 50 | ||
51 | static void r520_gpu_init(struct radeon_device *rdev) |
51 | static void r520_gpu_init(struct radeon_device *rdev) |
52 | { |
52 | { |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
- | |
Line 54... | Line 53... | ||
54 | ENTER(); |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
55 | 54 | ||
56 | r100_hdp_reset(rdev); |
55 | r100_hdp_reset(rdev); |
57 | rv515_vga_render_disable(rdev); |
56 | rv515_vga_render_disable(rdev); |
Line 93... | Line 92... | ||
93 | } |
92 | } |
Line 94... | Line 93... | ||
94 | 93 | ||
95 | static void r520_vram_get_type(struct radeon_device *rdev) |
94 | static void r520_vram_get_type(struct radeon_device *rdev) |
96 | { |
95 | { |
97 | uint32_t tmp; |
- | |
Line 98... | Line 96... | ||
98 | ENTER(); |
96 | uint32_t tmp; |
99 | 97 | ||
100 | rdev->mc.vram_width = 128; |
98 | rdev->mc.vram_width = 128; |
101 | rdev->mc.vram_is_ddr = true; |
99 | rdev->mc.vram_is_ddr = true; |
Line 119... | Line 117... | ||
119 | } |
117 | } |
120 | if (tmp & R520_MC_CHANNEL_SIZE) |
118 | if (tmp & R520_MC_CHANNEL_SIZE) |
121 | rdev->mc.vram_width *= 2; |
119 | rdev->mc.vram_width *= 2; |
122 | } |
120 | } |
Line 123... | Line 121... | ||
123 | 121 | ||
124 | void r520_vram_info(struct radeon_device *rdev) |
122 | void r520_mc_init(struct radeon_device *rdev) |
125 | { |
123 | { |
Line 126... | Line 124... | ||
126 | fixed20_12 a; |
124 | fixed20_12 a; |
127 | - | ||
128 | r520_vram_get_type(rdev); |
125 | |
- | 126 | r520_vram_get_type(rdev); |
|
- | 127 | r100_vram_init_sizes(rdev); |
|
- | 128 | radeon_vram_location(rdev, &rdev->mc, 0); |
|
129 | 129 | if (!(rdev->flags & RADEON_IS_AGP)) |
|
130 | r100_vram_init_sizes(rdev); |
130 | radeon_gtt_location(rdev, &rdev->mc); |
131 | /* FIXME: we should enforce default clock in case GPU is not in |
131 | /* FIXME: we should enforce default clock in case GPU is not in |
132 | * default setup |
132 | * default setup |
133 | */ |
133 | */ |
Line 249... | Line 249... | ||
249 | } |
249 | } |
250 | /* Initialize clocks */ |
250 | /* Initialize clocks */ |
251 | radeon_get_clock_info(rdev->ddev); |
251 | radeon_get_clock_info(rdev->ddev); |
252 | /* Initialize power management */ |
252 | /* Initialize power management */ |
253 | radeon_pm_init(rdev); |
253 | radeon_pm_init(rdev); |
254 | /* Get vram informations */ |
254 | /* initialize AGP */ |
255 | r520_vram_info(rdev); |
- | |
256 | /* Initialize memory controller (also test AGP) */ |
255 | if (rdev->flags & RADEON_IS_AGP) { |
257 | r = r420_mc_init(rdev); |
256 | r = radeon_agp_init(rdev); |
258 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
- | |
259 | if (r) |
257 | if (r) { |
- | 258 | radeon_agp_disable(rdev); |
|
- | 259 | } |
|
- | 260 | } |
|
- | 261 | /* initialize memory controller */ |
|
260 | return r; |
262 | r520_mc_init(rdev); |
261 | rv515_debugfs(rdev); |
263 | rv515_debugfs(rdev); |
262 | /* Fence driver */ |
264 | /* Fence driver */ |
263 | // r = radeon_fence_driver_init(rdev); |
265 | // r = radeon_fence_driver_init(rdev); |
264 | // if (r) |
266 | // if (r) |
265 | // return r; |
267 | // return r; |
Line 282... | Line 284... | ||
282 | // r100_cp_fini(rdev); |
284 | // r100_cp_fini(rdev); |
283 | // r100_wb_fini(rdev); |
285 | // r100_wb_fini(rdev); |
284 | // r100_ib_fini(rdev); |
286 | // r100_ib_fini(rdev); |
285 | rv370_pcie_gart_fini(rdev); |
287 | rv370_pcie_gart_fini(rdev); |
286 | // radeon_agp_fini(rdev); |
288 | // radeon_agp_fini(rdev); |
287 | // radeon_irq_kms_fini(rdev); |
- | |
288 | rdev->accel_working = false; |
289 | rdev->accel_working = false; |
289 | } |
290 | } |
Line 290... | Line 291... | ||
290 | 291 |