WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/r420.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include 
#include 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "r100d.h"
#include "r420d.h"
#include "r420_reg_safe.h"
 
void r420_pm_init_profile(struct radeon_device *rdev)
{
	/* default */
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
	/* low sh */
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
	/* mid sh */
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
	/* high sh */
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
	/* low mh */
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
	/* mid mh */
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
	/* high mh */
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
}
 
static void r420_set_reg_safe(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
}
 
void r420_pipes_init(struct radeon_device *rdev)
{
	unsigned tmp;
	unsigned gb_pipe_select;
	unsigned num_pipes;
 
	/* GA_ENHANCE workaround TCL deadlock issue */
	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
	       (1 << 2) | (1 << 3));
	/* add idle wait as per freedesktop.org bug 24041 */
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}
	/* get max number of pipes */
	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
 
	/* SE chips have 1 pipe */
	if ((rdev->pdev->device == 0x5e4c) ||
	    (rdev->pdev->device == 0x5e4f))
		num_pipes = 1;
 
	rdev->num_gb_pipes = num_pipes;
	tmp = 0;
	switch (num_pipes) {
	default:
		/* force to 1 pipe */
		num_pipes = 1;
	case 1:
		tmp = (0 << 1);
		break;
	case 2:
		tmp = (3 << 1);
		break;
	case 3:
		tmp = (6 << 1);
		break;
	case 4:
		tmp = (7 << 1);
		break;
	}
	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
	tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
	WREG32(R300_GB_TILE_CONFIG, tmp);
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}
 
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 
	WREG32(R300_RB2D_DSTCACHE_MODE,
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
	       R300_DC_AUTOFLUSH_ENABLE |
	       R300_DC_DC_DISABLE_IGNORE_PE);
 
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}
 
	if (rdev->family == CHIP_RV530) {
		tmp = RREG32(RV530_GB_PIPE_SELECT2);
		if ((tmp & 3) == 3)
			rdev->num_z_pipes = 2;
		else
			rdev->num_z_pipes = 1;
	} else
		rdev->num_z_pipes = 1;
 
	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
		 rdev->num_gb_pipes, rdev->num_z_pipes);
}
 
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
{
	unsigned long flags;
	u32 r;
 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
	r = RREG32(R_0001FC_MC_IND_DATA);
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
	return r;
}
 
void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
	unsigned long flags;
 
	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
		S_0001F8_MC_IND_WR_EN(1));
	WREG32(R_0001FC_MC_IND_DATA, v);
	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
}
 
static void r420_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}
	if (r420_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
}
 
static void r420_clock_resume(struct radeon_device *rdev)
{
	u32 sclk_cntl;
 
	if (radeon_dynclks != -1 && radeon_dynclks)
		radeon_atom_set_clock_gating(rdev, 1);
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
	if (rdev->family == CHIP_R420)
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
}
 
static void r420_cp_errata_init(struct radeon_device *rdev)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 
	/* RV410 and R420 can lock up if CP DMA to host memory happens
	 * while the 2D engine is busy.
	 *
	 * The proper workaround is to queue a RESYNC at the beginning
	 * of the CP init, apparently.
	 */
	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
	radeon_ring_lock(rdev, ring, 8);
	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
	radeon_ring_write(ring, 0xDEADBEEF);
	radeon_ring_unlock_commit(rdev, ring, false);
}
 
static void r420_cp_errata_fini(struct radeon_device *rdev)
{
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 
	/* Catch the RESYNC we dispatched all the way back,
	 * at the very beginning of the CP init.
	 */
	radeon_ring_lock(rdev, ring, 8);
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(ring, R300_RB3D_DC_FINISH);
	radeon_ring_unlock_commit(rdev, ring, false);
	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
}
 
static int r420_startup(struct radeon_device *rdev)
{
	int r;
 
	/* set common regs */
	r100_set_common_regs(rdev);
	/* program mc */
	r300_mc_program(rdev);
	/* Resume clock */
	r420_clock_resume(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_enable(rdev);
		if (r)
			return r;
	}
	r420_pipes_init(rdev);
 
	/* allocate wb buffer */
	r = radeon_wb_init(rdev);
	if (r)
		return r;
 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		return r;
	}
 
	/* Enable IRQ */
	if (!rdev->irq.installed) {
		r = radeon_irq_kms_init(rdev);
		if (r)
			return r;
	}
 
	r100_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
		return r;
	}
	r420_cp_errata_init(rdev);
 
	r = radeon_ib_pool_init(rdev);
	if (r) {
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
		return r;
	}
 
	return 0;
}
 
 
 
 
 
void r420_fini(struct radeon_device *rdev)
{
	radeon_pm_fini(rdev);
	r100_cp_fini(rdev);
	radeon_wb_fini(rdev);
	radeon_ib_pool_fini(rdev);
	radeon_gem_fini(rdev);
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_fini(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_fini(rdev);
	radeon_agp_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_bo_fini(rdev);
	if (rdev->is_atom_bios) {
		radeon_atombios_fini(rdev);
	} else {
		radeon_combios_fini(rdev);
	}
	kfree(rdev->bios);
	rdev->bios = NULL;
}
 
int r420_init(struct radeon_device *rdev)
{
	int r;
 
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* restore some register to sane defaults */
	r100_restore_sanity(rdev);
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r) {
			return r;
		}
	} else {
		r = radeon_combios_init(rdev);
		if (r) {
			return r;
		}
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;
 
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize AGP */
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			radeon_agp_disable(rdev);
		}
	}
	/* initialize memory controller */
	r300_mc_init(rdev);
	r420_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r) {
		return r;
	}
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r) {
		return r;
	}
	if (rdev->family == CHIP_R420)
		r100_enable_bm(rdev);
 
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_init(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_init(rdev);
		if (r)
			return r;
	}
	r420_set_reg_safe(rdev);
 
	/* Initialize power management */
	radeon_pm_init(rdev);
 
	rdev->accel_working = true;
	r = r420_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r100_cp_fini(rdev);
		radeon_wb_fini(rdev);
		radeon_ib_pool_fini(rdev);
		radeon_irq_kms_fini(rdev);
		if (rdev->flags & RADEON_IS_PCIE)
			rv370_pcie_gart_fini(rdev);
		if (rdev->flags & RADEON_IS_PCI)
			r100_pci_gart_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}
 
/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;
 
	tmp = RREG32(R400_GB_PIPE_SELECT);
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	tmp = RREG32(R300_GB_TILE_CONFIG);
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	return 0;
}
 
static struct drm_info_list r420_pipes_info_list[] = {
	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
};
#endif
 
int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
#else
	return 0;
#endif
}

Rev 5078	Rev 6104
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	#include	28	#include
29	#include	29	#include
30	#include	30	#include
31	#include "radeon_reg.h"	31	#include "radeon_reg.h"
32	#include "radeon.h"	32	#include "radeon.h"
33	#include "radeon_asic.h"	33	#include "radeon_asic.h"
34	#include "atom.h"	34	#include "atom.h"
35	#include "r100d.h"	35	#include "r100d.h"
36	#include "r420d.h"	36	#include "r420d.h"
37	#include "r420_reg_safe.h"	37	#include "r420_reg_safe.h"
38		38
39	void r420_pm_init_profile(struct radeon_device *rdev)	39	void r420_pm_init_profile(struct radeon_device *rdev)
40	{	40	{
41	/* default */	41	/* default */
42	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;	42	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;	43	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;	44	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;	45	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
46	/* low sh */	46	/* low sh */
47	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;	47	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;	48	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;	49	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;	50	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
51	/* mid sh */	51	/* mid sh */
52	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;	52	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;	53	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;	54	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;	55	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
56	/* high sh */	56	/* high sh */
57	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;	57	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;	58	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;	59	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;	60	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
61	/* low mh */	61	/* low mh */
62	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;	62	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;	63	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;	64	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;	65	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
66	/* mid mh */	66	/* mid mh */
67	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;	67	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;	68	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;	69	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;	70	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
71	/* high mh */	71	/* high mh */
72	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;	72	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;	73	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;	74	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;	75	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
76	}	76	}
77		77
78	static void r420_set_reg_safe(struct radeon_device *rdev)	78	static void r420_set_reg_safe(struct radeon_device *rdev)
79	{	79	{
80	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;	80	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);	81	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
82	}	82	}
83		83
84	void r420_pipes_init(struct radeon_device *rdev)	84	void r420_pipes_init(struct radeon_device *rdev)
85	{	85	{
86	unsigned tmp;	86	unsigned tmp;
87	unsigned gb_pipe_select;	87	unsigned gb_pipe_select;
88	unsigned num_pipes;	88	unsigned num_pipes;
89		89
90	/* GA_ENHANCE workaround TCL deadlock issue */	90	/* GA_ENHANCE workaround TCL deadlock issue */
91	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL \|	91	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL \|
92	(1 << 2) \| (1 << 3));	92	(1 << 2) \| (1 << 3));
93	/* add idle wait as per freedesktop.org bug 24041 */	93	/* add idle wait as per freedesktop.org bug 24041 */
94	if (r100_gui_wait_for_idle(rdev)) {	94	if (r100_gui_wait_for_idle(rdev)) {
95	printk(KERN_WARNING "Failed to wait GUI idle while "	95	printk(KERN_WARNING "Failed to wait GUI idle while "
96	"programming pipes. Bad things might happen.\n");	96	"programming pipes. Bad things might happen.\n");
97	}	97	}
98	/* get max number of pipes */	98	/* get max number of pipes */
99	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);	99	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
100	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;	100	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
101		101
102	/* SE chips have 1 pipe */	102	/* SE chips have 1 pipe */
103	if ((rdev->pdev->device == 0x5e4c) \|\|	103	if ((rdev->pdev->device == 0x5e4c) \|\|
104	(rdev->pdev->device == 0x5e4f))	104	(rdev->pdev->device == 0x5e4f))
105	num_pipes = 1;	105	num_pipes = 1;
106		106
107	rdev->num_gb_pipes = num_pipes;	107	rdev->num_gb_pipes = num_pipes;
108	tmp = 0;	108	tmp = 0;
109	switch (num_pipes) {	109	switch (num_pipes) {
110	default:	110	default:
111	/* force to 1 pipe */	111	/* force to 1 pipe */
112	num_pipes = 1;	112	num_pipes = 1;
113	case 1:	113	case 1:
114	tmp = (0 << 1);	114	tmp = (0 << 1);
115	break;	115	break;
116	case 2:	116	case 2:
117	tmp = (3 << 1);	117	tmp = (3 << 1);
118	break;	118	break;
119	case 3:	119	case 3:
120	tmp = (6 << 1);	120	tmp = (6 << 1);
121	break;	121	break;
122	case 4:	122	case 4:
123	tmp = (7 << 1);	123	tmp = (7 << 1);
124	break;	124	break;
125	}	125	}
126	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);	126	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
127	/* Sub pixel 1/12 so we can have 4K rendering according to doc */	127	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
128	tmp \|= R300_TILE_SIZE_16 \| R300_ENABLE_TILING;	128	tmp \|= R300_TILE_SIZE_16 \| R300_ENABLE_TILING;
129	WREG32(R300_GB_TILE_CONFIG, tmp);	129	WREG32(R300_GB_TILE_CONFIG, tmp);
130	if (r100_gui_wait_for_idle(rdev)) {	130	if (r100_gui_wait_for_idle(rdev)) {
131	printk(KERN_WARNING "Failed to wait GUI idle while "	131	printk(KERN_WARNING "Failed to wait GUI idle while "
132	"programming pipes. Bad things might happen.\n");	132	"programming pipes. Bad things might happen.\n");
133	}	133	}
134		134
135	tmp = RREG32(R300_DST_PIPE_CONFIG);	135	tmp = RREG32(R300_DST_PIPE_CONFIG);
136	WREG32(R300_DST_PIPE_CONFIG, tmp \| R300_PIPE_AUTO_CONFIG);	136	WREG32(R300_DST_PIPE_CONFIG, tmp \| R300_PIPE_AUTO_CONFIG);
137		137
138	WREG32(R300_RB2D_DSTCACHE_MODE,	138	WREG32(R300_RB2D_DSTCACHE_MODE,
139	RREG32(R300_RB2D_DSTCACHE_MODE) \|	139	RREG32(R300_RB2D_DSTCACHE_MODE) \|
140	R300_DC_AUTOFLUSH_ENABLE \|	140	R300_DC_AUTOFLUSH_ENABLE \|
141	R300_DC_DC_DISABLE_IGNORE_PE);	141	R300_DC_DC_DISABLE_IGNORE_PE);
142		142
143	if (r100_gui_wait_for_idle(rdev)) {	143	if (r100_gui_wait_for_idle(rdev)) {
144	printk(KERN_WARNING "Failed to wait GUI idle while "	144	printk(KERN_WARNING "Failed to wait GUI idle while "
145	"programming pipes. Bad things might happen.\n");	145	"programming pipes. Bad things might happen.\n");
146	}	146	}
147		147
148	if (rdev->family == CHIP_RV530) {	148	if (rdev->family == CHIP_RV530) {
149	tmp = RREG32(RV530_GB_PIPE_SELECT2);	149	tmp = RREG32(RV530_GB_PIPE_SELECT2);
150	if ((tmp & 3) == 3)	150	if ((tmp & 3) == 3)
151	rdev->num_z_pipes = 2;	151	rdev->num_z_pipes = 2;
152	else	152	else
153	rdev->num_z_pipes = 1;	153	rdev->num_z_pipes = 1;
154	} else	154	} else
155	rdev->num_z_pipes = 1;	155	rdev->num_z_pipes = 1;
156		156
157	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",	157	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
158	rdev->num_gb_pipes, rdev->num_z_pipes);	158	rdev->num_gb_pipes, rdev->num_z_pipes);
159	}	159	}
160		160
161	u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)	161	u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
162	{	162	{
163	unsigned long flags;	163	unsigned long flags;
164	u32 r;	164	u32 r;
165		165
166	spin_lock_irqsave(&rdev->mc_idx_lock, flags);	166	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
167	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));	167	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
168	r = RREG32(R_0001FC_MC_IND_DATA);	168	r = RREG32(R_0001FC_MC_IND_DATA);
169	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);	169	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
170	return r;	170	return r;
171	}	171	}
172		172
173	void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)	173	void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
174	{	174	{
175	unsigned long flags;	175	unsigned long flags;
176		176
177	spin_lock_irqsave(&rdev->mc_idx_lock, flags);	177	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
178	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|	178	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|
179	S_0001F8_MC_IND_WR_EN(1));	179	S_0001F8_MC_IND_WR_EN(1));
180	WREG32(R_0001FC_MC_IND_DATA, v);	180	WREG32(R_0001FC_MC_IND_DATA, v);
181	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);	181	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
182	}	182	}
183		183
184	static void r420_debugfs(struct radeon_device *rdev)	184	static void r420_debugfs(struct radeon_device *rdev)
185	{	185	{
186	if (r100_debugfs_rbbm_init(rdev)) {	186	if (r100_debugfs_rbbm_init(rdev)) {
187	DRM_ERROR("Failed to register debugfs file for RBBM !\n");	187	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
188	}	188	}
189	if (r420_debugfs_pipes_info_init(rdev)) {	189	if (r420_debugfs_pipes_info_init(rdev)) {
190	DRM_ERROR("Failed to register debugfs file for pipes !\n");	190	DRM_ERROR("Failed to register debugfs file for pipes !\n");
191	}	191	}
192	}	192	}
193		193
194	static void r420_clock_resume(struct radeon_device *rdev)	194	static void r420_clock_resume(struct radeon_device *rdev)
195	{	195	{
196	u32 sclk_cntl;	196	u32 sclk_cntl;
197		197
198	if (radeon_dynclks != -1 && radeon_dynclks)	198	if (radeon_dynclks != -1 && radeon_dynclks)
199	radeon_atom_set_clock_gating(rdev, 1);	199	radeon_atom_set_clock_gating(rdev, 1);
200	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);	200	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
201	sclk_cntl \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);	201	sclk_cntl \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
202	if (rdev->family == CHIP_R420)	202	if (rdev->family == CHIP_R420)
203	sclk_cntl \|= S_00000D_FORCE_PX(1) \| S_00000D_FORCE_TX(1);	203	sclk_cntl \|= S_00000D_FORCE_PX(1) \| S_00000D_FORCE_TX(1);
204	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);	204	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
205	}	205	}
206		206
207	static void r420_cp_errata_init(struct radeon_device *rdev)	207	static void r420_cp_errata_init(struct radeon_device *rdev)
208	{	208	{
209	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	209	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
210		210
211	/* RV410 and R420 can lock up if CP DMA to host memory happens	211	/* RV410 and R420 can lock up if CP DMA to host memory happens
212	* while the 2D engine is busy.	212	* while the 2D engine is busy.
213	*	213	*
214	* The proper workaround is to queue a RESYNC at the beginning	214	* The proper workaround is to queue a RESYNC at the beginning
215	* of the CP init, apparently.	215	* of the CP init, apparently.
216	*/	216	*/
217	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);	217	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
218	radeon_ring_lock(rdev, ring, 8);	218	radeon_ring_lock(rdev, ring, 8);
219	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));	219	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
220	radeon_ring_write(ring, rdev->config.r300.resync_scratch);	220	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
221	radeon_ring_write(ring, 0xDEADBEEF);	221	radeon_ring_write(ring, 0xDEADBEEF);
222	radeon_ring_unlock_commit(rdev, ring, false);	222	radeon_ring_unlock_commit(rdev, ring, false);
223	}	223	}
224		224
225	static void r420_cp_errata_fini(struct radeon_device *rdev)	225	static void r420_cp_errata_fini(struct radeon_device *rdev)
226	{	226	{
227	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];	227	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
228		228
229	/* Catch the RESYNC we dispatched all the way back,	229	/* Catch the RESYNC we dispatched all the way back,
230	* at the very beginning of the CP init.	230	* at the very beginning of the CP init.
231	*/	231	*/
232	radeon_ring_lock(rdev, ring, 8);	232	radeon_ring_lock(rdev, ring, 8);
233	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	233	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
234	radeon_ring_write(ring, R300_RB3D_DC_FINISH);	234	radeon_ring_write(ring, R300_RB3D_DC_FINISH);
235	radeon_ring_unlock_commit(rdev, ring, false);	235	radeon_ring_unlock_commit(rdev, ring, false);
236	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);	236	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
237	}	237	}
238		238
239	static int r420_startup(struct radeon_device *rdev)	239	static int r420_startup(struct radeon_device *rdev)
240	{	240	{
241	int r;	241	int r;
242		242
243	/* set common regs */	243	/* set common regs */
244	r100_set_common_regs(rdev);	244	r100_set_common_regs(rdev);
245	/* program mc */	245	/* program mc */
246	r300_mc_program(rdev);	246	r300_mc_program(rdev);
247	/* Resume clock */	247	/* Resume clock */
248	r420_clock_resume(rdev);	248	r420_clock_resume(rdev);
249	/* Initialize GART (initialize after TTM so we can allocate	249	/* Initialize GART (initialize after TTM so we can allocate
250	* memory through TTM but finalize after TTM) */	250	* memory through TTM but finalize after TTM) */
251	if (rdev->flags & RADEON_IS_PCIE) {	251	if (rdev->flags & RADEON_IS_PCIE) {
252	r = rv370_pcie_gart_enable(rdev);	252	r = rv370_pcie_gart_enable(rdev);
253	if (r)	253	if (r)
254	return r;	254	return r;
255	}	255	}
256	if (rdev->flags & RADEON_IS_PCI) {	256	if (rdev->flags & RADEON_IS_PCI) {
257	r = r100_pci_gart_enable(rdev);	257	r = r100_pci_gart_enable(rdev);
258	if (r)	258	if (r)
259	return r;	259	return r;
260	}	260	}
261	r420_pipes_init(rdev);	261	r420_pipes_init(rdev);
262		262
263	/* allocate wb buffer */	263	/* allocate wb buffer */
264	r = radeon_wb_init(rdev);	264	r = radeon_wb_init(rdev);
265	if (r)	265	if (r)
266	return r;	266	return r;
267		267
268	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);	268	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
269	if (r) {	269	if (r) {
270	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);	270	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
271	return r;	271	return r;
272	}	272	}
273		273
274	/* Enable IRQ */	274	/* Enable IRQ */
275	if (!rdev->irq.installed) {	275	if (!rdev->irq.installed) {
276	r = radeon_irq_kms_init(rdev);	276	r = radeon_irq_kms_init(rdev);
277	if (r)	277	if (r)
278	return r;	278	return r;
279	}	279	}
280		280
281	r100_irq_set(rdev);	281	r100_irq_set(rdev);
282	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);	282	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
283	/* 1M ring buffer */	283	/* 1M ring buffer */
284	r = r100_cp_init(rdev, 1024 * 1024);	284	r = r100_cp_init(rdev, 1024 * 1024);
285	if (r) {	285	if (r) {
286	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);	286	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
287	return r;	287	return r;
288	}	288	}
289	r420_cp_errata_init(rdev);	289	r420_cp_errata_init(rdev);
290		290
291	r = radeon_ib_pool_init(rdev);	291	r = radeon_ib_pool_init(rdev);
292	if (r) {	292	if (r) {
293	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);	293	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
294	return r;	294	return r;
295	}	295	}
296		296
297	return 0;	297	return 0;
298	}	298	}
299		299
300		300
301		301
302		302
-		303
-		304	void r420_fini(struct radeon_device *rdev)
-		305	{
-		306	radeon_pm_fini(rdev);
-		307	r100_cp_fini(rdev);
-		308	radeon_wb_fini(rdev);
-		309	radeon_ib_pool_fini(rdev);
-		310	radeon_gem_fini(rdev);
-		311	if (rdev->flags & RADEON_IS_PCIE)
-		312	rv370_pcie_gart_fini(rdev);
-		313	if (rdev->flags & RADEON_IS_PCI)
-		314	r100_pci_gart_fini(rdev);
-		315	radeon_agp_fini(rdev);
-		316	radeon_irq_kms_fini(rdev);
-		317	radeon_fence_driver_fini(rdev);
-		318	radeon_bo_fini(rdev);
-		319	if (rdev->is_atom_bios) {
-		320	radeon_atombios_fini(rdev);
-		321	} else {
-		322	radeon_combios_fini(rdev);
-		323	}
-		324	kfree(rdev->bios);
-		325	rdev->bios = NULL;
303		326	}
304		327
305	int r420_init(struct radeon_device *rdev)	328	int r420_init(struct radeon_device *rdev)
306	{	329	{
307	int r;	330	int r;
308		331
309	/* Initialize scratch registers */	332	/* Initialize scratch registers */
310	radeon_scratch_init(rdev);	333	radeon_scratch_init(rdev);
311	/* Initialize surface registers */	334	/* Initialize surface registers */
312	radeon_surface_init(rdev);	335	radeon_surface_init(rdev);
313	/* TODO: disable VGA need to use VGA request */	336	/* TODO: disable VGA need to use VGA request */
314	/* restore some register to sane defaults */	337	/* restore some register to sane defaults */
315	r100_restore_sanity(rdev);	338	r100_restore_sanity(rdev);
316	/* BIOS*/	339	/* BIOS*/
317	if (!radeon_get_bios(rdev)) {	340	if (!radeon_get_bios(rdev)) {
318	if (ASIC_IS_AVIVO(rdev))	341	if (ASIC_IS_AVIVO(rdev))
319	return -EINVAL;	342	return -EINVAL;
320	}	343	}
321	if (rdev->is_atom_bios) {	344	if (rdev->is_atom_bios) {
322	r = radeon_atombios_init(rdev);	345	r = radeon_atombios_init(rdev);
323	if (r) {	346	if (r) {
324	return r;	347	return r;
325	}	348	}
326	} else {	349	} else {
327	r = radeon_combios_init(rdev);	350	r = radeon_combios_init(rdev);
328	if (r) {	351	if (r) {
329	return r;	352	return r;
330	}	353	}
331	}	354	}
332	/* Reset gpu before posting otherwise ATOM will enter infinite loop */	355	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
333	if (radeon_asic_reset(rdev)) {	356	if (radeon_asic_reset(rdev)) {
334	dev_warn(rdev->dev,	357	dev_warn(rdev->dev,
335	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",	358	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
336	RREG32(R_000E40_RBBM_STATUS),	359	RREG32(R_000E40_RBBM_STATUS),
337	RREG32(R_0007C0_CP_STAT));	360	RREG32(R_0007C0_CP_STAT));
338	}	361	}
339	/* check if cards are posted or not */	362	/* check if cards are posted or not */
340	if (radeon_boot_test_post_card(rdev) == false)	363	if (radeon_boot_test_post_card(rdev) == false)
341	return -EINVAL;	364	return -EINVAL;
342		365
343	/* Initialize clocks */	366	/* Initialize clocks */
344	radeon_get_clock_info(rdev->ddev);	367	radeon_get_clock_info(rdev->ddev);
345	/* initialize AGP */	368	/* initialize AGP */
346	if (rdev->flags & RADEON_IS_AGP) {	369	if (rdev->flags & RADEON_IS_AGP) {
347	r = radeon_agp_init(rdev);	370	r = radeon_agp_init(rdev);
348	if (r) {	371	if (r) {
349	radeon_agp_disable(rdev);	372	radeon_agp_disable(rdev);
350	}	373	}
351	}	374	}
352	/* initialize memory controller */	375	/* initialize memory controller */
353	r300_mc_init(rdev);	376	r300_mc_init(rdev);
354	r420_debugfs(rdev);	377	r420_debugfs(rdev);
355	/* Fence driver */	378	/* Fence driver */
356	r = radeon_fence_driver_init(rdev);	379	r = radeon_fence_driver_init(rdev);
357	if (r) {	380	if (r) {
358	return r;	381	return r;
359	}	382	}
360	/* Memory manager */	383	/* Memory manager */
361	r = radeon_bo_init(rdev);	384	r = radeon_bo_init(rdev);
362	if (r) {	385	if (r) {
363	return r;	386	return r;
364	}	387	}
365	if (rdev->family == CHIP_R420)	388	if (rdev->family == CHIP_R420)
366	r100_enable_bm(rdev);	389	r100_enable_bm(rdev);
367		390
368	if (rdev->flags & RADEON_IS_PCIE) {	391	if (rdev->flags & RADEON_IS_PCIE) {
369	r = rv370_pcie_gart_init(rdev);	392	r = rv370_pcie_gart_init(rdev);
370	if (r)	393	if (r)
371	return r;	394	return r;
372	}	395	}
373	if (rdev->flags & RADEON_IS_PCI) {	396	if (rdev->flags & RADEON_IS_PCI) {
374	r = r100_pci_gart_init(rdev);	397	r = r100_pci_gart_init(rdev);
375	if (r)	398	if (r)
376	return r;	399	return r;
377	}	400	}
378	r420_set_reg_safe(rdev);	401	r420_set_reg_safe(rdev);
379		402
380	/* Initialize power management */	403	/* Initialize power management */
381	radeon_pm_init(rdev);	404	radeon_pm_init(rdev);
382		405
383	rdev->accel_working = true;	406	rdev->accel_working = true;
384	r = r420_startup(rdev);	407	r = r420_startup(rdev);
385	if (r) {	408	if (r) {
386	/* Somethings want wront with the accel init stop accel */	409	/* Somethings want wront with the accel init stop accel */
387	dev_err(rdev->dev, "Disabling GPU acceleration\n");	410	dev_err(rdev->dev, "Disabling GPU acceleration\n");
-		411	r100_cp_fini(rdev);
-		412	radeon_wb_fini(rdev);
-		413	radeon_ib_pool_fini(rdev);
-		414	radeon_irq_kms_fini(rdev);
388	if (rdev->flags & RADEON_IS_PCIE)	415	if (rdev->flags & RADEON_IS_PCIE)
389	rv370_pcie_gart_fini(rdev);	416	rv370_pcie_gart_fini(rdev);
390	if (rdev->flags & RADEON_IS_PCI)	417	if (rdev->flags & RADEON_IS_PCI)
391	r100_pci_gart_fini(rdev);	418	r100_pci_gart_fini(rdev);
392	rdev->accel_working = false;	419	rdev->accel_working = false;
393	}	420	}
394	return 0;	421	return 0;
395	}	422	}
396		423
397	/*	424	/*
398	* Debugfs info	425	* Debugfs info
399	*/	426	*/
400	#if defined(CONFIG_DEBUG_FS)	427	#if defined(CONFIG_DEBUG_FS)
401	static int r420_debugfs_pipes_info(struct seq_file m, void data)	428	static int r420_debugfs_pipes_info(struct seq_file m, void data)
402	{	429	{
403	struct drm_info_node node = (struct drm_info_node ) m->private;	430	struct drm_info_node node = (struct drm_info_node ) m->private;
404	struct drm_device *dev = node->minor->dev;	431	struct drm_device *dev = node->minor->dev;
405	struct radeon_device *rdev = dev->dev_private;	432	struct radeon_device *rdev = dev->dev_private;
406	uint32_t tmp;	433	uint32_t tmp;
407		434
408	tmp = RREG32(R400_GB_PIPE_SELECT);	435	tmp = RREG32(R400_GB_PIPE_SELECT);
409	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);	436	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
410	tmp = RREG32(R300_GB_TILE_CONFIG);	437	tmp = RREG32(R300_GB_TILE_CONFIG);
411	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);	438	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
412	tmp = RREG32(R300_DST_PIPE_CONFIG);	439	tmp = RREG32(R300_DST_PIPE_CONFIG);
413	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);	440	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
414	return 0;	441	return 0;
415	}	442	}
416		443
417	static struct drm_info_list r420_pipes_info_list[] = {	444	static struct drm_info_list r420_pipes_info_list[] = {
418	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},	445	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
419	};	446	};
420	#endif	447	#endif
421		448
422	int r420_debugfs_pipes_info_init(struct radeon_device *rdev)	449	int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
423	{	450	{
424	#if defined(CONFIG_DEBUG_FS)	451	#if defined(CONFIG_DEBUG_FS)
425	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);	452	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
426	#else	453	#else
427	return 0;	454	return 0;
428	#endif	455	#endif
429	}	456	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r420.c – Rev 5078 → 6104