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Rev 3120 Rev 3764
Line 34... Line 34...
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#include "atom.h"
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#include "atom.h"
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#include "r100d.h"
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#include "r100d.h"
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#include "r420d.h"
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#include "r420d.h"
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#include "r420_reg_safe.h"
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#include "r420_reg_safe.h"
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void r420_pm_init_profile(struct radeon_device *rdev)
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{
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	/* default */
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	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
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	/* low sh */
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	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
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	/* mid sh */
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	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
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	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
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	/* high sh */
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	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
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	/* low mh */
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	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
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	/* mid mh */
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	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
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	/* high mh */
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	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
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	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
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	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
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}
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static void r420_set_reg_safe(struct radeon_device *rdev)
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static void r420_set_reg_safe(struct radeon_device *rdev)
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{
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{
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	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
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	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
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	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
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	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
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		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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		return r;
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		return r;
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	}
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	}
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	/* Enable IRQ */
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	if (!rdev->irq.installed) {
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		r = radeon_irq_kms_init(rdev);
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		if (r)
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			return r;
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	}
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	/* Enable IRQ */
 273 
 
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	r100_irq_set(rdev);
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	r100_irq_set(rdev);
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	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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	/* 1M ring buffer */
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	/* 1M ring buffer */
232 
	r = r100_cp_init(rdev, 1024 * 1024);
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	r = r100_cp_init(rdev, 1024 * 1024);
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	/* Fence driver */
 348 
	/* Fence driver */
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	r = radeon_fence_driver_init(rdev);
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	r = radeon_fence_driver_init(rdev);
305 
	if (r) {
 350 
	if (r) {
306 
		return r;
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		return r;
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	}
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	}
308 
	r = radeon_irq_kms_init(rdev);
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309 
	if (r) {
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		return r;
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	}
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	/* Memory manager */
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	/* Memory manager */
313 
	r = radeon_bo_init(rdev);
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	r = radeon_bo_init(rdev);
314 
	if (r) {
 355 
	if (r) {
315 
		return r;
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		return r;
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	}
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	}