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Rev 3120 Rev 3764
1 
/*
 1 
/*
2 
 * Copyright 2008 Advanced Micro Devices, Inc.
 2 
 * Copyright 2008 Advanced Micro Devices, Inc.
3 
 * Copyright 2008 Red Hat Inc.
 3 
 * Copyright 2008 Red Hat Inc.
4 
 * Copyright 2009 Jerome Glisse.
 4 
 * Copyright 2009 Jerome Glisse.
5 
 *
 5 
 *
6 
 * Permission is hereby granted, free of charge, to any person obtaining a
 6 
 * Permission is hereby granted, free of charge, to any person obtaining a
7 
 * copy of this software and associated documentation files (the "Software"),
 7 
 * copy of this software and associated documentation files (the "Software"),
8 
 * to deal in the Software without restriction, including without limitation
 8 
 * to deal in the Software without restriction, including without limitation
9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 9 
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 
 * and/or sell copies of the Software, and to permit persons to whom the
 10 
 * and/or sell copies of the Software, and to permit persons to whom the
11 
 * Software is furnished to do so, subject to the following conditions:
 11 
 * Software is furnished to do so, subject to the following conditions:
12 
 *
 12 
 *
13 
 * The above copyright notice and this permission notice shall be included in
 13 
 * The above copyright notice and this permission notice shall be included in
14 
 * all copies or substantial portions of the Software.
 14 
 * all copies or substantial portions of the Software.
15 
 *
 15 
 *
16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 
 * OTHER DEALINGS IN THE SOFTWARE.
 22 
 * OTHER DEALINGS IN THE SOFTWARE.
23 
 *
 23 
 *
24 
 * Authors: Dave Airlie
 24 
 * Authors: Dave Airlie
25 
 *          Alex Deucher
 25 
 *          Alex Deucher
26 
 *          Jerome Glisse
 26 
 *          Jerome Glisse
27 
 */
 27 
 */
28 
#include
28 
#include
29 
#include
29 
#include
30 
#include
30 
#include
31 
#include
31 
#include
32 
#include
32 
#include
33 
#include "radeon_reg.h"
 33 
#include "radeon_reg.h"
34 
#include "radeon.h"
 34 
#include "radeon.h"
35 
#include "radeon_asic.h"
 35 
#include "radeon_asic.h"
36 
#include
36 
#include
37 
 
 37 
 
38 
#include "r300d.h"
 38 
#include "r300d.h"
39 
#include "rv350d.h"
 39 
#include "rv350d.h"
40 
#include "r300_reg_safe.h"
 40 
#include "r300_reg_safe.h"
41 
 
 41 
 
42 
/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
 42 
/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
43 
 *
 43 
 *
44 
 * GPU Errata:
 44 
 * GPU Errata:
45 
 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
 45 
 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 
 *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
 46 
 *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 
 *   However, scheduling such write to the ring seems harmless, i suspect
 47 
 *   However, scheduling such write to the ring seems harmless, i suspect
48 
 *   the CP read collide with the flush somehow, or maybe the MC, hard to
 48 
 *   the CP read collide with the flush somehow, or maybe the MC, hard to
49 
 *   tell. (Jerome Glisse)
 49 
 *   tell. (Jerome Glisse)
50 
 */
 50 
 */
51 
 
 51 
 
52 
/*
 52 
/*
53 
 * rv370,rv380 PCIE GART
 53 
 * rv370,rv380 PCIE GART
54 
 */
 54 
 */
55 
static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
 55 
static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56 
 
 56 
 
57 
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
 57 
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
58 
{
 58 
{
59 
	uint32_t tmp;
 59 
	uint32_t tmp;
60 
	int i;
 60 
	int i;
61 
 
 61 
 
62 
	/* Workaround HW bug do flush 2 times */
 62 
	/* Workaround HW bug do flush 2 times */
63 
	for (i = 0; i < 2; i++) {
 63 
	for (i = 0; i < 2; i++) {
64 
		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 64 
		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65 
		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
 65 
		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
66 
		(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 66 
		(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
67 
		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 67 
		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
68 
	}
 68 
	}
69 
		mb();
 69 
		mb();
70 
}
 70 
}
71 
 
 71 
 
72 
#define R300_PTE_WRITEABLE (1 << 2)
 72 
#define R300_PTE_WRITEABLE (1 << 2)
73 
#define R300_PTE_READABLE  (1 << 3)
 73 
#define R300_PTE_READABLE  (1 << 3)
74 
 
 74 
 
75 
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 75 
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
76 
{
 76 
{
77 
	void __iomem *ptr = rdev->gart.ptr;
 77 
	void __iomem *ptr = rdev->gart.ptr;
78 
 
 78 
 
79 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
 79 
	if (i < 0 || i > rdev->gart.num_gpu_pages) {
80 
		return -EINVAL;
 80 
		return -EINVAL;
81 
	}
 81 
	}
82 
	addr = (lower_32_bits(addr) >> 8) |
 82 
	addr = (lower_32_bits(addr) >> 8) |
83 
	       ((upper_32_bits(addr) & 0xff) << 24) |
 83 
	       ((upper_32_bits(addr) & 0xff) << 24) |
84 
	       R300_PTE_WRITEABLE | R300_PTE_READABLE;
 84 
	       R300_PTE_WRITEABLE | R300_PTE_READABLE;
85 
	/* on x86 we want this to be CPU endian, on powerpc
 85 
	/* on x86 we want this to be CPU endian, on powerpc
86 
	 * on powerpc without HW swappers, it'll get swapped on way
 86 
	 * on powerpc without HW swappers, it'll get swapped on way
87 
	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
 87 
	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
88 
	writel(addr, ((void __iomem *)ptr) + (i * 4));
 88 
	writel(addr, ((void __iomem *)ptr) + (i * 4));
89 
	return 0;
 89 
	return 0;
90 
}
 90 
}
91 
 
 91 
 
92 
int rv370_pcie_gart_init(struct radeon_device *rdev)
 92 
int rv370_pcie_gart_init(struct radeon_device *rdev)
93 
{
 93 
{
94 
	int r;
 94 
	int r;
95 
 
 95 
 
96 
	if (rdev->gart.robj) {
 96 
	if (rdev->gart.robj) {
97 
		WARN(1, "RV370 PCIE GART already initialized\n");
 97 
		WARN(1, "RV370 PCIE GART already initialized\n");
98 
		return 0;
 98 
		return 0;
99 
	}
 99 
	}
100 
	/* Initialize common gart structure */
 100 
	/* Initialize common gart structure */
101 
	r = radeon_gart_init(rdev);
 101 
	r = radeon_gart_init(rdev);
102 
	if (r)
 102 
	if (r)
103 
		return r;
 103 
		return r;
104 
	r = rv370_debugfs_pcie_gart_info_init(rdev);
 104 
	r = rv370_debugfs_pcie_gart_info_init(rdev);
105 
	if (r)
 105 
	if (r)
106 
		DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 106 
		DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
107 
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 107 
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108 
	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 108 
	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
109 
	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 109 
	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
110 
	return radeon_gart_table_vram_alloc(rdev);
 110 
	return radeon_gart_table_vram_alloc(rdev);
111 
}
 111 
}
112 
 
 112 
 
113 
int rv370_pcie_gart_enable(struct radeon_device *rdev)
 113 
int rv370_pcie_gart_enable(struct radeon_device *rdev)
114 
{
 114 
{
115 
	uint32_t table_addr;
 115 
	uint32_t table_addr;
116 
	uint32_t tmp;
 116 
	uint32_t tmp;
117 
	int r;
 117 
	int r;
118 
 
 118 
 
119 
	if (rdev->gart.robj == NULL) {
 119 
	if (rdev->gart.robj == NULL) {
120 
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 120 
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
121 
		return -EINVAL;
 121 
		return -EINVAL;
122 
	}
 122 
	}
123 
	r = radeon_gart_table_vram_pin(rdev);
 123 
	r = radeon_gart_table_vram_pin(rdev);
124 
	if (r)
 124 
	if (r)
125 
		return r;
 125 
		return r;
126 
	radeon_gart_restore(rdev);
 126 
	radeon_gart_restore(rdev);
127 
	/* discard memory request outside of configured range */
 127 
	/* discard memory request outside of configured range */
128 
	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 128 
	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
129 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 129 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
130 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 130 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
131 
	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 131 
	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
132 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 132 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
133 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 133 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
134 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 134 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
135 
	table_addr = rdev->gart.table_addr;
 135 
	table_addr = rdev->gart.table_addr;
136 
	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 136 
	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
137 
	/* FIXME: setup default page */
 137 
	/* FIXME: setup default page */
138 
	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 138 
	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
139 
	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 139 
	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
140 
	/* Clear error */
 140 
	/* Clear error */
141 
	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 141 
	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
142 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 142 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143 
	tmp |= RADEON_PCIE_TX_GART_EN;
 143 
	tmp |= RADEON_PCIE_TX_GART_EN;
144 
	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 144 
	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
145 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 145 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
146 
	rv370_pcie_gart_tlb_flush(rdev);
 146 
	rv370_pcie_gart_tlb_flush(rdev);
147 
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 147 
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
148 
		 (unsigned)(rdev->mc.gtt_size >> 20),
 148 
		 (unsigned)(rdev->mc.gtt_size >> 20),
149 
		 (unsigned long long)table_addr);
 149 
		 (unsigned long long)table_addr);
150 
	rdev->gart.ready = true;
 150 
	rdev->gart.ready = true;
151 
	return 0;
 151 
	return 0;
152 
}
 152 
}
153 
 
 153 
 
154 
void rv370_pcie_gart_disable(struct radeon_device *rdev)
 154 
void rv370_pcie_gart_disable(struct radeon_device *rdev)
155 
{
 155 
{
156 
	u32 tmp;
 156 
	u32 tmp;
157 
 
 157 
 
158 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 158 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
159 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 159 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
160 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 160 
	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
161 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 161 
	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
162 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 162 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
163 
	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 163 
	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
164 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 164 
	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
165 
	radeon_gart_table_vram_unpin(rdev);
 165 
	radeon_gart_table_vram_unpin(rdev);
166 
}
 166 
}
167 
 
 167 
 
168 
void rv370_pcie_gart_fini(struct radeon_device *rdev)
 168 
void rv370_pcie_gart_fini(struct radeon_device *rdev)
169 
{
 169 
{
170 
	radeon_gart_fini(rdev);
 170 
	radeon_gart_fini(rdev);
171 
			rv370_pcie_gart_disable(rdev);
 171 
			rv370_pcie_gart_disable(rdev);
172 
	radeon_gart_table_vram_free(rdev);
 172 
	radeon_gart_table_vram_free(rdev);
173 
}
 173 
}
174 
 
 174 
 
175 
void r300_fence_ring_emit(struct radeon_device *rdev,
 175 
void r300_fence_ring_emit(struct radeon_device *rdev,
176 
			  struct radeon_fence *fence)
 176 
			  struct radeon_fence *fence)
177 
{
 177 
{
178 
	struct radeon_ring *ring = &rdev->ring[fence->ring];
 178 
	struct radeon_ring *ring = &rdev->ring[fence->ring];
179 
 
 179 
 
180 
	/* Who ever call radeon_fence_emit should call ring_lock and ask
 180 
	/* Who ever call radeon_fence_emit should call ring_lock and ask
181 
	 * for enough space (today caller are ib schedule and buffer move) */
 181 
	 * for enough space (today caller are ib schedule and buffer move) */
182 
	/* Write SC register so SC & US assert idle */
 182 
	/* Write SC register so SC & US assert idle */
183 
	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
 183 
	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
184 
	radeon_ring_write(ring, 0);
 184 
	radeon_ring_write(ring, 0);
185 
	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
 185 
	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
186 
	radeon_ring_write(ring, 0);
 186 
	radeon_ring_write(ring, 0);
187 
	/* Flush 3D cache */
 187 
	/* Flush 3D cache */
188 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 188 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
189 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
 189 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
190 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 190 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
191 
	radeon_ring_write(ring, R300_ZC_FLUSH);
 191 
	radeon_ring_write(ring, R300_ZC_FLUSH);
192 
	/* Wait until IDLE & CLEAN */
 192 
	/* Wait until IDLE & CLEAN */
193 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 193 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
194 
	radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
 194 
	radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
195 
				 RADEON_WAIT_2D_IDLECLEAN |
 195 
				 RADEON_WAIT_2D_IDLECLEAN |
196 
				 RADEON_WAIT_DMA_GUI_IDLE));
 196 
				 RADEON_WAIT_DMA_GUI_IDLE));
197 
	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 197 
	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198 
	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
 198 
	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
199 
				RADEON_HDP_READ_BUFFER_INVALIDATE);
 199 
				RADEON_HDP_READ_BUFFER_INVALIDATE);
200 
	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 200 
	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
201 
	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
 201 
	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
202 
	/* Emit fence sequence & fire IRQ */
 202 
	/* Emit fence sequence & fire IRQ */
203 
	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 203 
	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
204 
	radeon_ring_write(ring, fence->seq);
 204 
	radeon_ring_write(ring, fence->seq);
205 
	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 205 
	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
206 
	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 206 
	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
207 
}
 207 
}
208 
 
 208 
 
209 
void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 209 
void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
210 
{
 210 
{
211 
	unsigned gb_tile_config;
 211 
	unsigned gb_tile_config;
212 
	int r;
 212 
	int r;
213 
 
 213 
 
214 
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
 214 
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
215 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 215 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
216 
	switch(rdev->num_gb_pipes) {
 216 
	switch(rdev->num_gb_pipes) {
217 
	case 2:
 217 
	case 2:
218 
		gb_tile_config |= R300_PIPE_COUNT_R300;
 218 
		gb_tile_config |= R300_PIPE_COUNT_R300;
219 
		break;
 219 
		break;
220 
	case 3:
 220 
	case 3:
221 
		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 221 
		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
222 
		break;
 222 
		break;
223 
	case 4:
 223 
	case 4:
224 
		gb_tile_config |= R300_PIPE_COUNT_R420;
 224 
		gb_tile_config |= R300_PIPE_COUNT_R420;
225 
		break;
 225 
		break;
226 
	case 1:
 226 
	case 1:
227 
	default:
 227 
	default:
228 
		gb_tile_config |= R300_PIPE_COUNT_RV350;
 228 
		gb_tile_config |= R300_PIPE_COUNT_RV350;
229 
		break;
 229 
		break;
230 
	}
 230 
	}
231 
 
 231 
 
232 
	r = radeon_ring_lock(rdev, ring, 64);
 232 
	r = radeon_ring_lock(rdev, ring, 64);
233 
	if (r) {
 233 
	if (r) {
234 
		return;
 234 
		return;
235 
	}
 235 
	}
236 
	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 236 
	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
237 
	radeon_ring_write(ring,
 237 
	radeon_ring_write(ring,
238 
			  RADEON_ISYNC_ANY2D_IDLE3D |
 238 
			  RADEON_ISYNC_ANY2D_IDLE3D |
239 
			  RADEON_ISYNC_ANY3D_IDLE2D |
 239 
			  RADEON_ISYNC_ANY3D_IDLE2D |
240 
			  RADEON_ISYNC_WAIT_IDLEGUI |
 240 
			  RADEON_ISYNC_WAIT_IDLEGUI |
241 
			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 241 
			  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
242 
	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
 242 
	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
243 
	radeon_ring_write(ring, gb_tile_config);
 243 
	radeon_ring_write(ring, gb_tile_config);
244 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 244 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
245 
	radeon_ring_write(ring,
 245 
	radeon_ring_write(ring,
246 
			  RADEON_WAIT_2D_IDLECLEAN |
 246 
			  RADEON_WAIT_2D_IDLECLEAN |
247 
			  RADEON_WAIT_3D_IDLECLEAN);
 247 
			  RADEON_WAIT_3D_IDLECLEAN);
248 
	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
 248 
	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
249 
	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
 249 
	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
250 
	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
 250 
	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
251 
	radeon_ring_write(ring, 0);
 251 
	radeon_ring_write(ring, 0);
252 
	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
 252 
	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
253 
	radeon_ring_write(ring, 0);
 253 
	radeon_ring_write(ring, 0);
254 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 254 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
255 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 255 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
256 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 256 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
257 
	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 257 
	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
258 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 258 
	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
259 
	radeon_ring_write(ring,
 259 
	radeon_ring_write(ring,
260 
			  RADEON_WAIT_2D_IDLECLEAN |
 260 
			  RADEON_WAIT_2D_IDLECLEAN |
261 
			  RADEON_WAIT_3D_IDLECLEAN);
 261 
			  RADEON_WAIT_3D_IDLECLEAN);
262 
	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
 262 
	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
263 
	radeon_ring_write(ring, 0);
 263 
	radeon_ring_write(ring, 0);
264 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 264 
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
265 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 265 
	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
266 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 266 
	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
267 
	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 267 
	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
268 
	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
 268 
	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
269 
	radeon_ring_write(ring,
 269 
	radeon_ring_write(ring,
270 
			  ((6 << R300_MS_X0_SHIFT) |
 270 
			  ((6 << R300_MS_X0_SHIFT) |
271 
			   (6 << R300_MS_Y0_SHIFT) |
 271 
			   (6 << R300_MS_Y0_SHIFT) |
272 
			   (6 << R300_MS_X1_SHIFT) |
 272 
			   (6 << R300_MS_X1_SHIFT) |
273 
			   (6 << R300_MS_Y1_SHIFT) |
 273 
			   (6 << R300_MS_Y1_SHIFT) |
274 
			   (6 << R300_MS_X2_SHIFT) |
 274 
			   (6 << R300_MS_X2_SHIFT) |
275 
			   (6 << R300_MS_Y2_SHIFT) |
 275 
			   (6 << R300_MS_Y2_SHIFT) |
276 
			   (6 << R300_MSBD0_Y_SHIFT) |
 276 
			   (6 << R300_MSBD0_Y_SHIFT) |
277 
			   (6 << R300_MSBD0_X_SHIFT)));
 277 
			   (6 << R300_MSBD0_X_SHIFT)));
278 
	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
 278 
	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
279 
	radeon_ring_write(ring,
 279 
	radeon_ring_write(ring,
280 
			  ((6 << R300_MS_X3_SHIFT) |
 280 
			  ((6 << R300_MS_X3_SHIFT) |
281 
			   (6 << R300_MS_Y3_SHIFT) |
 281 
			   (6 << R300_MS_Y3_SHIFT) |
282 
			   (6 << R300_MS_X4_SHIFT) |
 282 
			   (6 << R300_MS_X4_SHIFT) |
283 
			   (6 << R300_MS_Y4_SHIFT) |
 283 
			   (6 << R300_MS_Y4_SHIFT) |
284 
			   (6 << R300_MS_X5_SHIFT) |
 284 
			   (6 << R300_MS_X5_SHIFT) |
285 
			   (6 << R300_MS_Y5_SHIFT) |
 285 
			   (6 << R300_MS_Y5_SHIFT) |
286 
			   (6 << R300_MSBD1_SHIFT)));
 286 
			   (6 << R300_MSBD1_SHIFT)));
287 
	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
 287 
	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
288 
	radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 288 
	radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
289 
	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
 289 
	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
290 
	radeon_ring_write(ring,
 290 
	radeon_ring_write(ring,
291 
			  R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 291 
			  R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
292 
	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 292 
	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
293 
	radeon_ring_write(ring,
 293 
	radeon_ring_write(ring,
294 
			  R300_GEOMETRY_ROUND_NEAREST |
 294 
			  R300_GEOMETRY_ROUND_NEAREST |
295 
			  R300_COLOR_ROUND_NEAREST);
 295 
			  R300_COLOR_ROUND_NEAREST);
296 
	radeon_ring_unlock_commit(rdev, ring);
 296 
	radeon_ring_unlock_commit(rdev, ring);
297 
}
 297 
}
298 
 
 298 
 
299 
static void r300_errata(struct radeon_device *rdev)
 299 
static void r300_errata(struct radeon_device *rdev)
300 
{
 300 
{
301 
	rdev->pll_errata = 0;
 301 
	rdev->pll_errata = 0;
302 
 
 302 
 
303 
	if (rdev->family == CHIP_R300 &&
 303 
	if (rdev->family == CHIP_R300 &&
304 
	    (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 304 
	    (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
305 
		rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 305 
		rdev->pll_errata |= CHIP_ERRATA_R300_CG;
306 
	}
 306 
	}
307 
}
 307 
}
308 
 
 308 
 
309 
int r300_mc_wait_for_idle(struct radeon_device *rdev)
 309 
int r300_mc_wait_for_idle(struct radeon_device *rdev)
310 
{
 310 
{
311 
	unsigned i;
 311 
	unsigned i;
312 
	uint32_t tmp;
 312 
	uint32_t tmp;
313 
 
 313 
 
314 
	for (i = 0; i < rdev->usec_timeout; i++) {
 314 
	for (i = 0; i < rdev->usec_timeout; i++) {
315 
		/* read MC_STATUS */
 315 
		/* read MC_STATUS */
316 
		tmp = RREG32(RADEON_MC_STATUS);
 316 
		tmp = RREG32(RADEON_MC_STATUS);
317 
		if (tmp & R300_MC_IDLE) {
 317 
		if (tmp & R300_MC_IDLE) {
318 
			return 0;
 318 
			return 0;
319 
		}
 319 
		}
320 
		DRM_UDELAY(1);
 320 
		DRM_UDELAY(1);
321 
	}
 321 
	}
322 
	return -1;
 322 
	return -1;
323 
}
 323 
}
324 
 
 324 
 
325 
static void r300_gpu_init(struct radeon_device *rdev)
 325 
static void r300_gpu_init(struct radeon_device *rdev)
326 
{
 326 
{
327 
	uint32_t gb_tile_config, tmp;
 327 
	uint32_t gb_tile_config, tmp;
328 
 
 328 
 
329 
	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 329 
	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
330 
	    (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 330 
	    (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
331 
		/* r300,r350 */
 331 
		/* r300,r350 */
332 
		rdev->num_gb_pipes = 2;
 332 
		rdev->num_gb_pipes = 2;
333 
	} else {
 333 
	} else {
334 
		/* rv350,rv370,rv380,r300 AD, r350 AH */
 334 
		/* rv350,rv370,rv380,r300 AD, r350 AH */
335 
		rdev->num_gb_pipes = 1;
 335 
		rdev->num_gb_pipes = 1;
336 
	}
 336 
	}
337 
	rdev->num_z_pipes = 1;
 337 
	rdev->num_z_pipes = 1;
338 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 338 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
339 
	switch (rdev->num_gb_pipes) {
 339 
	switch (rdev->num_gb_pipes) {
340 
	case 2:
 340 
	case 2:
341 
		gb_tile_config |= R300_PIPE_COUNT_R300;
 341 
		gb_tile_config |= R300_PIPE_COUNT_R300;
342 
		break;
 342 
		break;
343 
	case 3:
 343 
	case 3:
344 
		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 344 
		gb_tile_config |= R300_PIPE_COUNT_R420_3P;
345 
		break;
 345 
		break;
346 
	case 4:
 346 
	case 4:
347 
		gb_tile_config |= R300_PIPE_COUNT_R420;
 347 
		gb_tile_config |= R300_PIPE_COUNT_R420;
348 
		break;
 348 
		break;
349 
	default:
 349 
	default:
350 
	case 1:
 350 
	case 1:
351 
		gb_tile_config |= R300_PIPE_COUNT_RV350;
 351 
		gb_tile_config |= R300_PIPE_COUNT_RV350;
352 
		break;
 352 
		break;
353 
	}
 353 
	}
354 
	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 354 
	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
355 
 
 355 
 
356 
	if (r100_gui_wait_for_idle(rdev)) {
 356 
	if (r100_gui_wait_for_idle(rdev)) {
357 
		printk(KERN_WARNING "Failed to wait GUI idle while "
 357 
		printk(KERN_WARNING "Failed to wait GUI idle while "
358 
		       "programming pipes. Bad things might happen.\n");
 358 
		       "programming pipes. Bad things might happen.\n");
359 
	}
 359 
	}
360 
 
 360 
 
361 
	tmp = RREG32(R300_DST_PIPE_CONFIG);
 361 
	tmp = RREG32(R300_DST_PIPE_CONFIG);
362 
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 362 
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
363 
 
 363 
 
364 
	WREG32(R300_RB2D_DSTCACHE_MODE,
 364 
	WREG32(R300_RB2D_DSTCACHE_MODE,
365 
	       R300_DC_AUTOFLUSH_ENABLE |
 365 
	       R300_DC_AUTOFLUSH_ENABLE |
366 
	       R300_DC_DC_DISABLE_IGNORE_PE);
 366 
	       R300_DC_DC_DISABLE_IGNORE_PE);
367 
 
 367 
 
368 
	if (r100_gui_wait_for_idle(rdev)) {
 368 
	if (r100_gui_wait_for_idle(rdev)) {
369 
		printk(KERN_WARNING "Failed to wait GUI idle while "
 369 
		printk(KERN_WARNING "Failed to wait GUI idle while "
370 
		       "programming pipes. Bad things might happen.\n");
 370 
		       "programming pipes. Bad things might happen.\n");
371 
	}
 371 
	}
372 
	if (r300_mc_wait_for_idle(rdev)) {
 372 
	if (r300_mc_wait_for_idle(rdev)) {
373 
		printk(KERN_WARNING "Failed to wait MC idle while "
 373 
		printk(KERN_WARNING "Failed to wait MC idle while "
374 
		       "programming pipes. Bad things might happen.\n");
 374 
		       "programming pipes. Bad things might happen.\n");
375 
	}
 375 
	}
376 
	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 376 
	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
377 
		 rdev->num_gb_pipes, rdev->num_z_pipes);
 377 
		 rdev->num_gb_pipes, rdev->num_z_pipes);
378 
}
 378 
}
379 
 
 379 
 
380 
int r300_asic_reset(struct radeon_device *rdev)
 380 
int r300_asic_reset(struct radeon_device *rdev)
381 
{
 381 
{
382 
	struct r100_mc_save save;
 382 
	struct r100_mc_save save;
383 
	u32 status, tmp;
 383 
	u32 status, tmp;
384 
	int ret = 0;
 384 
	int ret = 0;
385 
 
 385 
 
386 
	status = RREG32(R_000E40_RBBM_STATUS);
 386 
	status = RREG32(R_000E40_RBBM_STATUS);
387 
	if (!G_000E40_GUI_ACTIVE(status)) {
 387 
	if (!G_000E40_GUI_ACTIVE(status)) {
388 
		return 0;
 388 
		return 0;
389 
	}
 389 
	}
390 
	r100_mc_stop(rdev, &save);
 390 
	r100_mc_stop(rdev, &save);
391 
	status = RREG32(R_000E40_RBBM_STATUS);
 391 
	status = RREG32(R_000E40_RBBM_STATUS);
392 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 392 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
393 
	/* stop CP */
 393 
	/* stop CP */
394 
	WREG32(RADEON_CP_CSQ_CNTL, 0);
 394 
	WREG32(RADEON_CP_CSQ_CNTL, 0);
395 
	tmp = RREG32(RADEON_CP_RB_CNTL);
 395 
	tmp = RREG32(RADEON_CP_RB_CNTL);
396 
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 396 
	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
397 
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
 397 
	WREG32(RADEON_CP_RB_RPTR_WR, 0);
398 
	WREG32(RADEON_CP_RB_WPTR, 0);
 398 
	WREG32(RADEON_CP_RB_WPTR, 0);
399 
	WREG32(RADEON_CP_RB_CNTL, tmp);
 399 
	WREG32(RADEON_CP_RB_CNTL, tmp);
400 
	/* save PCI state */
 400 
	/* save PCI state */
401 
//   pci_save_state(rdev->pdev);
 401 
//   pci_save_state(rdev->pdev);
402 
	/* disable bus mastering */
 402 
	/* disable bus mastering */
403 
	r100_bm_disable(rdev);
 403 
	r100_bm_disable(rdev);
404 
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 404 
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
405 
					S_0000F0_SOFT_RESET_GA(1));
 405 
					S_0000F0_SOFT_RESET_GA(1));
406 
	RREG32(R_0000F0_RBBM_SOFT_RESET);
 406 
	RREG32(R_0000F0_RBBM_SOFT_RESET);
407 
	mdelay(500);
 407 
	mdelay(500);
408 
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 408 
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
409 
	mdelay(1);
 409 
	mdelay(1);
410 
	status = RREG32(R_000E40_RBBM_STATUS);
 410 
	status = RREG32(R_000E40_RBBM_STATUS);
411 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 411 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
412 
	/* resetting the CP seems to be problematic sometimes it end up
 412 
	/* resetting the CP seems to be problematic sometimes it end up
413 
	 * hard locking the computer, but it's necessary for successful
 413 
	 * hard locking the computer, but it's necessary for successful
414 
	 * reset more test & playing is needed on R3XX/R4XX to find a
 414 
	 * reset more test & playing is needed on R3XX/R4XX to find a
415 
	 * reliable (if any solution)
 415 
	 * reliable (if any solution)
416 
	 */
 416 
	 */
417 
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 417 
	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
418 
	RREG32(R_0000F0_RBBM_SOFT_RESET);
 418 
	RREG32(R_0000F0_RBBM_SOFT_RESET);
419 
	mdelay(500);
 419 
	mdelay(500);
420 
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 420 
	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
421 
	mdelay(1);
 421 
	mdelay(1);
422 
	status = RREG32(R_000E40_RBBM_STATUS);
 422 
	status = RREG32(R_000E40_RBBM_STATUS);
423 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 423 
	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
424 
	/* restore PCI & busmastering */
 424 
	/* restore PCI & busmastering */
425 
//   pci_restore_state(rdev->pdev);
 425 
//   pci_restore_state(rdev->pdev);
426 
	r100_enable_bm(rdev);
 426 
	r100_enable_bm(rdev);
427 
	/* Check if GPU is idle */
 427 
	/* Check if GPU is idle */
428 
	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 428 
	if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
429 
		dev_err(rdev->dev, "failed to reset GPU\n");
 429 
		dev_err(rdev->dev, "failed to reset GPU\n");
430 
		ret = -1;
 430 
		ret = -1;
431 
	} else
 431 
	} else
432 
		dev_info(rdev->dev, "GPU reset succeed\n");
 432 
		dev_info(rdev->dev, "GPU reset succeed\n");
433 
	r100_mc_resume(rdev, &save);
 433 
	r100_mc_resume(rdev, &save);
434 
	return ret;
 434 
	return ret;
435 
}
 435 
}
436 
 
 436 
 
437 
/*
 437 
/*
438 
 * r300,r350,rv350,rv380 VRAM info
 438 
 * r300,r350,rv350,rv380 VRAM info
439 
 */
 439 
 */
440 
void r300_mc_init(struct radeon_device *rdev)
 440 
void r300_mc_init(struct radeon_device *rdev)
441 
{
 441 
{
442 
	u64 base;
 442 
	u64 base;
443 
	u32 tmp;
 443 
	u32 tmp;
444 
 
 444 
 
445 
	/* DDR for all card after R300 & IGP */
 445 
	/* DDR for all card after R300 & IGP */
446 
	rdev->mc.vram_is_ddr = true;
 446 
	rdev->mc.vram_is_ddr = true;
447 
	tmp = RREG32(RADEON_MEM_CNTL);
 447 
	tmp = RREG32(RADEON_MEM_CNTL);
448 
	tmp &= R300_MEM_NUM_CHANNELS_MASK;
 448 
	tmp &= R300_MEM_NUM_CHANNELS_MASK;
449 
	switch (tmp) {
 449 
	switch (tmp) {
450 
	case 0: rdev->mc.vram_width = 64; break;
 450 
	case 0: rdev->mc.vram_width = 64; break;
451 
	case 1: rdev->mc.vram_width = 128; break;
 451 
	case 1: rdev->mc.vram_width = 128; break;
452 
	case 2: rdev->mc.vram_width = 256; break;
 452 
	case 2: rdev->mc.vram_width = 256; break;
453 
	default:  rdev->mc.vram_width = 128; break;
 453 
	default:  rdev->mc.vram_width = 128; break;
454 
	}
 454 
	}
455 
	r100_vram_init_sizes(rdev);
 455 
	r100_vram_init_sizes(rdev);
456 
	base = rdev->mc.aper_base;
 456 
	base = rdev->mc.aper_base;
457 
	if (rdev->flags & RADEON_IS_IGP)
 457 
	if (rdev->flags & RADEON_IS_IGP)
458 
		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 458 
		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
459 
	radeon_vram_location(rdev, &rdev->mc, base);
 459 
	radeon_vram_location(rdev, &rdev->mc, base);
460 
	rdev->mc.gtt_base_align = 0;
 460 
	rdev->mc.gtt_base_align = 0;
461 
	if (!(rdev->flags & RADEON_IS_AGP))
 461 
	if (!(rdev->flags & RADEON_IS_AGP))
462 
		radeon_gtt_location(rdev, &rdev->mc);
 462 
		radeon_gtt_location(rdev, &rdev->mc);
463 
	radeon_update_bandwidth_info(rdev);
 463 
	radeon_update_bandwidth_info(rdev);
464 
}
 464 
}
465 
 
 465 
 
466 
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 466 
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
467 
{
 467 
{
468 
	uint32_t link_width_cntl, mask;
 468 
	uint32_t link_width_cntl, mask;
469 
 
 469 
 
470 
	if (rdev->flags & RADEON_IS_IGP)
 470 
	if (rdev->flags & RADEON_IS_IGP)
471 
		return;
 471 
		return;
472 
 
 472 
 
473 
	if (!(rdev->flags & RADEON_IS_PCIE))
 473 
	if (!(rdev->flags & RADEON_IS_PCIE))
474 
		return;
 474 
		return;
475 
 
 475 
 
476 
	/* FIXME wait for idle */
 476 
	/* FIXME wait for idle */
477 
 
 477 
 
478 
	switch (lanes) {
 478 
	switch (lanes) {
479 
	case 0:
 479 
	case 0:
480 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 480 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
481 
		break;
 481 
		break;
482 
	case 1:
 482 
	case 1:
483 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 483 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
484 
		break;
 484 
		break;
485 
	case 2:
 485 
	case 2:
486 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 486 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
487 
		break;
 487 
		break;
488 
	case 4:
 488 
	case 4:
489 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 489 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
490 
		break;
 490 
		break;
491 
	case 8:
 491 
	case 8:
492 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 492 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
493 
		break;
 493 
		break;
494 
	case 12:
 494 
	case 12:
495 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 495 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
496 
		break;
 496 
		break;
497 
	case 16:
 497 
	case 16:
498 
	default:
 498 
	default:
499 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 499 
		mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
500 
		break;
 500 
		break;
501 
	}
 501 
	}
502 
 
 502 
 
503 
	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 503 
	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
504 
 
 504 
 
505 
	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 505 
	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
506 
	    (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 506 
	    (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
507 
		return;
 507 
		return;
508 
 
 508 
 
509 
	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 509 
	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
510 
			     RADEON_PCIE_LC_RECONFIG_NOW |
 510 
			     RADEON_PCIE_LC_RECONFIG_NOW |
511 
			     RADEON_PCIE_LC_RECONFIG_LATER |
 511 
			     RADEON_PCIE_LC_RECONFIG_LATER |
512 
			     RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 512 
			     RADEON_PCIE_LC_SHORT_RECONFIG_EN);
513 
	link_width_cntl |= mask;
 513 
	link_width_cntl |= mask;
514 
	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 514 
	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
515 
	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 515 
	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
516 
						     RADEON_PCIE_LC_RECONFIG_NOW));
 516 
						     RADEON_PCIE_LC_RECONFIG_NOW));
517 
 
 517 
 
518 
	/* wait for lane set to complete */
 518 
	/* wait for lane set to complete */
519 
	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 519 
	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
520 
	while (link_width_cntl == 0xffffffff)
 520 
	while (link_width_cntl == 0xffffffff)
521 
		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 521 
		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
522 
 
 522 
 
523 
}
 523 
}
524 
 
 524 
 
525 
int rv370_get_pcie_lanes(struct radeon_device *rdev)
 525 
int rv370_get_pcie_lanes(struct radeon_device *rdev)
526 
{
 526 
{
527 
	u32 link_width_cntl;
 527 
	u32 link_width_cntl;
528 
 
 528 
 
529 
	if (rdev->flags & RADEON_IS_IGP)
 529 
	if (rdev->flags & RADEON_IS_IGP)
530 
		return 0;
 530 
		return 0;
531 
 
 531 
 
532 
	if (!(rdev->flags & RADEON_IS_PCIE))
 532 
	if (!(rdev->flags & RADEON_IS_PCIE))
533 
		return 0;
 533 
		return 0;
534 
 
 534 
 
535 
	/* FIXME wait for idle */
 535 
	/* FIXME wait for idle */
536 
 
 536 
 
537 
		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 537 
		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
538 
 
 538 
 
539 
	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 539 
	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
540 
	case RADEON_PCIE_LC_LINK_WIDTH_X0:
 540 
	case RADEON_PCIE_LC_LINK_WIDTH_X0:
541 
		return 0;
 541 
		return 0;
542 
	case RADEON_PCIE_LC_LINK_WIDTH_X1:
 542 
	case RADEON_PCIE_LC_LINK_WIDTH_X1:
543 
		return 1;
 543 
		return 1;
544 
	case RADEON_PCIE_LC_LINK_WIDTH_X2:
 544 
	case RADEON_PCIE_LC_LINK_WIDTH_X2:
545 
		return 2;
 545 
		return 2;
546 
	case RADEON_PCIE_LC_LINK_WIDTH_X4:
 546 
	case RADEON_PCIE_LC_LINK_WIDTH_X4:
547 
		return 4;
 547 
		return 4;
548 
	case RADEON_PCIE_LC_LINK_WIDTH_X8:
 548 
	case RADEON_PCIE_LC_LINK_WIDTH_X8:
549 
		return 8;
 549 
		return 8;
550 
	case RADEON_PCIE_LC_LINK_WIDTH_X16:
 550 
	case RADEON_PCIE_LC_LINK_WIDTH_X16:
551 
	default:
 551 
	default:
552 
		return 16;
 552 
		return 16;
553 
	}
 553 
	}
554 
}
 554 
}
555 
 
 555 
 
556 
#if defined(CONFIG_DEBUG_FS)
 556 
#if defined(CONFIG_DEBUG_FS)
557 
static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 557 
static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
558 
{
 558 
{
559 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
 559 
	struct drm_info_node *node = (struct drm_info_node *) m->private;
560 
	struct drm_device *dev = node->minor->dev;
 560 
	struct drm_device *dev = node->minor->dev;
561 
	struct radeon_device *rdev = dev->dev_private;
 561 
	struct radeon_device *rdev = dev->dev_private;
562 
	uint32_t tmp;
 562 
	uint32_t tmp;
563 
 
 563 
 
564 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 564 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
565 
	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 565 
	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
566 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 566 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
567 
	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 567 
	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
568 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 568 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
569 
	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 569 
	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
570 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 570 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
571 
	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 571 
	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
572 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 572 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
573 
	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 573 
	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
574 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 574 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
575 
	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 575 
	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
576 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 576 
	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
577 
	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 577 
	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
578 
	return 0;
 578 
	return 0;
579 
}
 579 
}
580 
 
 580 
 
581 
static struct drm_info_list rv370_pcie_gart_info_list[] = {
 581 
static struct drm_info_list rv370_pcie_gart_info_list[] = {
582 
	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 582 
	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
583 
};
 583 
};
584 
#endif
 584 
#endif
585 
 
 585 
 
586 
static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 586 
static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
587 
{
 587 
{
588 
#if defined(CONFIG_DEBUG_FS)
 588 
#if defined(CONFIG_DEBUG_FS)
589 
	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 589 
	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
590 
#else
 590 
#else
591 
	return 0;
 591 
	return 0;
592 
#endif
 592 
#endif
593 
}
 593 
}
594 
 
 594 
 
595 
 
 595 
 
596 
#if 0
 596 
#if 0
597 
 
 597 
 
598 
static int r300_packet0_check(struct radeon_cs_parser *p,
 598 
static int r300_packet0_check(struct radeon_cs_parser *p,
599 
		struct radeon_cs_packet *pkt,
 599 
		struct radeon_cs_packet *pkt,
600 
		unsigned idx, unsigned reg)
 600 
		unsigned idx, unsigned reg)
601 
{
 601 
{
602 
	struct radeon_cs_reloc *reloc;
 602 
	struct radeon_cs_reloc *reloc;
603 
	struct r100_cs_track *track;
 603 
	struct r100_cs_track *track;
604 
	volatile uint32_t *ib;
 604 
	volatile uint32_t *ib;
605 
	uint32_t tmp, tile_flags = 0;
 605 
	uint32_t tmp, tile_flags = 0;
606 
	unsigned i;
 606 
	unsigned i;
607 
	int r;
 607 
	int r;
608 
	u32 idx_value;
 608 
	u32 idx_value;
609 
 
 609 
 
610 
	ib = p->ib.ptr;
 610 
	ib = p->ib.ptr;
611 
	track = (struct r100_cs_track *)p->track;
 611 
	track = (struct r100_cs_track *)p->track;
612 
	idx_value = radeon_get_ib_value(p, idx);
 612 
	idx_value = radeon_get_ib_value(p, idx);
613 
 
 613 
 
614 
	switch(reg) {
 614 
	switch(reg) {
615 
	case AVIVO_D1MODE_VLINE_START_END:
 615 
	case AVIVO_D1MODE_VLINE_START_END:
616 
	case RADEON_CRTC_GUI_TRIG_VLINE:
 616 
	case RADEON_CRTC_GUI_TRIG_VLINE:
617 
		r = r100_cs_packet_parse_vline(p);
 617 
		r = r100_cs_packet_parse_vline(p);
618 
		if (r) {
 618 
		if (r) {
619 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 619 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
620 
					idx, reg);
 620 
					idx, reg);
621 
			r100_cs_dump_packet(p, pkt);
 621 
			radeon_cs_dump_packet(p, pkt);
622 
			return r;
 622 
			return r;
623 
		}
 623 
		}
624 
		break;
 624 
		break;
625 
	case RADEON_DST_PITCH_OFFSET:
 625 
	case RADEON_DST_PITCH_OFFSET:
626 
	case RADEON_SRC_PITCH_OFFSET:
 626 
	case RADEON_SRC_PITCH_OFFSET:
627 
		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 627 
		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
628 
		if (r)
 628 
		if (r)
629 
			return r;
 629 
			return r;
630 
		break;
 630 
		break;
631 
	case R300_RB3D_COLOROFFSET0:
 631 
	case R300_RB3D_COLOROFFSET0:
632 
	case R300_RB3D_COLOROFFSET1:
 632 
	case R300_RB3D_COLOROFFSET1:
633 
	case R300_RB3D_COLOROFFSET2:
 633 
	case R300_RB3D_COLOROFFSET2:
634 
	case R300_RB3D_COLOROFFSET3:
 634 
	case R300_RB3D_COLOROFFSET3:
635 
		i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 635 
		i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
636 
		r = r100_cs_packet_next_reloc(p, &reloc);
 636 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
637 
		if (r) {
 637 
		if (r) {
638 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 638 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
639 
					idx, reg);
 639 
					idx, reg);
640 
			r100_cs_dump_packet(p, pkt);
 640 
			radeon_cs_dump_packet(p, pkt);
641 
			return r;
 641 
			return r;
642 
		}
 642 
		}
643 
		track->cb[i].robj = reloc->robj;
 643 
		track->cb[i].robj = reloc->robj;
644 
		track->cb[i].offset = idx_value;
 644 
		track->cb[i].offset = idx_value;
645 
		track->cb_dirty = true;
 645 
		track->cb_dirty = true;
646 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 646 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
647 
		break;
 647 
		break;
648 
	case R300_ZB_DEPTHOFFSET:
 648 
	case R300_ZB_DEPTHOFFSET:
649 
		r = r100_cs_packet_next_reloc(p, &reloc);
 649 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
650 
		if (r) {
 650 
		if (r) {
651 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 651 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
652 
					idx, reg);
 652 
					idx, reg);
653 
			r100_cs_dump_packet(p, pkt);
 653 
			radeon_cs_dump_packet(p, pkt);
654 
			return r;
 654 
			return r;
655 
		}
 655 
		}
656 
		track->zb.robj = reloc->robj;
 656 
		track->zb.robj = reloc->robj;
657 
		track->zb.offset = idx_value;
 657 
		track->zb.offset = idx_value;
658 
		track->zb_dirty = true;
 658 
		track->zb_dirty = true;
659 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 659 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
660 
		break;
 660 
		break;
661 
	case R300_TX_OFFSET_0:
 661 
	case R300_TX_OFFSET_0:
662 
	case R300_TX_OFFSET_0+4:
 662 
	case R300_TX_OFFSET_0+4:
663 
	case R300_TX_OFFSET_0+8:
 663 
	case R300_TX_OFFSET_0+8:
664 
	case R300_TX_OFFSET_0+12:
 664 
	case R300_TX_OFFSET_0+12:
665 
	case R300_TX_OFFSET_0+16:
 665 
	case R300_TX_OFFSET_0+16:
666 
	case R300_TX_OFFSET_0+20:
 666 
	case R300_TX_OFFSET_0+20:
667 
	case R300_TX_OFFSET_0+24:
 667 
	case R300_TX_OFFSET_0+24:
668 
	case R300_TX_OFFSET_0+28:
 668 
	case R300_TX_OFFSET_0+28:
669 
	case R300_TX_OFFSET_0+32:
 669 
	case R300_TX_OFFSET_0+32:
670 
	case R300_TX_OFFSET_0+36:
 670 
	case R300_TX_OFFSET_0+36:
671 
	case R300_TX_OFFSET_0+40:
 671 
	case R300_TX_OFFSET_0+40:
672 
	case R300_TX_OFFSET_0+44:
 672 
	case R300_TX_OFFSET_0+44:
673 
	case R300_TX_OFFSET_0+48:
 673 
	case R300_TX_OFFSET_0+48:
674 
	case R300_TX_OFFSET_0+52:
 674 
	case R300_TX_OFFSET_0+52:
675 
	case R300_TX_OFFSET_0+56:
 675 
	case R300_TX_OFFSET_0+56:
676 
	case R300_TX_OFFSET_0+60:
 676 
	case R300_TX_OFFSET_0+60:
677 
		i = (reg - R300_TX_OFFSET_0) >> 2;
 677 
		i = (reg - R300_TX_OFFSET_0) >> 2;
678 
		r = r100_cs_packet_next_reloc(p, &reloc);
 678 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
679 
		if (r) {
 679 
		if (r) {
680 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 680 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
681 
					idx, reg);
 681 
					idx, reg);
682 
			r100_cs_dump_packet(p, pkt);
 682 
			radeon_cs_dump_packet(p, pkt);
683 
			return r;
 683 
			return r;
684 
		}
 684 
		}
685 
 
 685 
 
686 
		if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 686 
		if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
687 
			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
 687 
			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
688 
				  ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
 688 
				  ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
689 
		} else {
 689 
		} else {
690 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 690 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
691 
			tile_flags |= R300_TXO_MACRO_TILE;
 691 
			tile_flags |= R300_TXO_MACRO_TILE;
692 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 692 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
693 
			tile_flags |= R300_TXO_MICRO_TILE;
 693 
			tile_flags |= R300_TXO_MICRO_TILE;
694 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 694 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
695 
			tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 695 
			tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
696 
 
 696 
 
697 
		tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 697 
		tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
698 
		tmp |= tile_flags;
 698 
		tmp |= tile_flags;
699 
		ib[idx] = tmp;
 699 
		ib[idx] = tmp;
700 
		}
 700 
		}
701 
		track->textures[i].robj = reloc->robj;
 701 
		track->textures[i].robj = reloc->robj;
702 
		track->tex_dirty = true;
 702 
		track->tex_dirty = true;
703 
		break;
 703 
		break;
704 
	/* Tracked registers */
 704 
	/* Tracked registers */
705 
	case 0x2084:
 705 
	case 0x2084:
706 
		/* VAP_VF_CNTL */
 706 
		/* VAP_VF_CNTL */
707 
		track->vap_vf_cntl = idx_value;
 707 
		track->vap_vf_cntl = idx_value;
708 
		break;
 708 
		break;
709 
	case 0x20B4:
 709 
	case 0x20B4:
710 
		/* VAP_VTX_SIZE */
 710 
		/* VAP_VTX_SIZE */
711 
		track->vtx_size = idx_value & 0x7F;
 711 
		track->vtx_size = idx_value & 0x7F;
712 
		break;
 712 
		break;
713 
	case 0x2134:
 713 
	case 0x2134:
714 
		/* VAP_VF_MAX_VTX_INDX */
 714 
		/* VAP_VF_MAX_VTX_INDX */
715 
		track->max_indx = idx_value & 0x00FFFFFFUL;
 715 
		track->max_indx = idx_value & 0x00FFFFFFUL;
716 
		break;
 716 
		break;
717 
	case 0x2088:
 717 
	case 0x2088:
718 
		/* VAP_ALT_NUM_VERTICES - only valid on r500 */
 718 
		/* VAP_ALT_NUM_VERTICES - only valid on r500 */
719 
		if (p->rdev->family < CHIP_RV515)
 719 
		if (p->rdev->family < CHIP_RV515)
720 
			goto fail;
 720 
			goto fail;
721 
		track->vap_alt_nverts = idx_value & 0xFFFFFF;
 721 
		track->vap_alt_nverts = idx_value & 0xFFFFFF;
722 
		break;
 722 
		break;
723 
	case 0x43E4:
 723 
	case 0x43E4:
724 
		/* SC_SCISSOR1 */
 724 
		/* SC_SCISSOR1 */
725 
		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 725 
		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
726 
		if (p->rdev->family < CHIP_RV515) {
 726 
		if (p->rdev->family < CHIP_RV515) {
727 
			track->maxy -= 1440;
 727 
			track->maxy -= 1440;
728 
		}
 728 
		}
729 
		track->cb_dirty = true;
 729 
		track->cb_dirty = true;
730 
		track->zb_dirty = true;
 730 
		track->zb_dirty = true;
731 
		break;
 731 
		break;
732 
	case 0x4E00:
 732 
	case 0x4E00:
733 
		/* RB3D_CCTL */
 733 
		/* RB3D_CCTL */
734 
		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 734 
		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
735 
		    p->rdev->cmask_filp != p->filp) {
 735 
		    p->rdev->cmask_filp != p->filp) {
736 
			DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 736 
			DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
737 
			return -EINVAL;
 737 
			return -EINVAL;
738 
		}
 738 
		}
739 
		track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 739 
		track->num_cb = ((idx_value >> 5) & 0x3) + 1;
740 
		track->cb_dirty = true;
 740 
		track->cb_dirty = true;
741 
		break;
 741 
		break;
742 
	case 0x4E38:
 742 
	case 0x4E38:
743 
	case 0x4E3C:
 743 
	case 0x4E3C:
744 
	case 0x4E40:
 744 
	case 0x4E40:
745 
	case 0x4E44:
 745 
	case 0x4E44:
746 
		/* RB3D_COLORPITCH0 */
 746 
		/* RB3D_COLORPITCH0 */
747 
		/* RB3D_COLORPITCH1 */
 747 
		/* RB3D_COLORPITCH1 */
748 
		/* RB3D_COLORPITCH2 */
 748 
		/* RB3D_COLORPITCH2 */
749 
		/* RB3D_COLORPITCH3 */
 749 
		/* RB3D_COLORPITCH3 */
750 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 750 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
751 
		r = r100_cs_packet_next_reloc(p, &reloc);
 751 
			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
752 
		if (r) {
 752 
		if (r) {
753 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 753 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
754 
				  idx, reg);
 754 
				  idx, reg);
755 
			r100_cs_dump_packet(p, pkt);
 755 
				radeon_cs_dump_packet(p, pkt);
756 
			return r;
 756 
			return r;
757 
		}
 757 
		}
758 
 
 758 
 
759 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 759 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
760 
			tile_flags |= R300_COLOR_TILE_ENABLE;
 760 
			tile_flags |= R300_COLOR_TILE_ENABLE;
761 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 761 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
762 
			tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 762 
			tile_flags |= R300_COLOR_MICROTILE_ENABLE;
763 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 763 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
764 
			tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 764 
			tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
765 
 
 765 
 
766 
		tmp = idx_value & ~(0x7 << 16);
 766 
		tmp = idx_value & ~(0x7 << 16);
767 
		tmp |= tile_flags;
 767 
		tmp |= tile_flags;
768 
		ib[idx] = tmp;
 768 
		ib[idx] = tmp;
769 
		}
 769 
		}
770 
		i = (reg - 0x4E38) >> 2;
 770 
		i = (reg - 0x4E38) >> 2;
771 
		track->cb[i].pitch = idx_value & 0x3FFE;
 771 
		track->cb[i].pitch = idx_value & 0x3FFE;
772 
		switch (((idx_value >> 21) & 0xF)) {
 772 
		switch (((idx_value >> 21) & 0xF)) {
773 
		case 9:
 773 
		case 9:
774 
		case 11:
 774 
		case 11:
775 
		case 12:
 775 
		case 12:
776 
			track->cb[i].cpp = 1;
 776 
			track->cb[i].cpp = 1;
777 
			break;
 777 
			break;
778 
		case 3:
 778 
		case 3:
779 
		case 4:
 779 
		case 4:
780 
		case 13:
 780 
		case 13:
781 
		case 15:
 781 
		case 15:
782 
			track->cb[i].cpp = 2;
 782 
			track->cb[i].cpp = 2;
783 
			break;
 783 
			break;
784 
		case 5:
 784 
		case 5:
785 
			if (p->rdev->family < CHIP_RV515) {
 785 
			if (p->rdev->family < CHIP_RV515) {
786 
				DRM_ERROR("Invalid color buffer format (%d)!\n",
 786 
				DRM_ERROR("Invalid color buffer format (%d)!\n",
787 
					  ((idx_value >> 21) & 0xF));
 787 
					  ((idx_value >> 21) & 0xF));
788 
				return -EINVAL;
 788 
				return -EINVAL;
789 
			}
 789 
			}
790 
			/* Pass through. */
 790 
			/* Pass through. */
791 
		case 6:
 791 
		case 6:
792 
			track->cb[i].cpp = 4;
 792 
			track->cb[i].cpp = 4;
793 
			break;
 793 
			break;
794 
		case 10:
 794 
		case 10:
795 
			track->cb[i].cpp = 8;
 795 
			track->cb[i].cpp = 8;
796 
			break;
 796 
			break;
797 
		case 7:
 797 
		case 7:
798 
			track->cb[i].cpp = 16;
 798 
			track->cb[i].cpp = 16;
799 
			break;
 799 
			break;
800 
		default:
 800 
		default:
801 
			DRM_ERROR("Invalid color buffer format (%d) !\n",
 801 
			DRM_ERROR("Invalid color buffer format (%d) !\n",
802 
				  ((idx_value >> 21) & 0xF));
 802 
				  ((idx_value >> 21) & 0xF));
803 
			return -EINVAL;
 803 
			return -EINVAL;
804 
		}
 804 
		}
805 
		track->cb_dirty = true;
 805 
		track->cb_dirty = true;
806 
		break;
 806 
		break;
807 
	case 0x4F00:
 807 
	case 0x4F00:
808 
		/* ZB_CNTL */
 808 
		/* ZB_CNTL */
809 
		if (idx_value & 2) {
 809 
		if (idx_value & 2) {
810 
			track->z_enabled = true;
 810 
			track->z_enabled = true;
811 
		} else {
 811 
		} else {
812 
			track->z_enabled = false;
 812 
			track->z_enabled = false;
813 
		}
 813 
		}
814 
		track->zb_dirty = true;
 814 
		track->zb_dirty = true;
815 
		break;
 815 
		break;
816 
	case 0x4F10:
 816 
	case 0x4F10:
817 
		/* ZB_FORMAT */
 817 
		/* ZB_FORMAT */
818 
		switch ((idx_value & 0xF)) {
 818 
		switch ((idx_value & 0xF)) {
819 
		case 0:
 819 
		case 0:
820 
		case 1:
 820 
		case 1:
821 
			track->zb.cpp = 2;
 821 
			track->zb.cpp = 2;
822 
			break;
 822 
			break;
823 
		case 2:
 823 
		case 2:
824 
			track->zb.cpp = 4;
 824 
			track->zb.cpp = 4;
825 
			break;
 825 
			break;
826 
		default:
 826 
		default:
827 
			DRM_ERROR("Invalid z buffer format (%d) !\n",
 827 
			DRM_ERROR("Invalid z buffer format (%d) !\n",
828 
				  (idx_value & 0xF));
 828 
				  (idx_value & 0xF));
829 
			return -EINVAL;
 829 
			return -EINVAL;
830 
		}
 830 
		}
831 
		track->zb_dirty = true;
 831 
		track->zb_dirty = true;
832 
		break;
 832 
		break;
833 
	case 0x4F24:
 833 
	case 0x4F24:
834 
		/* ZB_DEPTHPITCH */
 834 
		/* ZB_DEPTHPITCH */
835 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 835 
		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
836 
		r = r100_cs_packet_next_reloc(p, &reloc);
 836 
			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
837 
		if (r) {
 837 
		if (r) {
838 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 838 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
839 
				  idx, reg);
 839 
				  idx, reg);
840 
			r100_cs_dump_packet(p, pkt);
 840 
				radeon_cs_dump_packet(p, pkt);
841 
			return r;
 841 
			return r;
842 
		}
 842 
		}
843 
 
 843 
 
844 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 844 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
845 
			tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 845 
			tile_flags |= R300_DEPTHMACROTILE_ENABLE;
846 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 846 
		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
847 
			tile_flags |= R300_DEPTHMICROTILE_TILED;
 847 
			tile_flags |= R300_DEPTHMICROTILE_TILED;
848 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 848 
		else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
849 
			tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 849 
			tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
850 
 
 850 
 
851 
		tmp = idx_value & ~(0x7 << 16);
 851 
		tmp = idx_value & ~(0x7 << 16);
852 
		tmp |= tile_flags;
 852 
		tmp |= tile_flags;
853 
		ib[idx] = tmp;
 853 
		ib[idx] = tmp;
854 
		}
 854 
		}
855 
		track->zb.pitch = idx_value & 0x3FFC;
 855 
		track->zb.pitch = idx_value & 0x3FFC;
856 
		track->zb_dirty = true;
 856 
		track->zb_dirty = true;
857 
		break;
 857 
		break;
858 
	case 0x4104:
 858 
	case 0x4104:
859 
		/* TX_ENABLE */
 859 
		/* TX_ENABLE */
860 
		for (i = 0; i < 16; i++) {
 860 
		for (i = 0; i < 16; i++) {
861 
			bool enabled;
 861 
			bool enabled;
862 
 
 862 
 
863 
			enabled = !!(idx_value & (1 << i));
 863 
			enabled = !!(idx_value & (1 << i));
864 
			track->textures[i].enabled = enabled;
 864 
			track->textures[i].enabled = enabled;
865 
		}
 865 
		}
866 
		track->tex_dirty = true;
 866 
		track->tex_dirty = true;
867 
		break;
 867 
		break;
868 
	case 0x44C0:
 868 
	case 0x44C0:
869 
	case 0x44C4:
 869 
	case 0x44C4:
870 
	case 0x44C8:
 870 
	case 0x44C8:
871 
	case 0x44CC:
 871 
	case 0x44CC:
872 
	case 0x44D0:
 872 
	case 0x44D0:
873 
	case 0x44D4:
 873 
	case 0x44D4:
874 
	case 0x44D8:
 874 
	case 0x44D8:
875 
	case 0x44DC:
 875 
	case 0x44DC:
876 
	case 0x44E0:
 876 
	case 0x44E0:
877 
	case 0x44E4:
 877 
	case 0x44E4:
878 
	case 0x44E8:
 878 
	case 0x44E8:
879 
	case 0x44EC:
 879 
	case 0x44EC:
880 
	case 0x44F0:
 880 
	case 0x44F0:
881 
	case 0x44F4:
 881 
	case 0x44F4:
882 
	case 0x44F8:
 882 
	case 0x44F8:
883 
	case 0x44FC:
 883 
	case 0x44FC:
884 
		/* TX_FORMAT1_[0-15] */
 884 
		/* TX_FORMAT1_[0-15] */
885 
		i = (reg - 0x44C0) >> 2;
 885 
		i = (reg - 0x44C0) >> 2;
886 
		tmp = (idx_value >> 25) & 0x3;
 886 
		tmp = (idx_value >> 25) & 0x3;
887 
		track->textures[i].tex_coord_type = tmp;
 887 
		track->textures[i].tex_coord_type = tmp;
888 
		switch ((idx_value & 0x1F)) {
 888 
		switch ((idx_value & 0x1F)) {
889 
		case R300_TX_FORMAT_X8:
 889 
		case R300_TX_FORMAT_X8:
890 
		case R300_TX_FORMAT_Y4X4:
 890 
		case R300_TX_FORMAT_Y4X4:
891 
		case R300_TX_FORMAT_Z3Y3X2:
 891 
		case R300_TX_FORMAT_Z3Y3X2:
892 
			track->textures[i].cpp = 1;
 892 
			track->textures[i].cpp = 1;
893 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 893 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
894 
			break;
 894 
			break;
895 
		case R300_TX_FORMAT_X16:
 895 
		case R300_TX_FORMAT_X16:
896 
		case R300_TX_FORMAT_FL_I16:
 896 
		case R300_TX_FORMAT_FL_I16:
897 
		case R300_TX_FORMAT_Y8X8:
 897 
		case R300_TX_FORMAT_Y8X8:
898 
		case R300_TX_FORMAT_Z5Y6X5:
 898 
		case R300_TX_FORMAT_Z5Y6X5:
899 
		case R300_TX_FORMAT_Z6Y5X5:
 899 
		case R300_TX_FORMAT_Z6Y5X5:
900 
		case R300_TX_FORMAT_W4Z4Y4X4:
 900 
		case R300_TX_FORMAT_W4Z4Y4X4:
901 
		case R300_TX_FORMAT_W1Z5Y5X5:
 901 
		case R300_TX_FORMAT_W1Z5Y5X5:
902 
		case R300_TX_FORMAT_D3DMFT_CxV8U8:
 902 
		case R300_TX_FORMAT_D3DMFT_CxV8U8:
903 
		case R300_TX_FORMAT_B8G8_B8G8:
 903 
		case R300_TX_FORMAT_B8G8_B8G8:
904 
		case R300_TX_FORMAT_G8R8_G8B8:
 904 
		case R300_TX_FORMAT_G8R8_G8B8:
905 
			track->textures[i].cpp = 2;
 905 
			track->textures[i].cpp = 2;
906 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 906 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
907 
			break;
 907 
			break;
908 
		case R300_TX_FORMAT_Y16X16:
 908 
		case R300_TX_FORMAT_Y16X16:
909 
		case R300_TX_FORMAT_FL_I16A16:
 909 
		case R300_TX_FORMAT_FL_I16A16:
910 
		case R300_TX_FORMAT_Z11Y11X10:
 910 
		case R300_TX_FORMAT_Z11Y11X10:
911 
		case R300_TX_FORMAT_Z10Y11X11:
 911 
		case R300_TX_FORMAT_Z10Y11X11:
912 
		case R300_TX_FORMAT_W8Z8Y8X8:
 912 
		case R300_TX_FORMAT_W8Z8Y8X8:
913 
		case R300_TX_FORMAT_W2Z10Y10X10:
 913 
		case R300_TX_FORMAT_W2Z10Y10X10:
914 
		case 0x17:
 914 
		case 0x17:
915 
		case R300_TX_FORMAT_FL_I32:
 915 
		case R300_TX_FORMAT_FL_I32:
916 
		case 0x1e:
 916 
		case 0x1e:
917 
			track->textures[i].cpp = 4;
 917 
			track->textures[i].cpp = 4;
918 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 918 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
919 
			break;
 919 
			break;
920 
		case R300_TX_FORMAT_W16Z16Y16X16:
 920 
		case R300_TX_FORMAT_W16Z16Y16X16:
921 
		case R300_TX_FORMAT_FL_R16G16B16A16:
 921 
		case R300_TX_FORMAT_FL_R16G16B16A16:
922 
		case R300_TX_FORMAT_FL_I32A32:
 922 
		case R300_TX_FORMAT_FL_I32A32:
923 
			track->textures[i].cpp = 8;
 923 
			track->textures[i].cpp = 8;
924 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 924 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
925 
			break;
 925 
			break;
926 
		case R300_TX_FORMAT_FL_R32G32B32A32:
 926 
		case R300_TX_FORMAT_FL_R32G32B32A32:
927 
			track->textures[i].cpp = 16;
 927 
			track->textures[i].cpp = 16;
928 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 928 
			track->textures[i].compress_format = R100_TRACK_COMP_NONE;
929 
			break;
 929 
			break;
930 
		case R300_TX_FORMAT_DXT1:
 930 
		case R300_TX_FORMAT_DXT1:
931 
			track->textures[i].cpp = 1;
 931 
			track->textures[i].cpp = 1;
932 
			track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 932 
			track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
933 
			break;
 933 
			break;
934 
		case R300_TX_FORMAT_ATI2N:
 934 
		case R300_TX_FORMAT_ATI2N:
935 
			if (p->rdev->family < CHIP_R420) {
 935 
			if (p->rdev->family < CHIP_R420) {
936 
				DRM_ERROR("Invalid texture format %u\n",
 936 
				DRM_ERROR("Invalid texture format %u\n",
937 
					  (idx_value & 0x1F));
 937 
					  (idx_value & 0x1F));
938 
				return -EINVAL;
 938 
				return -EINVAL;
939 
			}
 939 
			}
940 
			/* The same rules apply as for DXT3/5. */
 940 
			/* The same rules apply as for DXT3/5. */
941 
			/* Pass through. */
 941 
			/* Pass through. */
942 
		case R300_TX_FORMAT_DXT3:
 942 
		case R300_TX_FORMAT_DXT3:
943 
		case R300_TX_FORMAT_DXT5:
 943 
		case R300_TX_FORMAT_DXT5:
944 
			track->textures[i].cpp = 1;
 944 
			track->textures[i].cpp = 1;
945 
			track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 945 
			track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
946 
			break;
 946 
			break;
947 
		default:
 947 
		default:
948 
			DRM_ERROR("Invalid texture format %u\n",
 948 
			DRM_ERROR("Invalid texture format %u\n",
949 
				  (idx_value & 0x1F));
 949 
				  (idx_value & 0x1F));
950 
			return -EINVAL;
 950 
			return -EINVAL;
951 
		}
 951 
		}
952 
		track->tex_dirty = true;
 952 
		track->tex_dirty = true;
953 
		break;
 953 
		break;
954 
	case 0x4400:
 954 
	case 0x4400:
955 
	case 0x4404:
 955 
	case 0x4404:
956 
	case 0x4408:
 956 
	case 0x4408:
957 
	case 0x440C:
 957 
	case 0x440C:
958 
	case 0x4410:
 958 
	case 0x4410:
959 
	case 0x4414:
 959 
	case 0x4414:
960 
	case 0x4418:
 960 
	case 0x4418:
961 
	case 0x441C:
 961 
	case 0x441C:
962 
	case 0x4420:
 962 
	case 0x4420:
963 
	case 0x4424:
 963 
	case 0x4424:
964 
	case 0x4428:
 964 
	case 0x4428:
965 
	case 0x442C:
 965 
	case 0x442C:
966 
	case 0x4430:
 966 
	case 0x4430:
967 
	case 0x4434:
 967 
	case 0x4434:
968 
	case 0x4438:
 968 
	case 0x4438:
969 
	case 0x443C:
 969 
	case 0x443C:
970 
		/* TX_FILTER0_[0-15] */
 970 
		/* TX_FILTER0_[0-15] */
971 
		i = (reg - 0x4400) >> 2;
 971 
		i = (reg - 0x4400) >> 2;
972 
		tmp = idx_value & 0x7;
 972 
		tmp = idx_value & 0x7;
973 
		if (tmp == 2 || tmp == 4 || tmp == 6) {
 973 
		if (tmp == 2 || tmp == 4 || tmp == 6) {
974 
			track->textures[i].roundup_w = false;
 974 
			track->textures[i].roundup_w = false;
975 
		}
 975 
		}
976 
		tmp = (idx_value >> 3) & 0x7;
 976 
		tmp = (idx_value >> 3) & 0x7;
977 
		if (tmp == 2 || tmp == 4 || tmp == 6) {
 977 
		if (tmp == 2 || tmp == 4 || tmp == 6) {
978 
			track->textures[i].roundup_h = false;
 978 
			track->textures[i].roundup_h = false;
979 
		}
 979 
		}
980 
		track->tex_dirty = true;
 980 
		track->tex_dirty = true;
981 
		break;
 981 
		break;
982 
	case 0x4500:
 982 
	case 0x4500:
983 
	case 0x4504:
 983 
	case 0x4504:
984 
	case 0x4508:
 984 
	case 0x4508:
985 
	case 0x450C:
 985 
	case 0x450C:
986 
	case 0x4510:
 986 
	case 0x4510:
987 
	case 0x4514:
 987 
	case 0x4514:
988 
	case 0x4518:
 988 
	case 0x4518:
989 
	case 0x451C:
 989 
	case 0x451C:
990 
	case 0x4520:
 990 
	case 0x4520:
991 
	case 0x4524:
 991 
	case 0x4524:
992 
	case 0x4528:
 992 
	case 0x4528:
993 
	case 0x452C:
 993 
	case 0x452C:
994 
	case 0x4530:
 994 
	case 0x4530:
995 
	case 0x4534:
 995 
	case 0x4534:
996 
	case 0x4538:
 996 
	case 0x4538:
997 
	case 0x453C:
 997 
	case 0x453C:
998 
		/* TX_FORMAT2_[0-15] */
 998 
		/* TX_FORMAT2_[0-15] */
999 
		i = (reg - 0x4500) >> 2;
 999 
		i = (reg - 0x4500) >> 2;
1000 
		tmp = idx_value & 0x3FFF;
 1000 
		tmp = idx_value & 0x3FFF;
1001 
		track->textures[i].pitch = tmp + 1;
 1001 
		track->textures[i].pitch = tmp + 1;
1002 
		if (p->rdev->family >= CHIP_RV515) {
 1002 
		if (p->rdev->family >= CHIP_RV515) {
1003 
			tmp = ((idx_value >> 15) & 1) << 11;
 1003 
			tmp = ((idx_value >> 15) & 1) << 11;
1004 
			track->textures[i].width_11 = tmp;
 1004 
			track->textures[i].width_11 = tmp;
1005 
			tmp = ((idx_value >> 16) & 1) << 11;
 1005 
			tmp = ((idx_value >> 16) & 1) << 11;
1006 
			track->textures[i].height_11 = tmp;
 1006 
			track->textures[i].height_11 = tmp;
1007 
 
 1007 
 
1008 
			/* ATI1N */
 1008 
			/* ATI1N */
1009 
			if (idx_value & (1 << 14)) {
 1009 
			if (idx_value & (1 << 14)) {
1010 
				/* The same rules apply as for DXT1. */
 1010 
				/* The same rules apply as for DXT1. */
1011 
				track->textures[i].compress_format =
 1011 
				track->textures[i].compress_format =
1012 
					R100_TRACK_COMP_DXT1;
 1012 
					R100_TRACK_COMP_DXT1;
1013 
			}
 1013 
			}
1014 
		} else if (idx_value & (1 << 14)) {
 1014 
		} else if (idx_value & (1 << 14)) {
1015 
			DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
 1015 
			DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1016 
			return -EINVAL;
 1016 
			return -EINVAL;
1017 
		}
 1017 
		}
1018 
		track->tex_dirty = true;
 1018 
		track->tex_dirty = true;
1019 
		break;
 1019 
		break;
1020 
	case 0x4480:
 1020 
	case 0x4480:
1021 
	case 0x4484:
 1021 
	case 0x4484:
1022 
	case 0x4488:
 1022 
	case 0x4488:
1023 
	case 0x448C:
 1023 
	case 0x448C:
1024 
	case 0x4490:
 1024 
	case 0x4490:
1025 
	case 0x4494:
 1025 
	case 0x4494:
1026 
	case 0x4498:
 1026 
	case 0x4498:
1027 
	case 0x449C:
 1027 
	case 0x449C:
1028 
	case 0x44A0:
 1028 
	case 0x44A0:
1029 
	case 0x44A4:
 1029 
	case 0x44A4:
1030 
	case 0x44A8:
 1030 
	case 0x44A8:
1031 
	case 0x44AC:
 1031 
	case 0x44AC:
1032 
	case 0x44B0:
 1032 
	case 0x44B0:
1033 
	case 0x44B4:
 1033 
	case 0x44B4:
1034 
	case 0x44B8:
 1034 
	case 0x44B8:
1035 
	case 0x44BC:
 1035 
	case 0x44BC:
1036 
		/* TX_FORMAT0_[0-15] */
 1036 
		/* TX_FORMAT0_[0-15] */
1037 
		i = (reg - 0x4480) >> 2;
 1037 
		i = (reg - 0x4480) >> 2;
1038 
		tmp = idx_value & 0x7FF;
 1038 
		tmp = idx_value & 0x7FF;
1039 
		track->textures[i].width = tmp + 1;
 1039 
		track->textures[i].width = tmp + 1;
1040 
		tmp = (idx_value >> 11) & 0x7FF;
 1040 
		tmp = (idx_value >> 11) & 0x7FF;
1041 
		track->textures[i].height = tmp + 1;
 1041 
		track->textures[i].height = tmp + 1;
1042 
		tmp = (idx_value >> 26) & 0xF;
 1042 
		tmp = (idx_value >> 26) & 0xF;
1043 
		track->textures[i].num_levels = tmp;
 1043 
		track->textures[i].num_levels = tmp;
1044 
		tmp = idx_value & (1 << 31);
 1044 
		tmp = idx_value & (1 << 31);
1045 
		track->textures[i].use_pitch = !!tmp;
 1045 
		track->textures[i].use_pitch = !!tmp;
1046 
		tmp = (idx_value >> 22) & 0xF;
 1046 
		tmp = (idx_value >> 22) & 0xF;
1047 
		track->textures[i].txdepth = tmp;
 1047 
		track->textures[i].txdepth = tmp;
1048 
		track->tex_dirty = true;
 1048 
		track->tex_dirty = true;
1049 
		break;
 1049 
		break;
1050 
	case R300_ZB_ZPASS_ADDR:
 1050 
	case R300_ZB_ZPASS_ADDR:
1051 
		r = r100_cs_packet_next_reloc(p, &reloc);
 1051 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1052 
		if (r) {
 1052 
		if (r) {
1053 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 1053 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1054 
					idx, reg);
 1054 
					idx, reg);
1055 
			r100_cs_dump_packet(p, pkt);
 1055 
			radeon_cs_dump_packet(p, pkt);
1056 
			return r;
 1056 
			return r;
1057 
		}
 1057 
		}
1058 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 1058 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1059 
		break;
 1059 
		break;
1060 
	case 0x4e0c:
 1060 
	case 0x4e0c:
1061 
		/* RB3D_COLOR_CHANNEL_MASK */
 1061 
		/* RB3D_COLOR_CHANNEL_MASK */
1062 
		track->color_channel_mask = idx_value;
 1062 
		track->color_channel_mask = idx_value;
1063 
		track->cb_dirty = true;
 1063 
		track->cb_dirty = true;
1064 
		break;
 1064 
		break;
1065 
	case 0x43a4:
 1065 
	case 0x43a4:
1066 
		/* SC_HYPERZ_EN */
 1066 
		/* SC_HYPERZ_EN */
1067 
		/* r300c emits this register - we need to disable hyperz for it
 1067 
		/* r300c emits this register - we need to disable hyperz for it
1068 
		 * without complaining */
 1068 
		 * without complaining */
1069 
		if (p->rdev->hyperz_filp != p->filp) {
 1069 
		if (p->rdev->hyperz_filp != p->filp) {
1070 
			if (idx_value & 0x1)
 1070 
			if (idx_value & 0x1)
1071 
				ib[idx] = idx_value & ~1;
 1071 
				ib[idx] = idx_value & ~1;
1072 
		}
 1072 
		}
1073 
		break;
 1073 
		break;
1074 
	case 0x4f1c:
 1074 
	case 0x4f1c:
1075 
		/* ZB_BW_CNTL */
 1075 
		/* ZB_BW_CNTL */
1076 
		track->zb_cb_clear = !!(idx_value & (1 << 5));
 1076 
		track->zb_cb_clear = !!(idx_value & (1 << 5));
1077 
		track->cb_dirty = true;
 1077 
		track->cb_dirty = true;
1078 
		track->zb_dirty = true;
 1078 
		track->zb_dirty = true;
1079 
		if (p->rdev->hyperz_filp != p->filp) {
 1079 
		if (p->rdev->hyperz_filp != p->filp) {
1080 
			if (idx_value & (R300_HIZ_ENABLE |
 1080 
			if (idx_value & (R300_HIZ_ENABLE |
1081 
					 R300_RD_COMP_ENABLE |
 1081 
					 R300_RD_COMP_ENABLE |
1082 
					 R300_WR_COMP_ENABLE |
 1082 
					 R300_WR_COMP_ENABLE |
1083 
					 R300_FAST_FILL_ENABLE))
 1083 
					 R300_FAST_FILL_ENABLE))
1084 
				goto fail;
 1084 
				goto fail;
1085 
		}
 1085 
		}
1086 
		break;
 1086 
		break;
1087 
	case 0x4e04:
 1087 
	case 0x4e04:
1088 
		/* RB3D_BLENDCNTL */
 1088 
		/* RB3D_BLENDCNTL */
1089 
		track->blend_read_enable = !!(idx_value & (1 << 2));
 1089 
		track->blend_read_enable = !!(idx_value & (1 << 2));
1090 
		track->cb_dirty = true;
 1090 
		track->cb_dirty = true;
1091 
		break;
 1091 
		break;
1092 
	case R300_RB3D_AARESOLVE_OFFSET:
 1092 
	case R300_RB3D_AARESOLVE_OFFSET:
1093 
		r = r100_cs_packet_next_reloc(p, &reloc);
 1093 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1094 
		if (r) {
 1094 
		if (r) {
1095 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 1095 
			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1096 
				  idx, reg);
 1096 
				  idx, reg);
1097 
			r100_cs_dump_packet(p, pkt);
 1097 
			radeon_cs_dump_packet(p, pkt);
1098 
			return r;
 1098 
			return r;
1099 
		}
 1099 
		}
1100 
		track->aa.robj = reloc->robj;
 1100 
		track->aa.robj = reloc->robj;
1101 
		track->aa.offset = idx_value;
 1101 
		track->aa.offset = idx_value;
1102 
		track->aa_dirty = true;
 1102 
		track->aa_dirty = true;
1103 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 1103 
		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1104 
		break;
 1104 
		break;
1105 
	case R300_RB3D_AARESOLVE_PITCH:
 1105 
	case R300_RB3D_AARESOLVE_PITCH:
1106 
		track->aa.pitch = idx_value & 0x3FFE;
 1106 
		track->aa.pitch = idx_value & 0x3FFE;
1107 
		track->aa_dirty = true;
 1107 
		track->aa_dirty = true;
1108 
		break;
 1108 
		break;
1109 
	case R300_RB3D_AARESOLVE_CTL:
 1109 
	case R300_RB3D_AARESOLVE_CTL:
1110 
		track->aaresolve = idx_value & 0x1;
 1110 
		track->aaresolve = idx_value & 0x1;
1111 
		track->aa_dirty = true;
 1111 
		track->aa_dirty = true;
1112 
		break;
 1112 
		break;
1113 
	case 0x4f30: /* ZB_MASK_OFFSET */
 1113 
	case 0x4f30: /* ZB_MASK_OFFSET */
1114 
	case 0x4f34: /* ZB_ZMASK_PITCH */
 1114 
	case 0x4f34: /* ZB_ZMASK_PITCH */
1115 
	case 0x4f44: /* ZB_HIZ_OFFSET */
 1115 
	case 0x4f44: /* ZB_HIZ_OFFSET */
1116 
	case 0x4f54: /* ZB_HIZ_PITCH */
 1116 
	case 0x4f54: /* ZB_HIZ_PITCH */
1117 
		if (idx_value && (p->rdev->hyperz_filp != p->filp))
 1117 
		if (idx_value && (p->rdev->hyperz_filp != p->filp))
1118 
			goto fail;
 1118 
			goto fail;
1119 
		break;
 1119 
		break;
1120 
	case 0x4028:
 1120 
	case 0x4028:
1121 
		if (idx_value && (p->rdev->hyperz_filp != p->filp))
 1121 
		if (idx_value && (p->rdev->hyperz_filp != p->filp))
1122 
			goto fail;
 1122 
			goto fail;
1123 
		/* GB_Z_PEQ_CONFIG */
 1123 
		/* GB_Z_PEQ_CONFIG */
1124 
		if (p->rdev->family >= CHIP_RV350)
 1124 
		if (p->rdev->family >= CHIP_RV350)
1125 
			break;
 1125 
			break;
1126 
		goto fail;
 1126 
		goto fail;
1127 
		break;
 1127 
		break;
1128 
	case 0x4be8:
 1128 
	case 0x4be8:
1129 
		/* valid register only on RV530 */
 1129 
		/* valid register only on RV530 */
1130 
		if (p->rdev->family == CHIP_RV530)
 1130 
		if (p->rdev->family == CHIP_RV530)
1131 
			break;
 1131 
			break;
1132 
		/* fallthrough do not move */
 1132 
		/* fallthrough do not move */
1133 
	default:
 1133 
	default:
1134 
		goto fail;
 1134 
		goto fail;
1135 
	}
 1135 
	}
1136 
	return 0;
 1136 
	return 0;
1137 
fail:
 1137 
fail:
1138 
	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
 1138 
	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1139 
	       reg, idx, idx_value);
 1139 
	       reg, idx, idx_value);
1140 
		return -EINVAL;
 1140 
		return -EINVAL;
1141 
}
 1141 
}
1142 
 
 1142 
 
1143 
static int r300_packet3_check(struct radeon_cs_parser *p,
 1143 
static int r300_packet3_check(struct radeon_cs_parser *p,
1144 
			      struct radeon_cs_packet *pkt)
 1144 
			      struct radeon_cs_packet *pkt)
1145 
{
 1145 
{
1146 
	struct radeon_cs_reloc *reloc;
 1146 
	struct radeon_cs_reloc *reloc;
1147 
	struct r100_cs_track *track;
 1147 
	struct r100_cs_track *track;
1148 
	volatile uint32_t *ib;
 1148 
	volatile uint32_t *ib;
1149 
	unsigned idx;
 1149 
	unsigned idx;
1150 
	int r;
 1150 
	int r;
1151 
 
 1151 
 
1152 
	ib = p->ib.ptr;
 1152 
	ib = p->ib.ptr;
1153 
	idx = pkt->idx + 1;
 1153 
	idx = pkt->idx + 1;
1154 
	track = (struct r100_cs_track *)p->track;
 1154 
	track = (struct r100_cs_track *)p->track;
1155 
	switch(pkt->opcode) {
 1155 
	switch(pkt->opcode) {
1156 
	case PACKET3_3D_LOAD_VBPNTR:
 1156 
	case PACKET3_3D_LOAD_VBPNTR:
1157 
		r = r100_packet3_load_vbpntr(p, pkt, idx);
 1157 
		r = r100_packet3_load_vbpntr(p, pkt, idx);
1158 
		if (r)
 1158 
		if (r)
1159 
				return r;
 1159 
				return r;
1160 
		break;
 1160 
		break;
1161 
	case PACKET3_INDX_BUFFER:
 1161 
	case PACKET3_INDX_BUFFER:
1162 
		r = r100_cs_packet_next_reloc(p, &reloc);
 1162 
		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1163 
		if (r) {
 1163 
		if (r) {
1164 
			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
 1164 
			DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1165 
			r100_cs_dump_packet(p, pkt);
 1165 
			radeon_cs_dump_packet(p, pkt);
1166 
			return r;
 1166 
			return r;
1167 
		}
 1167 
		}
1168 
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 1168 
		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1169 
		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
 1169 
		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1170 
		if (r) {
 1170 
		if (r) {
1171 
			return r;
 1171 
			return r;
1172 
		}
 1172 
		}
1173 
		break;
 1173 
		break;
1174 
	/* Draw packet */
 1174 
	/* Draw packet */
1175 
	case PACKET3_3D_DRAW_IMMD:
 1175 
	case PACKET3_3D_DRAW_IMMD:
1176 
		/* Number of dwords is vtx_size * (num_vertices - 1)
 1176 
		/* Number of dwords is vtx_size * (num_vertices - 1)
1177 
		 * PRIM_WALK must be equal to 3 vertex data in embedded
 1177 
		 * PRIM_WALK must be equal to 3 vertex data in embedded
1178 
		 * in cmd stream */
 1178 
		 * in cmd stream */
1179 
		if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
 1179 
		if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1180 
			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
 1180 
			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1181 
			return -EINVAL;
 1181 
			return -EINVAL;
1182 
		}
 1182 
		}
1183 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
 1183 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1184 
		track->immd_dwords = pkt->count - 1;
 1184 
		track->immd_dwords = pkt->count - 1;
1185 
		r = r100_cs_track_check(p->rdev, track);
 1185 
		r = r100_cs_track_check(p->rdev, track);
1186 
		if (r) {
 1186 
		if (r) {
1187 
			return r;
 1187 
			return r;
1188 
		}
 1188 
		}
1189 
		break;
 1189 
		break;
1190 
	case PACKET3_3D_DRAW_IMMD_2:
 1190 
	case PACKET3_3D_DRAW_IMMD_2:
1191 
		/* Number of dwords is vtx_size * (num_vertices - 1)
 1191 
		/* Number of dwords is vtx_size * (num_vertices - 1)
1192 
		 * PRIM_WALK must be equal to 3 vertex data in embedded
 1192 
		 * PRIM_WALK must be equal to 3 vertex data in embedded
1193 
		 * in cmd stream */
 1193 
		 * in cmd stream */
1194 
		if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
 1194 
		if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1195 
			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
 1195 
			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1196 
			return -EINVAL;
 1196 
			return -EINVAL;
1197 
		}
 1197 
		}
1198 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
 1198 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1199 
		track->immd_dwords = pkt->count;
 1199 
		track->immd_dwords = pkt->count;
1200 
		r = r100_cs_track_check(p->rdev, track);
 1200 
		r = r100_cs_track_check(p->rdev, track);
1201 
		if (r) {
 1201 
		if (r) {
1202 
			return r;
 1202 
			return r;
1203 
		}
 1203 
		}
1204 
		break;
 1204 
		break;
1205 
	case PACKET3_3D_DRAW_VBUF:
 1205 
	case PACKET3_3D_DRAW_VBUF:
1206 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
 1206 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1207 
		r = r100_cs_track_check(p->rdev, track);
 1207 
		r = r100_cs_track_check(p->rdev, track);
1208 
		if (r) {
 1208 
		if (r) {
1209 
			return r;
 1209 
			return r;
1210 
		}
 1210 
		}
1211 
		break;
 1211 
		break;
1212 
	case PACKET3_3D_DRAW_VBUF_2:
 1212 
	case PACKET3_3D_DRAW_VBUF_2:
1213 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
 1213 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1214 
		r = r100_cs_track_check(p->rdev, track);
 1214 
		r = r100_cs_track_check(p->rdev, track);
1215 
		if (r) {
 1215 
		if (r) {
1216 
			return r;
 1216 
			return r;
1217 
		}
 1217 
		}
1218 
		break;
 1218 
		break;
1219 
	case PACKET3_3D_DRAW_INDX:
 1219 
	case PACKET3_3D_DRAW_INDX:
1220 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
 1220 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1221 
		r = r100_cs_track_check(p->rdev, track);
 1221 
		r = r100_cs_track_check(p->rdev, track);
1222 
		if (r) {
 1222 
		if (r) {
1223 
			return r;
 1223 
			return r;
1224 
		}
 1224 
		}
1225 
		break;
 1225 
		break;
1226 
	case PACKET3_3D_DRAW_INDX_2:
 1226 
	case PACKET3_3D_DRAW_INDX_2:
1227 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
 1227 
		track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1228 
		r = r100_cs_track_check(p->rdev, track);
 1228 
		r = r100_cs_track_check(p->rdev, track);
1229 
		if (r) {
 1229 
		if (r) {
1230 
			return r;
 1230 
			return r;
1231 
		}
 1231 
		}
1232 
		break;
 1232 
		break;
1233 
	case PACKET3_3D_CLEAR_HIZ:
 1233 
	case PACKET3_3D_CLEAR_HIZ:
1234 
	case PACKET3_3D_CLEAR_ZMASK:
 1234 
	case PACKET3_3D_CLEAR_ZMASK:
1235 
		if (p->rdev->hyperz_filp != p->filp)
 1235 
		if (p->rdev->hyperz_filp != p->filp)
1236 
			return -EINVAL;
 1236 
			return -EINVAL;
1237 
		break;
 1237 
		break;
1238 
	case PACKET3_3D_CLEAR_CMASK:
 1238 
	case PACKET3_3D_CLEAR_CMASK:
1239 
		if (p->rdev->cmask_filp != p->filp)
 1239 
		if (p->rdev->cmask_filp != p->filp)
1240 
			return -EINVAL;
 1240 
			return -EINVAL;
1241 
		break;
 1241 
		break;
1242 
	case PACKET3_NOP:
 1242 
	case PACKET3_NOP:
1243 
		break;
 1243 
		break;
1244 
	default:
 1244 
	default:
1245 
		DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
 1245 
		DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1246 
		return -EINVAL;
 1246 
		return -EINVAL;
1247 
	}
 1247 
	}
1248 
	return 0;
 1248 
	return 0;
1249 
}
 1249 
}
1250 
 
 1250 
 
1251 
int r300_cs_parse(struct radeon_cs_parser *p)
 1251 
int r300_cs_parse(struct radeon_cs_parser *p)
1252 
{
 1252 
{
1253 
	struct radeon_cs_packet pkt;
 1253 
	struct radeon_cs_packet pkt;
1254 
	struct r100_cs_track *track;
 1254 
	struct r100_cs_track *track;
1255 
	int r;
 1255 
	int r;
1256 
 
 1256 
 
1257 
	track = kzalloc(sizeof(*track), GFP_KERNEL);
 1257 
	track = kzalloc(sizeof(*track), GFP_KERNEL);
1258 
	if (track == NULL)
 1258 
	if (track == NULL)
1259 
		return -ENOMEM;
 1259 
		return -ENOMEM;
1260 
	r100_cs_track_clear(p->rdev, track);
 1260 
	r100_cs_track_clear(p->rdev, track);
1261 
	p->track = track;
 1261 
	p->track = track;
1262 
	do {
 1262 
	do {
1263 
		r = r100_cs_packet_parse(p, &pkt, p->idx);
 1263 
		r = radeon_cs_packet_parse(p, &pkt, p->idx);
1264 
		if (r) {
 1264 
		if (r) {
1265 
			return r;
 1265 
			return r;
1266 
		}
 1266 
		}
1267 
		p->idx += pkt.count + 2;
 1267 
		p->idx += pkt.count + 2;
1268 
		switch (pkt.type) {
 1268 
		switch (pkt.type) {
1269 
		case PACKET_TYPE0:
 1269 
		case RADEON_PACKET_TYPE0:
1270 
			r = r100_cs_parse_packet0(p, &pkt,
 1270 
			r = r100_cs_parse_packet0(p, &pkt,
1271 
						  p->rdev->config.r300.reg_safe_bm,
 1271 
						  p->rdev->config.r300.reg_safe_bm,
1272 
						  p->rdev->config.r300.reg_safe_bm_size,
 1272 
						  p->rdev->config.r300.reg_safe_bm_size,
1273 
						  &r300_packet0_check);
 1273 
						  &r300_packet0_check);
1274 
			break;
 1274 
			break;
1275 
		case PACKET_TYPE2:
 1275 
		case RADEON_PACKET_TYPE2:
1276 
			break;
 1276 
			break;
1277 
		case PACKET_TYPE3:
 1277 
		case RADEON_PACKET_TYPE3:
1278 
			r = r300_packet3_check(p, &pkt);
 1278 
			r = r300_packet3_check(p, &pkt);
1279 
			break;
 1279 
			break;
1280 
		default:
 1280 
		default:
1281 
			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 1281 
			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1282 
			return -EINVAL;
 1282 
			return -EINVAL;
1283 
		}
 1283 
		}
1284 
		if (r) {
 1284 
		if (r) {
1285 
			return r;
 1285 
			return r;
1286 
		}
 1286 
		}
1287 
	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 1287 
	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1288 
	return 0;
 1288 
	return 0;
1289 
}
 1289 
}
1290 
#endif
 1290 
#endif
1291 
 
 1291 
 
1292 
 
 1292 
 
1293 
void r300_set_reg_safe(struct radeon_device *rdev)
 1293 
void r300_set_reg_safe(struct radeon_device *rdev)
1294 
{
 1294 
{
1295 
	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
 1295 
	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1296 
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
 1296 
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1297 
}
 1297 
}
1298 
 
 1298 
 
1299 
void r300_mc_program(struct radeon_device *rdev)
 1299 
void r300_mc_program(struct radeon_device *rdev)
1300 
{
 1300 
{
1301 
	struct r100_mc_save save;
 1301 
	struct r100_mc_save save;
1302 
	int r;
 1302 
	int r;
1303 
 
 1303 
 
1304 
	r = r100_debugfs_mc_info_init(rdev);
 1304 
	r = r100_debugfs_mc_info_init(rdev);
1305 
	if (r) {
 1305 
	if (r) {
1306 
		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
 1306 
		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1307 
	}
 1307 
	}
1308 
 
 1308 
 
1309 
	/* Stops all mc clients */
 1309 
	/* Stops all mc clients */
1310 
	r100_mc_stop(rdev, &save);
 1310 
	r100_mc_stop(rdev, &save);
1311 
	if (rdev->flags & RADEON_IS_AGP) {
 1311 
	if (rdev->flags & RADEON_IS_AGP) {
1312 
		WREG32(R_00014C_MC_AGP_LOCATION,
 1312 
		WREG32(R_00014C_MC_AGP_LOCATION,
1313 
			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 1313 
			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1314 
			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 1314 
			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1315 
		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 1315 
		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1316 
		WREG32(R_00015C_AGP_BASE_2,
 1316 
		WREG32(R_00015C_AGP_BASE_2,
1317 
			upper_32_bits(rdev->mc.agp_base) & 0xff);
 1317 
			upper_32_bits(rdev->mc.agp_base) & 0xff);
1318 
	} else {
 1318 
	} else {
1319 
		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
 1319 
		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1320 
		WREG32(R_000170_AGP_BASE, 0);
 1320 
		WREG32(R_000170_AGP_BASE, 0);
1321 
		WREG32(R_00015C_AGP_BASE_2, 0);
 1321 
		WREG32(R_00015C_AGP_BASE_2, 0);
1322 
	}
 1322 
	}
1323 
	/* Wait for mc idle */
 1323 
	/* Wait for mc idle */
1324 
	if (r300_mc_wait_for_idle(rdev))
 1324 
	if (r300_mc_wait_for_idle(rdev))
1325 
		DRM_INFO("Failed to wait MC idle before programming MC.\n");
 1325 
		DRM_INFO("Failed to wait MC idle before programming MC.\n");
1326 
	/* Program MC, should be a 32bits limited address space */
 1326 
	/* Program MC, should be a 32bits limited address space */
1327 
	WREG32(R_000148_MC_FB_LOCATION,
 1327 
	WREG32(R_000148_MC_FB_LOCATION,
1328 
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
 1328 
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1329 
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
 1329 
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1330 
	r100_mc_resume(rdev, &save);
 1330 
	r100_mc_resume(rdev, &save);
1331 
}
 1331 
}
1332 
 
 1332 
 
1333 
void r300_clock_startup(struct radeon_device *rdev)
 1333 
void r300_clock_startup(struct radeon_device *rdev)
1334 
{
 1334 
{
1335 
	u32 tmp;
 1335 
	u32 tmp;
1336 
 
 1336 
 
1337 
	if (radeon_dynclks != -1 && radeon_dynclks)
 1337 
	if (radeon_dynclks != -1 && radeon_dynclks)
1338 
		radeon_legacy_set_clock_gating(rdev, 1);
 1338 
		radeon_legacy_set_clock_gating(rdev, 1);
1339 
	/* We need to force on some of the block */
 1339 
	/* We need to force on some of the block */
1340 
	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
 1340 
	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1341 
	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 1341 
	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1342 
	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
 1342 
	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1343 
		tmp |= S_00000D_FORCE_VAP(1);
 1343 
		tmp |= S_00000D_FORCE_VAP(1);
1344 
	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
 1344 
	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1345 
}
 1345 
}
1346 
 
 1346 
 
1347 
static int r300_startup(struct radeon_device *rdev)
 1347 
static int r300_startup(struct radeon_device *rdev)
1348 
{
 1348 
{
1349 
	int r;
 1349 
	int r;
1350 
 
 1350 
 
1351 
	/* set common regs */
 1351 
	/* set common regs */
1352 
	r100_set_common_regs(rdev);
 1352 
	r100_set_common_regs(rdev);
1353 
	/* program mc */
 1353 
	/* program mc */
1354 
	r300_mc_program(rdev);
 1354 
	r300_mc_program(rdev);
1355 
	/* Resume clock */
 1355 
	/* Resume clock */
1356 
	r300_clock_startup(rdev);
 1356 
	r300_clock_startup(rdev);
1357 
	/* Initialize GPU configuration (# pipes, ...) */
 1357 
	/* Initialize GPU configuration (# pipes, ...) */
1358 
	r300_gpu_init(rdev);
 1358 
	r300_gpu_init(rdev);
1359 
	/* Initialize GART (initialize after TTM so we can allocate
 1359 
	/* Initialize GART (initialize after TTM so we can allocate
1360 
	 * memory through TTM but finalize after TTM) */
 1360 
	 * memory through TTM but finalize after TTM) */
1361 
	if (rdev->flags & RADEON_IS_PCIE) {
 1361 
	if (rdev->flags & RADEON_IS_PCIE) {
1362 
		r = rv370_pcie_gart_enable(rdev);
 1362 
		r = rv370_pcie_gart_enable(rdev);
1363 
		if (r)
 1363 
		if (r)
1364 
			return r;
 1364 
			return r;
1365 
	}
 1365 
	}
1366 
 
 1366 
 
1367 
	if (rdev->family == CHIP_R300 ||
 1367 
	if (rdev->family == CHIP_R300 ||
1368 
	    rdev->family == CHIP_R350 ||
 1368 
	    rdev->family == CHIP_R350 ||
1369 
	    rdev->family == CHIP_RV350)
 1369 
	    rdev->family == CHIP_RV350)
1370 
		r100_enable_bm(rdev);
 1370 
		r100_enable_bm(rdev);
1371 
 
 1371 
 
1372 
	if (rdev->flags & RADEON_IS_PCI) {
 1372 
	if (rdev->flags & RADEON_IS_PCI) {
1373 
		r = r100_pci_gart_enable(rdev);
 1373 
		r = r100_pci_gart_enable(rdev);
1374 
		if (r)
 1374 
		if (r)
1375 
			return r;
 1375 
			return r;
1376 
	}
 1376 
	}
1377 
 
 1377 
 
1378 
	/* allocate wb buffer */
 1378 
	/* allocate wb buffer */
1379 
	r = radeon_wb_init(rdev);
 1379 
	r = radeon_wb_init(rdev);
1380 
	if (r)
 1380 
	if (r)
1381 
		return r;
 1381 
		return r;
1382 
 
 1382 
 
1383 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 1383 
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1384 
	if (r) {
 1384 
	if (r) {
1385 
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 1385 
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1386 
		return r;
 1386 
		return r;
1387 
	}
 1387 
	}
1388 
 
 1388 
 
1389 
	/* Enable IRQ */
 1389 
	/* Enable IRQ */
- 
 
 1390 
	if (!rdev->irq.installed) {
- 
 
 1391 
		r = radeon_irq_kms_init(rdev);
- 
 
 1392 
		if (r)
- 
 
 1393 
			return r;
- 
 
 1394 
	}
- 
 
 1395 
 
1390 
	r100_irq_set(rdev);
 1396 
	r100_irq_set(rdev);
1391 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 1397 
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1392 
	/* 1M ring buffer */
 1398 
	/* 1M ring buffer */
1393 
    r = r100_cp_init(rdev, 1024 * 1024);
 1399 
    r = r100_cp_init(rdev, 1024 * 1024);
1394 
    if (r) {
 1400 
    if (r) {
1395 
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 1401 
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1396 
       return r;
 1402 
       return r;
1397 
    }
 1403 
    }
1398 
 
 1404 
 
1399 
	r = radeon_ib_pool_init(rdev);
 1405 
	r = radeon_ib_pool_init(rdev);
1400 
	if (r) {
 1406 
	if (r) {
1401 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 1407 
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1402 
		return r;
 1408 
		return r;
1403 
	}
 1409 
	}
1404 
 
 1410 
 
1405 
	return 0;
 1411 
	return 0;
1406 
}
 1412 
}
1407 
 
 1413 
 
1408 
 
 1414 
 
1409 
 
 1415 
 
1410 
 
 1416 
 
1411 
 
 1417 
 
1412 
int r300_init(struct radeon_device *rdev)
 1418 
int r300_init(struct radeon_device *rdev)
1413 
{
 1419 
{
1414 
	int r;
 1420 
	int r;
1415 
 
 1421 
 
1416 
	/* Disable VGA */
 1422 
	/* Disable VGA */
1417 
	r100_vga_render_disable(rdev);
 1423 
	r100_vga_render_disable(rdev);
1418 
	/* Initialize scratch registers */
 1424 
	/* Initialize scratch registers */
1419 
	radeon_scratch_init(rdev);
 1425 
	radeon_scratch_init(rdev);
1420 
	/* Initialize surface registers */
 1426 
	/* Initialize surface registers */
1421 
	radeon_surface_init(rdev);
 1427 
	radeon_surface_init(rdev);
1422 
	/* TODO: disable VGA need to use VGA request */
 1428 
	/* TODO: disable VGA need to use VGA request */
1423 
	/* restore some register to sane defaults */
 1429 
	/* restore some register to sane defaults */
1424 
	r100_restore_sanity(rdev);
 1430 
	r100_restore_sanity(rdev);
1425 
	/* BIOS*/
 1431 
	/* BIOS*/
1426 
	if (!radeon_get_bios(rdev)) {
 1432 
	if (!radeon_get_bios(rdev)) {
1427 
		if (ASIC_IS_AVIVO(rdev))
 1433 
		if (ASIC_IS_AVIVO(rdev))
1428 
			return -EINVAL;
 1434 
			return -EINVAL;
1429 
	}
 1435 
	}
1430 
	if (rdev->is_atom_bios) {
 1436 
	if (rdev->is_atom_bios) {
1431 
		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
 1437 
		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1432 
		return -EINVAL;
 1438 
		return -EINVAL;
1433 
	} else {
 1439 
	} else {
1434 
		r = radeon_combios_init(rdev);
 1440 
		r = radeon_combios_init(rdev);
1435 
		if (r)
 1441 
		if (r)
1436 
			return r;
 1442 
			return r;
1437 
	}
 1443 
	}
1438 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
 1444 
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1439 
	if (radeon_asic_reset(rdev)) {
 1445 
	if (radeon_asic_reset(rdev)) {
1440 
		dev_warn(rdev->dev,
 1446 
		dev_warn(rdev->dev,
1441 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 1447 
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1442 
			RREG32(R_000E40_RBBM_STATUS),
 1448 
			RREG32(R_000E40_RBBM_STATUS),
1443 
			RREG32(R_0007C0_CP_STAT));
 1449 
			RREG32(R_0007C0_CP_STAT));
1444 
	}
 1450 
	}
1445 
	/* check if cards are posted or not */
 1451 
	/* check if cards are posted or not */
1446 
	if (radeon_boot_test_post_card(rdev) == false)
 1452 
	if (radeon_boot_test_post_card(rdev) == false)
1447 
		return -EINVAL;
 1453 
		return -EINVAL;
1448 
	/* Set asic errata */
 1454 
	/* Set asic errata */
1449 
	r300_errata(rdev);
 1455 
	r300_errata(rdev);
1450 
	/* Initialize clocks */
 1456 
	/* Initialize clocks */
1451 
	radeon_get_clock_info(rdev->ddev);
 1457 
	radeon_get_clock_info(rdev->ddev);
1452 
	/* initialize AGP */
 1458 
	/* initialize AGP */
1453 
	if (rdev->flags & RADEON_IS_AGP) {
 1459 
	if (rdev->flags & RADEON_IS_AGP) {
1454 
		r = radeon_agp_init(rdev);
 1460 
		r = radeon_agp_init(rdev);
1455 
		if (r) {
 1461 
		if (r) {
1456 
			radeon_agp_disable(rdev);
 1462 
			radeon_agp_disable(rdev);
1457 
		}
 1463 
		}
1458 
	}
 1464 
	}
1459 
	/* initialize memory controller */
 1465 
	/* initialize memory controller */
1460 
	r300_mc_init(rdev);
 1466 
	r300_mc_init(rdev);
1461 
	/* Fence driver */
 1467 
	/* Fence driver */
1462 
	r = radeon_fence_driver_init(rdev);
 1468 
	r = radeon_fence_driver_init(rdev);
1463 
	if (r)
 1469 
	if (r)
1464 
		return r;
 - 
 
1465 
	r = radeon_irq_kms_init(rdev);
 - 
 
1466 
	if (r)
 - 
 
1467 
		return r;
 1470 
		return r;
1468 
	/* Memory manager */
 1471 
	/* Memory manager */
1469 
	r = radeon_bo_init(rdev);
 1472 
	r = radeon_bo_init(rdev);
1470 
	if (r)
 1473 
	if (r)
1471 
		return r;
 1474 
		return r;
1472 
	if (rdev->flags & RADEON_IS_PCIE) {
 1475 
	if (rdev->flags & RADEON_IS_PCIE) {
1473 
		r = rv370_pcie_gart_init(rdev);
 1476 
		r = rv370_pcie_gart_init(rdev);
1474 
		if (r)
 1477 
		if (r)
1475 
			return r;
 1478 
			return r;
1476 
	}
 1479 
	}
1477 
	if (rdev->flags & RADEON_IS_PCI) {
 1480 
	if (rdev->flags & RADEON_IS_PCI) {
1478 
		r = r100_pci_gart_init(rdev);
 1481 
		r = r100_pci_gart_init(rdev);
1479 
		if (r)
 1482 
		if (r)
1480 
			return r;
 1483 
			return r;
1481 
	}
 1484 
	}
1482 
	r300_set_reg_safe(rdev);
 1485 
	r300_set_reg_safe(rdev);
1483 
 
 1486 
 
1484 
	rdev->accel_working = true;
 1487 
	rdev->accel_working = true;
1485 
	r = r300_startup(rdev);
 1488 
	r = r300_startup(rdev);
1486 
	if (r) {
 1489 
	if (r) {
1487 
		/* Somethings want wront with the accel init stop accel */
 1490 
		/* Somethings want wront with the accel init stop accel */
1488 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
 1491 
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
1489 
		if (rdev->flags & RADEON_IS_PCIE)
 1492 
		if (rdev->flags & RADEON_IS_PCIE)
1490 
			rv370_pcie_gart_fini(rdev);
 1493 
			rv370_pcie_gart_fini(rdev);
1491 
		if (rdev->flags & RADEON_IS_PCI)
 1494 
		if (rdev->flags & RADEON_IS_PCI)
1492 
			r100_pci_gart_fini(rdev);
 1495 
			r100_pci_gart_fini(rdev);
1493 
		rdev->accel_working = false;
 1496 
		rdev->accel_working = false;
1494 
	}
 1497 
	}
1495 
	return 0;
 1498 
	return 0;
1496 
}
 1499 
}